From a8df952dd38cb686c6a795480630649aa51fd894 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Tue, 22 Jul 2008 17:00:18 -0400
Subject: tests: update config.ini and stdout for the various tests. These
 files were a bit too out of date and resulted in a bit of confusion.

---
 .../00.gzip/ref/alpha/tru64/o3-timing/config.ini   |  2 +
 .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout  | 14 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../00.gzip/ref/alpha/tru64/simple-atomic/stdout   | 14 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../00.gzip/ref/alpha/tru64/simple-timing/stdout   | 14 +++++
 .../00.gzip/ref/sparc/linux/o3-timing/config.ini   |  2 +
 .../long/00.gzip/ref/sparc/linux/o3-timing/stdout  | 26 ++++----
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../00.gzip/ref/sparc/linux/simple-atomic/stdout   | 26 ++++----
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../00.gzip/ref/sparc/linux/simple-timing/stdout   | 26 ++++----
 .../00.gzip/ref/x86/linux/simple-atomic/config.ini |  4 +-
 .../00.gzip/ref/x86/linux/simple-atomic/stdout     | 26 ++++----
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../10.mcf/ref/sparc/linux/simple-atomic/stdout    | 26 ++++----
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../10.mcf/ref/sparc/linux/simple-timing/stdout    | 26 ++++----
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |  4 +-
 .../long/10.mcf/ref/x86/linux/simple-atomic/stdout | 26 ++++----
 .../ref/x86/linux/simple-atomic/config.ini         |  4 +-
 .../20.parser/ref/x86/linux/simple-atomic/stdout   | 28 +++++----
 .../30.eon/ref/alpha/tru64/o3-timing/config.ini    |  2 +
 tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 14 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../30.eon/ref/alpha/tru64/simple-atomic/stdout    | 14 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../30.eon/ref/alpha/tru64/simple-timing/stdout    | 14 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../ref/alpha/tru64/simple-atomic/stdout           | 14 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../ref/alpha/tru64/simple-timing/stdout           | 14 +++++
 .../50.vortex/ref/alpha/tru64/o3-timing/config.ini |  2 +
 .../50.vortex/ref/alpha/tru64/o3-timing/stdout     | 14 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../50.vortex/ref/alpha/tru64/simple-atomic/stdout | 14 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 14 +++++
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../50.vortex/ref/sparc/linux/simple-atomic/stdout | 10 +--
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../50.vortex/ref/sparc/linux/simple-timing/stdout |  8 ++-
 .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini  |  2 +
 .../long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 14 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../60.bzip2/ref/alpha/tru64/simple-atomic/stdout  | 14 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../60.bzip2/ref/alpha/tru64/simple-timing/stdout  | 14 +++++
 .../ref/x86/linux/simple-atomic/config.ini         |  4 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/stdout    | 26 ++++----
 .../70.twolf/ref/alpha/tru64/o3-timing/config.ini  |  2 +
 .../long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 16 +++++
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../70.twolf/ref/alpha/tru64/simple-atomic/stdout  | 16 +++++
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../70.twolf/ref/alpha/tru64/simple-timing/stdout  | 16 +++++
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../70.twolf/ref/sparc/linux/simple-atomic/stdout  | 30 +++++----
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../70.twolf/ref/sparc/linux/simple-timing/stdout  | 32 +++++-----
 .../ref/x86/linux/simple-atomic/config.ini         |  4 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stdout    | 30 +++++----
 .../sparc/solaris/t1000-simple-atomic/config.ini   | 37 +++++++----
 .../ref/sparc/solaris/t1000-simple-atomic/stdout   | 10 +--
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  |  3 +
 .../00.hello/ref/alpha/linux/o3-timing/stdout      |  8 ++-
 .../ref/alpha/linux/simple-atomic/config.ini       |  8 ++-
 .../00.hello/ref/alpha/linux/simple-atomic/stdout  | 12 ++--
 .../ref/alpha/linux/simple-timing/config.ini       |  3 +
 .../00.hello/ref/alpha/linux/simple-timing/stdout  | 10 +--
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  |  3 +
 .../00.hello/ref/alpha/tru64/o3-timing/stdout      |  8 ++-
 .../ref/alpha/tru64/simple-atomic/config.ini       |  8 ++-
 .../00.hello/ref/alpha/tru64/simple-atomic/stdout  | 12 ++--
 .../ref/alpha/tru64/simple-timing/config.ini       |  3 +
 .../00.hello/ref/alpha/tru64/simple-timing/stdout  | 10 +--
 .../ref/mips/linux/simple-atomic/config.ini        | 72 +++++++++++++++++++++-
 .../00.hello/ref/mips/linux/simple-atomic/stdout   | 12 ++--
 .../ref/mips/linux/simple-timing/config.ini        |  3 +
 .../00.hello/ref/mips/linux/simple-timing/stdout   | 10 +--
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../00.hello/ref/sparc/linux/simple-atomic/stdout  | 14 +++--
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../00.hello/ref/sparc/linux/simple-timing/stdout  | 12 ++--
 .../ref/x86/linux/simple-atomic/config.ini         |  4 +-
 .../00.hello/ref/x86/linux/simple-atomic/stdout    | 10 +--
 .../ref/alpha/linux/o3-timing/config.ini           |  4 ++
 .../ref/alpha/linux/o3-timing/stdout               | 10 +--
 .../ref/sparc/linux/o3-timing/config.ini           |  3 +
 .../02.insttest/ref/sparc/linux/o3-timing/stdout   | 26 ++++----
 .../ref/sparc/linux/simple-atomic/config.ini       |  7 ++-
 .../ref/sparc/linux/simple-atomic/stdout           | 26 ++++----
 .../ref/sparc/linux/simple-timing/config.ini       |  3 +
 .../ref/sparc/linux/simple-timing/stdout           | 26 ++++----
 .../linux/tsunami-simple-atomic-dual/config.ini    | 56 +++++++++--------
 .../alpha/linux/tsunami-simple-atomic-dual/stdout  |  8 ++-
 .../alpha/linux/tsunami-simple-atomic/config.ini   | 53 ++++++++--------
 .../ref/alpha/linux/tsunami-simple-atomic/stdout   |  8 ++-
 .../linux/tsunami-simple-timing-dual/config.ini    | 47 +++++++-------
 .../alpha/linux/tsunami-simple-timing-dual/stdout  |  6 +-
 .../alpha/linux/tsunami-simple-timing/config.ini   | 47 +++++++-------
 .../ref/alpha/linux/tsunami-simple-timing/stdout   |  8 ++-
 .../ref/alpha/eio/simple-atomic/config.ini         |  8 ++-
 .../ref/alpha/eio/simple-atomic/stdout             | 18 +++---
 .../ref/alpha/eio/simple-timing/config.ini         |  2 +
 .../ref/alpha/eio/simple-timing/stdout             | 16 ++---
 .../50.memtest/ref/alpha/linux/memtest/config.ini  |  4 ++
 .../50.memtest/ref/alpha/linux/memtest/stdout      |  6 +-
 .../linux/twosys-tsunami-simple-atomic/config.ini  | 10 +--
 .../linux/twosys-tsunami-simple-atomic/stdout      | 12 ++--
 110 files changed, 1006 insertions(+), 418 deletions(-)

(limited to 'tests')

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 595b91bdc..737f0dea4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
index 9aaca3eeb..cbeafd848 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:22:47 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index e21c42f32..471b28d35 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
index 9aaca3eeb..26bc81b05 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 87443a024..0c02ed13c 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
index 9aaca3eeb..1faa3f4e8 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:00 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 4e87924ca..4219e15b7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
index d3d1e3cfb..ce2e79d1f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:25 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Mar 17 2008 06:14:16
-M5 started Mon Mar 17 06:14:18 2008
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1102714100000 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index b267c8dc4..70a42097e 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
index 5f4ac4eab..e334149fe 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:20 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 744759833500 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 6c34c6dee..af1b3a07f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
index ce05ca938..5597eb1d2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:09 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:45 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 2070157841000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 3572e375e..7f66790fb 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
index 682b64f8a..79273f082 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:48:56 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 955075963000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index ef3141a33..5c55bdb1c 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=55300000000
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
index eb0a0f196..8fdd56739 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:36:22 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 122212687000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index a0f77bf10..a9213133f 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=55300000000
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index 8270f923d..5fdb31dc0 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:32 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:46 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 363652229000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index d878cb424..4ca62bb34 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
index e519e0a5b..996ca24f1 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:45:29 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 165703651500 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index af0a9ce63..0b6f15f38 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
index b105051a9..2ab0ba3a2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:45:29 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
  Reading the dictionary files: *************************************************
  58924 words stored in 3784810 bytes
@@ -57,16 +71,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 863350524000 because target called exit()
+Exiting @ tick 863350526500 because target called exit()
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 56c9263b3..bcc536301 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
index 50ed34325..53e92e76c 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:58 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.133333
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index bfc3d0e40..f1d9f437d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
index 5f057b8dd..285c8d750 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:02 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic tests/run.py long/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.183333
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 6912167e0..4e4683ed6 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
index f9d497506..9f21edbf0 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:28 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.566667
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 9054cf093..68b00e416 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
index d4a078b85..e78146575 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:58 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 1375000: 2038431008
 1374000: 3487365506
 1373000: 4184770123
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 7985d0869..360603943 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
index d4a078b85..722e49f95 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:00 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 1375000: 2038431008
 1374000: 3487365506
 1373000: 4184770123
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 78b7f1eec..162b46290 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
index e69de29bb..f03ee0333 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:19:28 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 4745ee94c..337e5e366 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
index e69de29bb..f99b33e5f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:04 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic tests/run.py long/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 2aab198c9..99587aea2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
index e69de29bb..c568a72c2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:07 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 973d6211f..b8eed166b 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
index 0a780ccee..b230e2c83 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:38:08 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 68148678500 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 01fab79ce..77a49bdbd 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index 5b4fb94a9..592b35b7a 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:46 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:36:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 200790381000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index abff97de4..be4327e6c 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
index 0c5c00118..da44e8643 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:17:14 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 378e34da6..0768661a6 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
index 0c5c00118..469f3b36a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:16:25 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6adec3b74..48686792e 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
index 0c5c00118..c0a8b63da 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index d18301e7c..989908e23 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
index 01a877484..17f5ab40f 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:49:02 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
@@ -12,16 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 2806437159500 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 945804e3d..dbf63ca05 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index f32f0a972..20e9ee506 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:27 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 8fbd6f60b..f0ed922b1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f32f0a972..0fc73d0d9 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index fd50e16e0..0190cf0fe 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index f32f0a972..a512928ef 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:15:31 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 31489ec58..a772db39f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
index 8a70482ca..ab5b187b5 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:08 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 96718067000 because target called exit()
+122 123 124 Exiting @ tick 96718067000 because target called exit()
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index fe6c893b2..77060efdc 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index 0d7eb187f..90bf47617 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:34:33 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,18 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:18:16 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 270416976000 because target called exit()
+122 123 124 Exiting @ tick 270416976000 because target called exit()
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index f3b9dea12..27c1d66f3 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
index ab6e8b338..a8e5ba7f4 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:50:19 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 129915167500 because target called exit()
+122 123 124 Exiting @ tick 129915167500 because target called exit()
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 7369c8a0c..2616832f0 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -65,7 +65,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -109,6 +110,8 @@ read_only=true
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133446500352:133446508543
 zero=false
 port=system.membus.port[7]
@@ -123,6 +126,7 @@ children=responder
 block_size=64
 bus_id=0
 clock=2
+header_cycles=1
 responder_set=false
 width=64
 default=system.iobus.responder.pio
@@ -150,6 +154,7 @@ children=responder
 block_size=64
 bus_id=1
 clock=2
+header_cycles=1
 responder_set=false
 width=64
 default=system.membus.responder.pio
@@ -175,6 +180,8 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133429198848:133429207039
 zero=false
 port=system.membus.port[6]
@@ -183,6 +190,8 @@ port=system.membus.port[6]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133445976064:133445984255
 zero=false
 port=system.membus.port[8]
@@ -191,6 +200,8 @@ port=system.membus.port[8]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=1048576:68157439
 zero=true
 port=system.membus.port[3]
@@ -199,6 +210,8 @@ port=system.membus.port[3]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=2147483648:2415919103
 zero=true
 port=system.membus.port[4]
@@ -207,13 +220,15 @@ port=system.membus.port[4]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=1099243192320:1099251580927
 zero=false
 port=system.membus.port[5]
 
 [system.t1000]
 type=T1000
-children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0
+children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
 intrctrl=system.intrctrl
 system=system
 
@@ -409,12 +424,11 @@ update_data=false
 warn_access=
 pio=system.iobus.port[10]
 
-[system.t1000.hconsole]
-type=SimConsole
-append_name=true
+[system.t1000.hterm]
+type=Terminal
 intr_control=system.intrctrl
 number=0
-output=console
+output=true
 port=3456
 
 [system.t1000.htod]
@@ -431,8 +445,8 @@ type=Uart8250
 pio_addr=1099255955456
 pio_latency=2
 platform=system.t1000
-sim_console=system.t1000.hconsole
 system=system
+terminal=system.t1000.hterm
 pio=system.iobus.port[13]
 
 [system.t1000.iob]
@@ -442,12 +456,11 @@ platform=system.t1000
 system=system
 pio=system.membus.port[0]
 
-[system.t1000.pconsole]
-type=SimConsole
-append_name=true
+[system.t1000.pterm]
+type=Terminal
 intr_control=system.intrctrl
 number=0
-output=console
+output=true
 port=3456
 
 [system.t1000.puart0]
@@ -455,7 +468,7 @@ type=Uart8250
 pio_addr=133412421632
 pio_latency=2
 platform=system.t1000
-sim_console=system.t1000.pconsole
 system=system
+terminal=system.t1000.pterm
 pio=system.iobus.port[12]
 
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
index 4c8cf9392..78a121c17 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2007 14:42:25
-M5 started Tue Aug 21 14:44:56 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:41:45
+M5 started Mon Jul 21 20:41:46 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 Exiting @ tick 2233777512 because m5_exit instruction encountered
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 1d32ced97..3db01031d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index fc63a59a9..05d3c33eb 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -1,4 +1,3 @@
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2008 17:52:16
-M5 started Wed Feb 27 17:56:32 2008
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:18:02 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 5303000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 264bd19de..e68e8bc1c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index 9af7c0a45..ae7c0fe57 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -1,14 +1,16 @@
-Hello world!
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 17:36:58
-M5 started Tue Aug 14 17:40:03 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:07 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 2833500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 7b95a328d..bbb328185 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index 11d2e9b8e..c8cf5ab9d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -1,4 +1,3 @@
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 12:58:20
-M5 started Sun Feb 24 12:58:22 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:04 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 19285000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 26f63e7be..2971dacfa 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 95bc632c8..abedce50c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -1,4 +1,3 @@
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2008 17:52:16
-M5 started Wed Feb 27 17:56:33 2008
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 2700000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index ac0ec32b8..74656d464 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index d906bb79e..0f1a816dd 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -1,14 +1,16 @@
-Hello world!
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 27 2007 13:46:37
-M5 started Thu Sep 27 20:06:36 2007
-M5 executing on zeep
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:07 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 1297500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 4f7ec60f2..7d543f47c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index c25792a5f..d1bbc80b8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -1,4 +1,3 @@
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 12:58:20
-M5 started Sun Feb 24 12:58:25 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:24:22 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 9950000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 653ab3552..11bedc8c7 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -11,7 +11,62 @@ physmem=system.physmem
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb itb tlb tracer workload
+CP0_Config=0
+CP0_Config1=0
+CP0_Config1_C2=false
+CP0_Config1_CA=false
+CP0_Config1_DA=0
+CP0_Config1_DL=0
+CP0_Config1_DS=0
+CP0_Config1_EP=false
+CP0_Config1_FP=false
+CP0_Config1_IA=0
+CP0_Config1_IL=0
+CP0_Config1_IS=0
+CP0_Config1_M=0
+CP0_Config1_MD=false
+CP0_Config1_MMU=0
+CP0_Config1_PC=false
+CP0_Config1_WR=false
+CP0_Config2=0
+CP0_Config2_M=false
+CP0_Config2_SA=0
+CP0_Config2_SL=0
+CP0_Config2_SS=0
+CP0_Config2_SU=0
+CP0_Config2_TA=0
+CP0_Config2_TL=0
+CP0_Config2_TS=0
+CP0_Config2_TU=0
+CP0_Config3=0
+CP0_Config3_DSPP=false
+CP0_Config3_LPA=false
+CP0_Config3_M=false
+CP0_Config3_MT=false
+CP0_Config3_SM=false
+CP0_Config3_SP=false
+CP0_Config3_TL=false
+CP0_Config3_VEIC=false
+CP0_Config3_VInt=false
+CP0_Config_AR=0
+CP0_Config_AT=0
+CP0_Config_BE=0
+CP0_Config_MT=0
+CP0_Config_VI=0
+CP0_EBase_CPUNum=0
+CP0_IntCtl_IPPCI=0
+CP0_IntCtl_IPTI=0
+CP0_PRId=0
+CP0_PRId_CompanyID=0
+CP0_PRId_CompanyOptions=0
+CP0_PRId_ProcessorID=1
+CP0_PRId_Revision=0
+CP0_PerfCtr_M=false
+CP0_PerfCtr_W=false
+CP0_SrsCtl_HSS=0
+CP0_WatchHi_M=false
+UnifiedTLB=true
 clock=500
 cpu_id=0
 defer_registration=false
@@ -25,8 +80,10 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
+tlb=system.cpu.tlb
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
@@ -35,9 +92,15 @@ icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
 type=MipsDTB
+size=64
 
 [system.cpu.itb]
 type=MipsITB
+size=64
+
+[system.cpu.tlb]
+type=MipsUTB
+size=64
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -52,9 +115,11 @@ euid=100
 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -63,6 +128,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -71,6 +137,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 1cc3f6662..43b61af39 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -1,14 +1,16 @@
-Hello World!
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 22:02:23
-M5 started Tue Aug 14 22:02:24 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:31:07
+M5 started Mon Jul 21 20:31:10 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
+Hello World!
 Exiting @ tick 2828000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 1b246149f..e5f76a0a8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -234,6 +234,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -251,6 +252,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 4dcddd5ae..37be8fb0c 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -1,4 +1,3 @@
-Hello World!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:24:29
-M5 started Sun Feb 24 13:24:31 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:31:07
+M5 started Mon Jul 21 20:31:09 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
+Hello World!
 Exiting @ tick 19359000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 73da00d73..d13eeb4e2 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
index cf86d0964..b07b710c8 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
@@ -1,13 +1,15 @@
-Hello World!M5 Simulator System
+M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:18 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2447500 because target called exit()
+Hello World!Exiting @ tick 2447500 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index ef40ce3fd..092061e7f 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
index 12e9a5d09..4d51e2838 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
@@ -1,13 +1,15 @@
-Hello World!M5 Simulator System
+M5 Simulator System
 
 Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:27:50
-M5 started Sun Feb 24 13:28:47 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:08 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 16662000 because target called exit()
+Hello World!Exiting @ tick 16662000 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 6d8421e24..569d4b220 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout
index 80b2e5852..99e187690 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout
@@ -1,4 +1,3 @@
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -6,9 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:50:18 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
+Hello world!
 Exiting @ tick 4932000 because target called exit()
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index d966db2bf..ca040dc25 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -393,6 +394,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -410,6 +412,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index 9d1a14d46..1b77a8f81 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -1,5 +1,3 @@
-Hello world!
-Hello world!
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,9 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2008 17:52:16
-M5 started Wed Feb 27 17:56:35 2008
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
+Hello world!
+Hello world!
 Exiting @ tick 6363000 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index c6ceaa121..e981744fd 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
index ee061a6c6..e6fab5604 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:19 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
 Begining test of difficult SPARC instructions...
 LDSTUB:		Passed
 SWAP:		Passed
@@ -9,16 +23,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 27 2008 17:54:12
-M5 started Wed Feb 27 18:07:27 2008
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 15392500 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index a1a3cadc4..ba8f324ab 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
index c0bb8f23f..6632a0f07 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:18 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 Begining test of difficult SPARC instructions...
 LDSTUB:		Passed
 SWAP:		Passed
@@ -9,16 +23,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 5514000 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index f4a82a8e3..fa313ad0d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
index a0c51dd80..e7f5d2afa 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:19 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
 Begining test of difficult SPARC instructions...
 LDSTUB:		Passed
 SWAP:		Passed
@@ -9,16 +23,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 12:26:21 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 25237000 because target called exit()
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index aaa49012b..ecab1a9a6 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -53,7 +53,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu0.tracer
 width=1
@@ -163,7 +164,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu1.tracer
 width=1
@@ -300,10 +302,11 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
 
 [system.iocache]
 type=BaseCache
@@ -383,6 +386,7 @@ children=responder
 block_size=64
 bus_id=1
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 default=system.membus.responder.pio
@@ -408,18 +412,12 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[1]
 
-[system.sim_console]
-type=SimConsole
-append_name=true
-intr_control=system.intrctrl
-number=0
-output=console
-port=3456
-
 [system.simple_disk]
 type=SimpleDisk
 children=disk
@@ -431,12 +429,20 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
 [system.toL2Bus]
 type=Bus
 children=responder
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 default=system.toL2Bus.responder.pio
@@ -460,10 +466,21 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
 [system.tsunami.cchip]
 type=TsunamiCChip
 pio_addr=8803072344064
@@ -473,17 +490,6 @@ system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
 
-[system.tsunami.console]
-type=AlphaConsole
-cpu=system.cpu0
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-sim_console=system.sim_console
-system=system
-pio=system.iobus.port[25]
-
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
@@ -945,7 +951,7 @@ type=Uart8250
 pio_addr=8804615848952
 pio_latency=1000
 platform=system.tsunami
-sim_console=system.sim_console
 system=system
+terminal=system.terminal
 pio=system.iobus.port[24]
 
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index 5f45dab42..a5a0972a1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 13 2008 00:33:19
-M5 started Wed Feb 13 00:38:27 2008
+M5 compiled Jul 21 2008 20:27:21
+M5 started Mon Jul 21 20:28:09 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1870335151500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index f47a4495c..4ce652819 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -53,7 +53,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -190,10 +191,11 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
 
 [system.iocache]
 type=BaseCache
@@ -273,6 +275,7 @@ children=responder
 block_size=64
 bus_id=1
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 default=system.membus.responder.pio
@@ -298,18 +301,12 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[1]
 
-[system.sim_console]
-type=SimConsole
-append_name=true
-intr_control=system.intrctrl
-number=0
-output=console
-port=3456
-
 [system.simple_disk]
 type=SimpleDisk
 children=disk
@@ -321,12 +318,20 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
 [system.toL2Bus]
 type=Bus
 children=responder
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 default=system.toL2Bus.responder.pio
@@ -350,10 +355,21 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
 [system.tsunami.cchip]
 type=TsunamiCChip
 pio_addr=8803072344064
@@ -363,17 +379,6 @@ system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
 
-[system.tsunami.console]
-type=AlphaConsole
-cpu=system.cpu
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-sim_console=system.sim_console
-system=system
-pio=system.iobus.port[25]
-
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
@@ -835,7 +840,7 @@ type=Uart8250
 pio_addr=8804615848952
 pio_latency=1000
 platform=system.tsunami
-sim_console=system.sim_console
 system=system
+terminal=system.terminal
 pio=system.iobus.port[24]
 
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index 830f4d057..ac8785088 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 13 2008 00:33:19
-M5 started Wed Feb 13 00:37:45 2008
+M5 compiled Jul 21 2008 20:27:21
+M5 started Mon Jul 21 20:27:46 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1828355496000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 1181dac96..459187376 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -300,7 +300,7 @@ header_cycles=1
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
 
 [system.iocache]
 type=BaseCache
@@ -406,18 +406,12 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[1]
 
-[system.sim_console]
-type=SimConsole
-append_name=true
-intr_control=system.intrctrl
-number=0
-output=console
-port=3456
-
 [system.simple_disk]
 type=SimpleDisk
 children=disk
@@ -429,6 +423,13 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
 [system.toL2Bus]
 type=Bus
 children=responder
@@ -459,10 +460,21 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
 [system.tsunami.cchip]
 type=TsunamiCChip
 pio_addr=8803072344064
@@ -472,17 +484,6 @@ system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
 
-[system.tsunami.console]
-type=AlphaConsole
-cpu=system.cpu0
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-sim_console=system.sim_console
-system=system
-pio=system.iobus.port[25]
-
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
@@ -944,7 +945,7 @@ type=Uart8250
 pio_addr=8804615848952
 pio_latency=1000
 platform=system.tsunami
-sim_console=system.sim_console
 system=system
+terminal=system.terminal
 pio=system.iobus.port[24]
 
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 84f4de778..18467c41b 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,9 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2008 17:52:52
-M5 started Wed Feb 27 18:02:58 2008
+M5 compiled Jul 21 2008 20:27:21
+M5 started Mon Jul 21 20:27:23 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1972679592000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 1b52231ed..66d96d325 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -192,7 +192,7 @@ header_cycles=1
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
 
 [system.iocache]
 type=BaseCache
@@ -298,18 +298,12 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[1]
 
-[system.sim_console]
-type=SimConsole
-append_name=true
-intr_control=system.intrctrl
-number=0
-output=console
-port=3456
-
 [system.simple_disk]
 type=SimpleDisk
 children=disk
@@ -321,6 +315,13 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
 [system.toL2Bus]
 type=Bus
 children=responder
@@ -351,10 +352,21 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
 [system.tsunami.cchip]
 type=TsunamiCChip
 pio_addr=8803072344064
@@ -364,17 +376,6 @@ system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
 
-[system.tsunami.console]
-type=AlphaConsole
-cpu=system.cpu
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-sim_console=system.sim_console
-system=system
-pio=system.iobus.port[25]
-
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
@@ -836,7 +837,7 @@ type=Uart8250
 pio_addr=8804615848952
 pio_latency=1000
 platform=system.tsunami
-sim_console=system.sim_console
 system=system
+terminal=system.terminal
 pio=system.iobus.port[24]
 
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index fee547a1f..a429ac712 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,9 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:18:14
-M5 started Sun Feb 24 13:19:10 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:27:21
+M5 started Mon Jul 21 20:28:11 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1931639667000 because m5_exit instruction encountered
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 9db92d8dc..a0555b3f3 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -48,6 +49,8 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
 output=cout
 system=system
 
@@ -56,6 +59,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -64,6 +68,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index fee99ba99..54f73c06e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -1,15 +1,17 @@
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
+M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 17:58:14
-M5 started Tue Aug 14 17:58:32 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:16:25 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 250015500 because a thread reached the max instruction count
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 766b954c1..ddf7f50b2 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -183,6 +183,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 870de60ce..3f3a9bccf 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -1,15 +1,17 @@
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
+M5 Simulator System
 
 Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 12:58:20
-M5 started Sun Feb 24 12:58:24 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:18:02 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 707548000 because a thread reached the max instruction count
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 707548000 because a thread reached the max instruction count
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index e04a78cce..1a7e3807d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -429,6 +429,8 @@ mem_side=system.toL2Bus.port[8]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
@@ -483,6 +485,8 @@ port=system.l2c.mem_side system.physmem.port[0]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[1]
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index 3088b7501..d0d9bd67d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,9 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2008 17:52:16
-M5 started Wed Feb 27 17:56:37 2008
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:18:03 2008
 M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 113467820 because maximum number of loads reached
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 8acd4fb85..5ae2e325d 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-server.rcS
+readfile=/z/binkertn/regress/m5/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -53,7 +53,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=drivesys
 tracer=drivesys.cpu.tracer
 width=1
@@ -697,7 +698,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-stream-client.rcS
+readfile=/z/binkertn/regress/m5/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -736,7 +737,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=testsys
 tracer=testsys.cpu.tracer
 width=1
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
index bc3aa034b..c137b03cf 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jun 18 2008 01:24:58
-M5 started Wed Jun 18 09:39:49 2008
+M5 compiled Jul 21 2008 20:27:21
+M5 started Mon Jul 21 20:27:45 2008
 M5 executing on zizzer
-M5 revision 5485:840f91d062a9bd9c980e5959005329c3ed1bc82e
-M5 commit date Tue Jun 17 22:22:44 2008 -0700
-command line: /n/zeep/y/binkertn/build/work/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/work/build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 Exiting @ tick 4300235844056 because checkpoint
-- 
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