From bfd5eb2b08dad700d085a637d5e16a61dcc530d7 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 14:33:56 -0500 Subject: Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3 --- tests/configs/o3-timing-mp.py | 1 - tests/configs/o3-timing.py | 1 - tests/configs/simple-atomic-mp.py | 1 - tests/configs/simple-atomic.py | 1 - tests/configs/simple-timing-mp.py | 1 - tests/configs/simple-timing.py | 2 -- tests/configs/tsunami-simple-atomic-dual.py | 1 - tests/configs/tsunami-simple-atomic.py | 1 - tests/configs/tsunami-simple-timing-dual.py | 1 - tests/configs/tsunami-simple-timing.py | 1 - 10 files changed, 11 deletions(-) (limited to 'tests') diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 68631b3d2..331e2c569 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -71,7 +71,6 @@ system.l2c.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 0dd7be506..a66cd436e 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -40,7 +40,6 @@ class MyCache(BaseCache): cpu = DerivO3CPU() cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) -cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index eaa6ec66e..f9e4e2767 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index d35ac4ae0..a8a876994 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -34,6 +34,5 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0), membus = Bus()) system.physmem.port = system.membus.port system.cpu.connectMemPorts(system.membus) -system.cpu.mem = system.physmem root = Root(system = system) diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 8f9ab0dde..0d99d8714 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 60190b47c..d7d505a5a 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -39,8 +39,6 @@ class MyCache(BaseCache): cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) -cpu.mem = cpu.dcache -cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 1e6c10243..4adb32868 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) - c.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 623d285e4..653df9bb0 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -35,6 +35,5 @@ cpu = AtomicSimpleCPU(cpu_id=0) system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpu cpu.connectMemPorts(system.membus) -cpu.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 516495d18..bfd478969 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) - c.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 2edf5ac32..59401c040 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -35,6 +35,5 @@ cpu = TimingSimpleCPU(cpu_id=0) system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu cpu.connectMemPorts(system.membus) -cpu.mem = system.physmem root = Root(clock = '2GHz', system = system) -- cgit v1.2.3