From ca0fd665dcf6a4aeda07955d3898b03204c88fd8 Mon Sep 17 00:00:00 2001
From: Wendy Elsasser <wendy.elsasser@arm.com>
Date: Tue, 14 Feb 2017 15:09:18 -0600
Subject: mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
	<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
	<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
	n = 16
	w = 4
The resulting configuration name is:
	DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
---
 tests/configs/minor-timing-mp.py               | 2 +-
 tests/configs/minor-timing.py                  | 2 +-
 tests/configs/o3-timing-checker.py             | 2 +-
 tests/configs/o3-timing-mp.py                  | 2 +-
 tests/configs/o3-timing-mt.py                  | 4 ++--
 tests/configs/o3-timing.py                     | 4 ++--
 tests/configs/pc-o3-timing.py                  | 2 +-
 tests/configs/pc-simple-timing.py              | 2 +-
 tests/configs/pc-switcheroo-full.py            | 2 +-
 tests/configs/realview-minor-dual.py           | 2 +-
 tests/configs/realview-minor.py                | 2 +-
 tests/configs/realview-o3-checker.py           | 2 +-
 tests/configs/realview-o3-dual.py              | 2 +-
 tests/configs/realview-o3.py                   | 2 +-
 tests/configs/realview-simple-timing-dual.py   | 2 +-
 tests/configs/realview-simple-timing.py        | 2 +-
 tests/configs/realview-switcheroo-full.py      | 2 +-
 tests/configs/realview-switcheroo-o3.py        | 2 +-
 tests/configs/realview-switcheroo-timing.py    | 2 +-
 tests/configs/realview64-minor-dual.py         | 2 +-
 tests/configs/realview64-minor.py              | 2 +-
 tests/configs/realview64-o3-checker.py         | 2 +-
 tests/configs/realview64-o3-dual.py            | 2 +-
 tests/configs/realview64-o3.py                 | 2 +-
 tests/configs/realview64-simple-timing-dual.py | 2 +-
 tests/configs/realview64-simple-timing.py      | 2 +-
 tests/configs/realview64-switcheroo-full.py    | 2 +-
 tests/configs/realview64-switcheroo-o3.py      | 2 +-
 tests/configs/realview64-switcheroo-timing.py  | 2 +-
 tests/configs/tgen-dram-ctrl.py                | 2 +-
 tests/configs/tsunami-minor-dual.py            | 2 +-
 tests/configs/tsunami-minor.py                 | 2 +-
 tests/configs/tsunami-o3-dual.py               | 2 +-
 tests/configs/tsunami-o3.py                    | 2 +-
 tests/configs/tsunami-simple-timing-dual.py    | 2 +-
 tests/configs/tsunami-simple-timing.py         | 2 +-
 tests/configs/tsunami-switcheroo-full.py       | 2 +-
 37 files changed, 39 insertions(+), 39 deletions(-)

(limited to 'tests')

diff --git a/tests/configs/minor-timing-mp.py b/tests/configs/minor-timing-mp.py
index 047f84684..1c999b22f 100644
--- a/tests/configs/minor-timing-mp.py
+++ b/tests/configs/minor-timing-mp.py
@@ -42,5 +42,5 @@ from m5.objects import *
 from base_config import *
 
 nb_cores = 4
-root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
+root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
                     cpu_class=MinorCPU, num_cpus=nb_cores).create_root()
diff --git a/tests/configs/minor-timing.py b/tests/configs/minor-timing.py
index 751481e37..047675c64 100644
--- a/tests/configs/minor-timing.py
+++ b/tests/configs/minor-timing.py
@@ -41,5 +41,5 @@
 from m5.objects import *
 from base_config import *
 
-root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                 cpu_class=MinorCPU).create_root()
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 94131d745..8fc9a4d5f 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -38,6 +38,6 @@
 from m5.objects import *
 from base_config import *
 
-root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                 cpu_class=DerivO3CPU,
                                 checker=True).create_root()
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 1ec4182bd..80870388d 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -42,5 +42,5 @@ from m5.objects import *
 from base_config import *
 
 nb_cores = 4
-root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
+root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
                     cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()
diff --git a/tests/configs/o3-timing-mt.py b/tests/configs/o3-timing-mt.py
index 3802941ab..7a829bb05 100644
--- a/tests/configs/o3-timing-mt.py
+++ b/tests/configs/o3-timing-mt.py
@@ -48,10 +48,10 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
 # configuration. This makes the results more meaningful, and also
 # increases the coverage of the regressions.
 if buildEnv['TARGET_ISA'] == "arm":
-    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                    cpu_class=O3_ARM_v7a_3,
                                    num_threads=2).create_root()
 else:
-    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                     cpu_class=DerivO3CPU,
                                     num_threads=2).create_root()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index c573277d1..050e4050e 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -48,8 +48,8 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
 # configuration. This makes the results more meaningful, and also
 # increases the coverage of the regressions.
 if buildEnv['TARGET_ISA'] == "arm":
-    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                    cpu_class=O3_ARM_v7a_3).create_root()
 else:
-    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
                                    cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index ed21a9f38..9b6341996 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 45fff460e..5f9f19580 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=TimingSimpleCPU).create_root()
 
diff --git a/tests/configs/pc-switcheroo-full.py b/tests/configs/pc-switcheroo-full.py
index ccae0cc76..6b2bd86f8 100644
--- a/tests/configs/pc-switcheroo-full.py
+++ b/tests/configs/pc-switcheroo-full.py
@@ -42,7 +42,7 @@ from x86_generic import *
 import switcheroo
 
 root = LinuxX86FSSwitcheroo(
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-minor-dual.py b/tests/configs/realview-minor-dual.py
index 2a78d1ed6..ea01c2457 100644
--- a/tests/configs/realview-minor-dual.py
+++ b/tests/configs/realview-minor-dual.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystem(mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=MinorCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-minor.py b/tests/configs/realview-minor.py
index a577a90b9..486e72e09 100644
--- a/tests/configs/realview-minor.py
+++ b/tests/configs/realview-minor.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=MinorCPU).create_root()
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index a2f1c7134..b2e61d258 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -40,6 +40,6 @@ from arm_generic import *
 from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=O3_ARM_v7a_3,
                                     checker=True).create_root()
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 9dff95ac7..f2042cd4e 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -40,6 +40,6 @@ from arm_generic import *
 from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystem(mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=O3_ARM_v7a_3,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index ba4ddde52..6d5752f9b 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -40,5 +40,5 @@ from arm_generic import *
 from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=O3_ARM_v7a_3).create_root()
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 1744f4af0..e875c1f91 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystem(mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=TimingSimpleCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index f73823d30..43a22b39d 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/configs/realview-switcheroo-full.py b/tests/configs/realview-switcheroo-full.py
index 3b28691d4..cdecd252e 100644
--- a/tests/configs/realview-switcheroo-full.py
+++ b/tests/configs/realview-switcheroo-full.py
@@ -40,7 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-switcheroo-o3.py b/tests/configs/realview-switcheroo-o3.py
index 864e0cfd4..54ed0244e 100644
--- a/tests/configs/realview-switcheroo-o3.py
+++ b/tests/configs/realview-switcheroo-o3.py
@@ -40,7 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(DerivO3CPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-switcheroo-timing.py b/tests/configs/realview-switcheroo-timing.py
index ff09b7f26..5dd50169b 100644
--- a/tests/configs/realview-switcheroo-timing.py
+++ b/tests/configs/realview-switcheroo-timing.py
@@ -40,7 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
     ).create_root()
 
diff --git a/tests/configs/realview64-minor-dual.py b/tests/configs/realview64-minor-dual.py
index 67d8a43f3..7a7e21868 100644
--- a/tests/configs/realview64-minor-dual.py
+++ b/tests/configs/realview64-minor-dual.py
@@ -40,6 +40,6 @@ from arm_generic import *
 
 root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
                         mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=MinorCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview64-minor.py b/tests/configs/realview64-minor.py
index 4674ad59d..796a36db0 100644
--- a/tests/configs/realview64-minor.py
+++ b/tests/configs/realview64-minor.py
@@ -40,5 +40,5 @@ from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
                                     mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=MinorCPU).create_root()
diff --git a/tests/configs/realview64-o3-checker.py b/tests/configs/realview64-o3-checker.py
index 904f0b718..0d5232996 100644
--- a/tests/configs/realview64-o3-checker.py
+++ b/tests/configs/realview64-o3-checker.py
@@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
                                     mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=O3_ARM_v7a_3,
                                     checker=True).create_root()
diff --git a/tests/configs/realview64-o3-dual.py b/tests/configs/realview64-o3-dual.py
index bdfaac0dc..6675c6e3b 100644
--- a/tests/configs/realview64-o3-dual.py
+++ b/tests/configs/realview64-o3-dual.py
@@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
                         mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=O3_ARM_v7a_3,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview64-o3.py b/tests/configs/realview64-o3.py
index b54defa73..090db1e63 100644
--- a/tests/configs/realview64-o3.py
+++ b/tests/configs/realview64-o3.py
@@ -41,5 +41,5 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
 
 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
                                     mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=O3_ARM_v7a_3).create_root()
diff --git a/tests/configs/realview64-simple-timing-dual.py b/tests/configs/realview64-simple-timing-dual.py
index 34f1245e0..fe1e67dd1 100644
--- a/tests/configs/realview64-simple-timing-dual.py
+++ b/tests/configs/realview64-simple-timing-dual.py
@@ -40,6 +40,6 @@ from arm_generic import *
 
 root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
                         mem_mode='timing',
-                        mem_class=DDR3_1600_x64,
+                        mem_class=DDR3_1600_8x8,
                         cpu_class=TimingSimpleCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview64-simple-timing.py b/tests/configs/realview64-simple-timing.py
index 6d9068d92..fb2844e96 100644
--- a/tests/configs/realview64-simple-timing.py
+++ b/tests/configs/realview64-simple-timing.py
@@ -40,5 +40,5 @@ from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
                                     mem_mode='timing',
-                                    mem_class=DDR3_1600_x64,
+                                    mem_class=DDR3_1600_8x8,
                                     cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/configs/realview64-switcheroo-full.py b/tests/configs/realview64-switcheroo-full.py
index b9f28a4a9..6033e4992 100644
--- a/tests/configs/realview64-switcheroo-full.py
+++ b/tests/configs/realview64-switcheroo-full.py
@@ -41,7 +41,7 @@ import switcheroo
 
 root = LinuxArmFSSwitcheroo(
     machine_type='VExpress_EMM64',
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview64-switcheroo-o3.py b/tests/configs/realview64-switcheroo-o3.py
index 7ed9dbf7a..065e1e004 100644
--- a/tests/configs/realview64-switcheroo-o3.py
+++ b/tests/configs/realview64-switcheroo-o3.py
@@ -41,7 +41,7 @@ import switcheroo
 
 root = LinuxArmFSSwitcheroo(
     machine_type='VExpress_EMM64',
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(DerivO3CPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview64-switcheroo-timing.py b/tests/configs/realview64-switcheroo-timing.py
index 1dd481fe2..6be68339d 100644
--- a/tests/configs/realview64-switcheroo-timing.py
+++ b/tests/configs/realview64-switcheroo-timing.py
@@ -41,7 +41,7 @@ import switcheroo
 
 root = LinuxArmFSSwitcheroo(
     machine_type='VExpress_EMM64',
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
     ).create_root()
 
diff --git a/tests/configs/tgen-dram-ctrl.py b/tests/configs/tgen-dram-ctrl.py
index 292c7e5b9..c6d4deef9 100644
--- a/tests/configs/tgen-dram-ctrl.py
+++ b/tests/configs/tgen-dram-ctrl.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(
     config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
 
 # system simulated
-system = System(cpu = cpu, physmem = DDR3_1600_x64(),
+system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
                 membus = IOXBar(width = 16),
                 clk_domain = SrcClockDomain(clock = '1GHz',
                                             voltage_domain =
diff --git a/tests/configs/tsunami-minor-dual.py b/tests/configs/tsunami-minor-dual.py
index 747a45d22..241dd4e95 100644
--- a/tests/configs/tsunami-minor-dual.py
+++ b/tests/configs/tsunami-minor-dual.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystem(mem_mode='timing',
-                          mem_class=DDR3_1600_x64,
+                          mem_class=DDR3_1600_8x8,
                           cpu_class=MinorCPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-minor.py b/tests/configs/tsunami-minor.py
index b234442d3..a202f5cba 100644
--- a/tests/configs/tsunami-minor.py
+++ b/tests/configs/tsunami-minor.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
-                                      mem_class=DDR3_1600_x64,
+                                      mem_class=DDR3_1600_8x8,
                                       cpu_class=MinorCPU).create_root()
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index b50cda557..849b70727 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystem(mem_mode='timing',
-                          mem_class=DDR3_1600_x64,
+                          mem_class=DDR3_1600_8x8,
                           cpu_class=DerivO3CPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index dbbc75e1c..b62a78213 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
-                                      mem_class=DDR3_1600_x64,
+                                      mem_class=DDR3_1600_8x8,
                                       cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 5b8a99ca6..a4653c2d4 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -39,6 +39,6 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystem(mem_mode='timing',
-                          mem_class=DDR3_1600_x64,
+                          mem_class=DDR3_1600_8x8,
                           cpu_class=TimingSimpleCPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 082f79d1e..b19a8f95d 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -39,5 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
-                                      mem_class=DDR3_1600_x64,
+                                      mem_class=DDR3_1600_8x8,
                                       cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/configs/tsunami-switcheroo-full.py b/tests/configs/tsunami-switcheroo-full.py
index 121e669b4..d684cfdc5 100644
--- a/tests/configs/tsunami-switcheroo-full.py
+++ b/tests/configs/tsunami-switcheroo-full.py
@@ -40,7 +40,7 @@ from alpha_generic import *
 import switcheroo
 
 root = LinuxAlphaFSSwitcheroo(
-    mem_class=DDR3_1600_x64,
+    mem_class=DDR3_1600_8x8,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 
-- 
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