From 3de8a78a04b1d1c5e901f3613b6247da9cf00a9c Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 17 Mar 2008 23:07:22 -0400 Subject: Update long regression stats for semi-recent cache changes. --HG-- extra : convert_revision : 7fef1e4f684ced37479ed363ebbb3a7485bc0d52 --- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 1 + .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 76 ++++++++++---------- .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 +- .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 1 + .../00.gzip/ref/sparc/linux/o3-timing/m5stats.txt | 70 +++++++++--------- .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 6 +- .../30.eon/ref/alpha/tru64/o3-timing/config.ini | 1 + .../30.eon/ref/alpha/tru64/o3-timing/m5stats.txt | 68 +++++++++--------- .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 1 + .../ref/alpha/tru64/o3-timing/m5stats.txt | 82 +++++++++++----------- .../50.vortex/ref/alpha/tru64/o3-timing/stderr | 2 +- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 1 + .../60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt | 70 +++++++++--------- .../70.twolf/ref/alpha/tru64/o3-timing/config.ini | 1 + .../70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt | 68 +++++++++--------- 15 files changed, 228 insertions(+), 222 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 60a97b97b..595b91bdc 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 04959f23f..ca33458cb 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4205990 # Nu global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted global.BPredUnit.lookups 76112488 # Number of BP lookups global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target. -host_inst_rate 185893 # Simulator instruction rate (inst/s) -host_mem_usage 223968 # Number of bytes of host memory used -host_seconds 3042.35 # Real time elapsed on the host -host_tick_rate 54375513 # Simulator tick rate (ticks/s) +host_inst_rate 131337 # Simulator instruction rate (inst/s) +host_mem_usage 179084 # Number of bytes of host memory used +host_seconds 4306.11 # Real time elapsed on the host +host_tick_rate 38417331 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads. memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores. memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit. @@ -53,61 +53,61 @@ system.cpu.cpi 0.585019 # CP system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 114321557 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 115038352 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6257.587595 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 216307 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.008111 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 933102 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001892 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001880 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 37579282 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 7448.640662 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008975 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 337288 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.056001 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2209327 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 320.196392 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 321.245700 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 151900839 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 40273.937496 # average overall miss latency +system.cpu.dcache.demand_accesses 154489673 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7094.973483 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003644 # miss rate for demand accesses -system.cpu.dcache.demand_misses 553595 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.020341 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3142429 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003644 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003583 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 151900839 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 40273.937496 # average overall miss latency +system.cpu.dcache.overall_accesses 154489673 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7094.973483 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 151347244 # number of overall hits system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003644 # miss rate for overall accesses -system.cpu.dcache.overall_misses 553595 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.020341 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3142429 # number of overall misses system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003644 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003583 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 468826 # nu system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use -system.cpu.dcache.total_refs 151427918 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 151924159 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 334126 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked @@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66025546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10641.352550 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 66025670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9355.263158 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1026 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses @@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66025546 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10641.352550 # average overall miss latency +system.cpu.icache.demand_accesses 66025670 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9355.263158 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_misses 902 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_misses 1026 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses @@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses 902 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66025546 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10641.352550 # average overall miss latency +system.cpu.icache.overall_accesses 66025670 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9355.263158 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 66024644 # number of overall hits system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_misses 902 # number of overall misses +system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_misses 1026 # number of overall misses system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index 598fc86c0..8053728f7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 857d77efe..4e87924ca 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index a32e8681e..623095a72 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 84375502 # Nu global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted global.BPredUnit.lookups 253548806 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116576 # Simulator instruction rate (inst/s) -host_mem_usage 226608 # Number of bytes of host memory used -host_seconds 12057.44 # Real time elapsed on the host -host_tick_rate 91455071 # Simulator tick rate (ticks/s) +host_inst_rate 60603 # Simulator instruction rate (inst/s) +host_mem_usage 181372 # Number of bytes of host memory used +host_seconds 23193.76 # Real time elapsed on the host +host_tick_rate 47543564 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads. memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores. memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit. @@ -51,16 +51,16 @@ system.cpu.committedInsts 1405610550 # Nu system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 431513840 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5832.966573 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 837060 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency @@ -72,50 +72,50 @@ system.cpu.dcache.SwapReq_misses 40 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 166856456 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 10313.606533 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2134144 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002050 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1192.980326 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency +system.cpu.dcache.demand_accesses 598370296 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9051.301930 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses -system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.004965 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2971204 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency +system.cpu.dcache.overall_accesses 598370296 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9051.301930 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595399092 # number of overall hits system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses -system.cpu.dcache.overall_misses 569002 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.004965 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2971204 # number of overall misses system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -132,7 +132,7 @@ system.cpu.dcache.replacements 495151 # nu system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use -system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 595591849 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 338813 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked @@ -166,13 +166,13 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 356679455 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8992.990654 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 1498 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses @@ -185,13 +185,13 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency +system.cpu.icache.demand_accesses 356679455 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8992.990654 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1498 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses @@ -199,14 +199,14 @@ system.cpu.icache.demand_mshr_misses 1353 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency +system.cpu.icache.overall_accesses 356679455 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8992.990654 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 356677957 # number of overall hits system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1353 # number of overall misses +system.cpu.icache.overall_misses 1498 # number of overall misses system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index 8ee292d5b..d3d1e3cfb 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater +M5 compiled Mar 17 2008 06:14:16 +M5 started Mon Mar 17 06:14:18 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 1102714100000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50eaa3f41..56c9263b3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 3af370c7d..c2cc5eeb4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5691744 # Nu global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted global.BPredUnit.lookups 62480259 # Number of BP lookups global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target. -host_inst_rate 155119 # Simulator instruction rate (inst/s) -host_mem_usage 205336 # Number of bytes of host memory used -host_seconds 2421.21 # Real time elapsed on the host -host_tick_rate 55712012 # Simulator tick rate (ticks/s) +host_inst_rate 99164 # Simulator instruction rate (inst/s) +host_mem_usage 157680 # Number of bytes of host memory used +host_seconds 3787.43 # Real time elapsed on the host +host_tick_rate 35615266 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores. memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit. @@ -53,43 +53,43 @@ system.cpu.cpi 0.718313 # CP system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95885180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15194.726166 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 95885716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9843.626807 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1522 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73513083 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32019.486405 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 9673.649142 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.000149 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 10956 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40554.006943 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40554.032799 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169398263 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 28157.937616 # average overall miss latency +system.cpu.dcache.demand_accesses 169406445 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9694.382113 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.000074 # miss rate for demand accesses +system.cpu.dcache.demand_misses 12478 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses @@ -97,14 +97,14 @@ system.cpu.dcache.demand_mshr_misses 4296 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169398263 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 28157.937616 # average overall miss latency +system.cpu.dcache.overall_accesses 169406445 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9694.382113 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 169393967 # number of overall hits system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4296 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.000074 # miss rate for overall accesses +system.cpu.dcache.overall_misses 12478 # number of overall misses system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 781 # nu system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use -system.cpu.dcache.total_refs 169394087 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 169394195 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 636 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked @@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 64020369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9431.835687 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 64020665 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8765.688380 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3895 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4191 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses @@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 64020369 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9431.835687 # average overall miss latency +system.cpu.icache.demand_accesses 64020665 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8765.688380 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.demand_misses 3895 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_misses 4191 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses @@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses 3895 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 64020369 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9431.835687 # average overall miss latency +system.cpu.icache.overall_accesses 64020665 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8765.688380 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 64016474 # number of overall hits system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.overall_misses 3895 # number of overall misses +system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_misses 4191 # number of overall misses system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index fcea1b656..78b7f1eec 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3829dd799..2e39bfe33 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 455745 # Nu global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted global.BPredUnit.lookups 16239906 # Number of BP lookups global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target. -host_inst_rate 101925 # Simulator instruction rate (inst/s) -host_mem_usage 220292 # Number of bytes of host memory used -host_seconds 780.89 # Real time elapsed on the host -host_tick_rate 32150232 # Simulator tick rate (ticks/s) +host_inst_rate 108698 # Simulator instruction rate (inst/s) +host_mem_usage 171788 # Number of bytes of host memory used +host_seconds 732.23 # Real time elapsed on the host +host_tick_rate 34286652 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads. memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores. memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit. @@ -53,61 +53,61 @@ system.cpu.cpi 0.630861 # CP system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20369036 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19244.510005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 20452895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8143.771495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61521 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.007108 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 145380 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003008 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 13753160 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 50456.177120 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 7484.182742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010893 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149819 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.069117 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1010036 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.441832 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.460856 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34122196 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41370.471752 # average overall miss latency +system.cpu.dcache.demand_accesses 35066272 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7567.175372 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006194 # miss rate for demand accesses -system.cpu.dcache.demand_misses 211340 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.032949 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1155416 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34122196 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41370.471752 # average overall miss latency +system.cpu.dcache.overall_accesses 35066272 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7567.175372 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 33910856 # number of overall hits system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006194 # miss rate for overall accesses -system.cpu.dcache.overall_misses 211340 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.032949 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1155416 # number of overall misses system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006194 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 200914 # nu system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use -system.cpu.dcache.total_refs 33917230 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 33921130 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147756 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked @@ -173,16 +173,16 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13372459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5833.169458 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 13373612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5755.491777 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 85431 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.006474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 86584 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006389 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.006388 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked @@ -192,31 +192,31 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13372459 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5833.169458 # average overall miss latency +system.cpu.icache.demand_accesses 13373612 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5755.491777 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006389 # miss rate for demand accesses -system.cpu.icache.demand_misses 85431 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.006474 # miss rate for demand accesses +system.cpu.icache.demand_misses 86584 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006389 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.006388 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13372459 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5833.169458 # average overall miss latency +system.cpu.icache.overall_accesses 13373612 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5755.491777 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 13287028 # number of overall hits system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006389 # miss rate for overall accesses -system.cpu.icache.overall_misses 85431 # number of overall misses +system.cpu.icache.overall_miss_rate 0.006474 # miss rate for overall accesses +system.cpu.icache.overall_misses 86584 # number of overall misses system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006389 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.006388 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index 8053728f7..5992f7131 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 966f49abc..abff97de4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index d545db111..98a4ae9ba 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19461333 # Nu global.BPredUnit.condPredicted 256954278 # Number of conditional branches predicted global.BPredUnit.lookups 332748805 # Number of BP lookups global.BPredUnit.usedRAS 23332154 # Number of times the RAS was used to get a target. -host_inst_rate 185907 # Simulator instruction rate (inst/s) -host_mem_usage 374916 # Number of bytes of host memory used -host_seconds 9338.25 # Real time elapsed on the host -host_tick_rate 70823738 # Simulator tick rate (ticks/s) +host_inst_rate 98561 # Simulator instruction rate (inst/s) +host_mem_usage 329172 # Number of bytes of host memory used +host_seconds 17613.94 # Real time elapsed on the host +host_tick_rate 37548074 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 73213571 # Number of conflicting loads. memdepunit.memDep.conflictingStores 37308198 # Number of conflicting stores. memdepunit.memDep.insertedLoads 599919223 # Number of loads inserted to the mem dependence unit. @@ -61,61 +61,61 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu system.cpu.dcache.LoadLockedReq_mshr_miss_latency 6500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 513272040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8025.908244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 514699566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6709.313547 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3665.501336 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 505997425 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 58385392500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.014173 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7274615 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.016907 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8702141 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 1427526 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 26665111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014173 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014134 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7274615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 158750545 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19340.801620 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 10289.713687 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 156501908 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 43490442133 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.014165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2248637 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.026296 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4226594 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1977957 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 22750942389 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.014165 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2248637 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 2040.681665 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 2667.920935 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.369821 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 72.404790 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 71409 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 65111 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 145723037 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 173711000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 672022585 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 10697.588873 # average overall miss latency +system.cpu.dcache.demand_accesses 675428068 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7879.799117 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency system.cpu.dcache.demand_hits 662499333 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 101875834633 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.014171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9523252 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.019142 # miss rate for demand accesses +system.cpu.dcache.demand_misses 12928735 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 3405483 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 49416053389 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014171 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.014100 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9523252 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 672022585 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 10697.588873 # average overall miss latency +system.cpu.dcache.overall_accesses 675428068 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7879.799117 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 662499333 # number of overall hits system.cpu.dcache.overall_miss_latency 101875834633 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.014171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9523252 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.019142 # miss rate for overall accesses +system.cpu.dcache.overall_misses 12928735 # number of overall misses system.cpu.dcache.overall_mshr_hits 3405483 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 49416053389 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014171 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.014100 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9523252 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -132,7 +132,7 @@ system.cpu.dcache.replacements 9155291 # nu system.cpu.dcache.sampled_refs 9159387 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4084.377148 # Cycle average of tags in use -system.cpu.dcache.total_refs 662863201 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 663183492 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 6956358000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2245548 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 25695554 # Number of cycles decode is blocked @@ -181,13 +181,13 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 340572130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10589.900111 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 340572268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9183.349374 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6758.046615 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 340571229 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 9541500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 1039 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 138 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 6089000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses @@ -200,13 +200,13 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 340572130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10589.900111 # average overall miss latency +system.cpu.icache.demand_accesses 340572268 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9183.349374 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency system.cpu.icache.demand_hits 340571229 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 9541500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 901 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1039 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 138 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6089000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses @@ -214,14 +214,14 @@ system.cpu.icache.demand_mshr_misses 901 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 340572130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10589.900111 # average overall miss latency +system.cpu.icache.overall_accesses 340572268 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9183.349374 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 340571229 # number of overall hits system.cpu.icache.overall_miss_latency 9541500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 901 # number of overall misses +system.cpu.icache.overall_misses 1039 # number of overall misses system.cpu.icache.overall_mshr_hits 138 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6089000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a81a73367..945804e3d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 2580b06c8..4231c8e95 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1950052 # Nu global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted global.BPredUnit.lookups 19451761 # Number of BP lookups global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target. -host_inst_rate 79678 # Simulator instruction rate (inst/s) -host_mem_usage 202860 # Number of bytes of host memory used -host_seconds 1056.50 # Real time elapsed on the host -host_tick_rate 38578826 # Simulator tick rate (ticks/s) +host_inst_rate 82033 # Simulator instruction rate (inst/s) +host_mem_usage 156240 # Number of bytes of host memory used +host_seconds 1026.17 # Real time elapsed on the host +host_tick_rate 39719192 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit. @@ -53,43 +53,43 @@ system.cpu.cpi 0.968368 # CP system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23270992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 11553.149606 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 23271115 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9301.109350 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 508 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 631 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6494911 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34394.822006 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 7925.428784 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8046 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13269.579581 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13269.627731 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29765903 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29482.218459 # average overall miss latency +system.cpu.dcache.demand_accesses 29772218 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 8025.469632 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2362 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 8677 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses @@ -97,14 +97,14 @@ system.cpu.dcache.demand_mshr_misses 2362 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29765903 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29482.218459 # average overall miss latency +system.cpu.dcache.overall_accesses 29772218 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 8025.469632 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 29763541 # number of overall hits system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2362 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 8677 # number of overall misses system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 159 # nu system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use -system.cpu.dcache.total_refs 29763667 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 29763775 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked @@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19219343 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 6740.447436 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 19219800 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 6448.716735 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000526 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10102 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.000549 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10559 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses @@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19219343 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 6740.447436 # average overall miss latency +system.cpu.icache.demand_accesses 19219800 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 6448.716735 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000526 # miss rate for demand accesses -system.cpu.icache.demand_misses 10102 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.000549 # miss rate for demand accesses +system.cpu.icache.demand_misses 10559 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses @@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses 10102 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19219343 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 6740.447436 # average overall miss latency +system.cpu.icache.overall_accesses 19219800 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 6448.716735 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 19209241 # number of overall hits system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000526 # miss rate for overall accesses -system.cpu.icache.overall_misses 10102 # number of overall misses +system.cpu.icache.overall_miss_rate 0.000549 # miss rate for overall accesses +system.cpu.icache.overall_misses 10559 # number of overall misses system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses -- cgit v1.2.3 From 9ebd244991f473cacc1f73ff4877f2472af3a8fc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 12 Jun 2008 00:42:52 -0400 Subject: X86: Update the regressions for the fact that rdtsc does something now. --- .../long/00.gzip/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr | 1 - tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr | 3 +-- tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout | 10 +++++----- .../20.parser/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../20.parser/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/20.parser/ref/x86/linux/simple-atomic/stderr | 3 +-- tests/long/20.parser/ref/x86/linux/simple-atomic/stdout | 8 ++++---- .../long/60.bzip2/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr | 3 +-- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout | 10 +++++----- .../long/70.twolf/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../70.twolf/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr | 3 +-- tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout | 12 +++++++----- .../00.hello/ref/x86/linux/simple-atomic/config.ini | 3 +++ .../00.hello/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr | 1 - tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout | 10 +++++----- 24 files changed, 101 insertions(+), 87 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index b66960bf9..3572e375e 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index 186158b96..e830c139f 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1240763 # Simulator instruction rate (inst/s) -host_mem_usage 175872 # Number of bytes of host memory used -host_seconds 1292.50 # Real time elapsed on the host -host_tick_rate 738827746 # Simulator tick rate (ticks/s) +host_inst_rate 1980122 # Simulator instruction rate (inst/s) +host_mem_usage 190864 # Number of bytes of host memory used +host_seconds 809.89 # Real time elapsed on the host +host_tick_rate 1179088562 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1603680167 # Number of instructions simulated +sim_insts 1603680170 # Number of instructions simulated sim_seconds 0.954932 # Number of seconds simulated -sim_ticks 954931687500 # Number of ticks simulated +sim_ticks 954931689000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1909863376 # number of cpu cycles simulated -system.cpu.num_insts 1603680167 # Number of instructions executed +system.cpu.numCycles 1909863379 # number of cpu cycles simulated +system.cpu.num_insts 1603680170 # Number of instructions executed system.cpu.num_refs 607157396 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr index 01076d21a..cbad25dfb 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -2,5 +2,4 @@ warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index b0a68cad2..1c14170f7 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -31,14 +31,14 @@ Uncompressed data compared correctly Tested 1MB buffer: OK! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 21:35:26 2007 -M5 executing on nacho +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:59:05 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 954931687500 because target called exit() +Exiting @ tick 954931689000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 527f1b385..d878cb424 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index 794286196..e8cd3750d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1168424 # Simulator instruction rate (inst/s) -host_mem_usage 310284 # Number of bytes of host memory used -host_seconds 230.78 # Real time elapsed on the host -host_tick_rate 718029499 # Simulator tick rate (ticks/s) +host_inst_rate 1615040 # Simulator instruction rate (inst/s) +host_mem_usage 325376 # Number of bytes of host memory used +host_seconds 166.96 # Real time elapsed on the host +host_tick_rate 992489174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269642969 # Number of instructions simulated +sim_insts 269642972 # Number of instructions simulated sim_seconds 0.165704 # Number of seconds simulated -sim_ticks 165703616000 # Number of ticks simulated +sim_ticks 165703617500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331407233 # number of cpu cycles simulated -system.cpu.num_insts 269642969 # Number of instructions executed +system.cpu.numCycles 331407236 # number of cpu cycles simulated +system.cpu.num_insts 269642972 # Number of instructions executed system.cpu.num_refs 124052668 # Number of memory references system.cpu.workload.PROG:num_syscalls 429 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr index 863f1adb9..d81394784 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr @@ -1,5 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index 743c3e8f1..4bc947613 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -16,14 +16,14 @@ checksum : 68389 optimal M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 21:57:00 2007 -M5 executing on nacho +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:59:05 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 165703616000 because target called exit() +Exiting @ tick 165703617500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 10efbab5f..af0a9ce63 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=114600000000 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index 727d390d0..902cda39a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 830115 # Simulator instruction rate (inst/s) -host_mem_usage 150180 # Number of bytes of host memory used -host_seconds 1788.44 # Real time elapsed on the host -host_tick_rate 482678947 # Simulator tick rate (ticks/s) +host_inst_rate 1972929 # Simulator instruction rate (inst/s) +host_mem_usage 194468 # Number of bytes of host memory used +host_seconds 752.49 # Real time elapsed on the host +host_tick_rate 1147180666 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484611664 # Number of instructions simulated +sim_insts 1484611667 # Number of instructions simulated sim_seconds 0.863243 # Number of seconds simulated -sim_ticks 863243462500 # Number of ticks simulated +sim_ticks 863243464000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726486926 # number of cpu cycles simulated -system.cpu.num_insts 1484611664 # Number of instructions executed +system.cpu.numCycles 1726486929 # number of cpu cycles simulated +system.cpu.num_insts 1484611667 # Number of instructions executed system.cpu.num_refs 533543283 # Number of memory references system.cpu.workload.PROG:num_syscalls 541 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr index 46a429e22..67ea3cc5a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr @@ -1,8 +1,7 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index 3c6b14676..7332263ab 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -64,9 +64,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2008 13:01:44 -M5 started Sat Feb 16 13:01:45 2008 -M5 executing on zizzer +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:59:05 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 863243462500 because target called exit() +Exiting @ tick 863243464000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 322bfab4b..d18301e7c 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index 03017061d..fbb7f4253 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1084871 # Simulator instruction rate (inst/s) -host_mem_usage 175684 # Number of bytes of host memory used -host_seconds 4236.15 # Real time elapsed on the host -host_tick_rate 662497504 # Simulator tick rate (ticks/s) +host_inst_rate 1920772 # Simulator instruction rate (inst/s) +host_mem_usage 190768 # Number of bytes of host memory used +host_seconds 2392.62 # Real time elapsed on the host +host_tick_rate 1172956454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4595672201 # Number of instructions simulated +sim_insts 4595672204 # Number of instructions simulated sim_seconds 2.806437 # Number of seconds simulated -sim_ticks 2806436542000 # Number of ticks simulated +sim_ticks 2806436543500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5612873085 # number of cpu cycles simulated -system.cpu.num_insts 4595672201 # Number of instructions executed +system.cpu.numCycles 5612873088 # number of cpu cycles simulated +system.cpu.num_insts 4595672204 # Number of instructions executed system.cpu.num_refs 1686312529 # Number of memory references system.cpu.workload.PROG:num_syscalls 33 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr index 46a429e22..e75f35ba1 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr @@ -1,8 +1,7 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index 1a0378ca6..dd2b3c1b8 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -14,14 +14,14 @@ Uncompressed data compared correctly Tested 1MB buffer: OK! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 22:20:45 2007 -M5 executing on nacho +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:59:05 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2806436542000 because target called exit() +Exiting @ tick 2806436543500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index 0644df864..f3b9dea12 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index db17fc7d7..47792068c 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1304954 # Simulator instruction rate (inst/s) -host_mem_usage 183200 # Number of bytes of host memory used -host_seconds 167.36 # Real time elapsed on the host -host_tick_rate 776224834 # Simulator tick rate (ticks/s) +host_inst_rate 1448506 # Simulator instruction rate (inst/s) +host_mem_usage 197928 # Number of bytes of host memory used +host_seconds 150.78 # Real time elapsed on the host +host_tick_rate 861614355 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218399764 # Number of instructions simulated +sim_insts 218399767 # Number of instructions simulated sim_seconds 0.129911 # Number of seconds simulated -sim_ticks 129910855000 # Number of ticks simulated +sim_ticks 129910856500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259821711 # number of cpu cycles simulated -system.cpu.num_insts 218399764 # Number of instructions executed +system.cpu.numCycles 259821714 # number of cpu cycles simulated +system.cpu.num_insts 218399767 # Number of instructions executed system.cpu.num_refs 77164404 # Number of memory references system.cpu.workload.PROG:num_syscalls 395 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr index 6947c985e..1ba198a70 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr @@ -1,7 +1,6 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index 4f9067256..3e37f91d8 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -13,14 +13,16 @@ Authors: Carl Sechen, Bill Swartz 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 122 123 124 M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 23:31:23 2007 -M5 executing on nacho +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:59:05 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 129910855000 because target called exit() +Exiting @ tick 129910856500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 74f6c930e..6d8421e24 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -58,6 +58,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +67,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +76,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index f834f694b..647bad718 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21996 # Simulator instruction rate (inst/s) -host_mem_usage 172228 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 12789916 # Simulator tick rate (ticks/s) +host_inst_rate 13844 # Simulator instruction rate (inst/s) +host_mem_usage 186312 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +host_tick_rate 8053994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 8472 # Number of instructions simulated +sim_insts 8475 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4930500 # Number of ticks simulated +sim_ticks 4932000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9862 # number of cpu cycles simulated -system.cpu.num_insts 8472 # Number of instructions executed +system.cpu.numCycles 9865 # number of cpu cycles simulated +system.cpu.num_insts 8475 # Number of instructions executed system.cpu.num_refs 1765 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr index 863f1adb9..3d07bd911 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr @@ -2,4 +2,3 @@ warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 302f58c0c..065bf1388 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -1,14 +1,14 @@ Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 25 2007 18:49:38 -M5 started Thu Oct 25 18:49:42 2007 -M5 executing on nacho +M5 compiled Apr 21 2008 13:57:00 +M5 started Mon Apr 21 13:57:01 2008 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4930500 because target called exit() +Exiting @ tick 4932000 because target called exit() -- cgit v1.2.3 From f58f99935a139380d34166cdd20e84d1366e3f6e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 12 Jun 2008 00:48:33 -0400 Subject: X86: Update the regressions for the new string instructions. --- .../00.gzip/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout | 6 +++--- .../10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout | 6 +++--- .../20.parser/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- .../long/20.parser/ref/x86/linux/simple-atomic/stderr | 2 +- .../long/20.parser/ref/x86/linux/simple-atomic/stdout | 6 +++--- .../60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt | 14 +++++++------- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout | 6 +++--- .../70.twolf/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout | 8 +++----- .../00.hello/ref/x86/linux/simple-atomic/m5stats.txt | 8 ++++---- .../quick/00.hello/ref/x86/linux/simple-atomic/stderr | 2 +- .../quick/00.hello/ref/x86/linux/simple-atomic/stdout | 4 ++-- 17 files changed, 68 insertions(+), 70 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index e830c139f..1dc72cfa0 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1980122 # Simulator instruction rate (inst/s) -host_mem_usage 190864 # Number of bytes of host memory used -host_seconds 809.89 # Real time elapsed on the host -host_tick_rate 1179088562 # Simulator tick rate (ticks/s) +host_inst_rate 1900139 # Simulator instruction rate (inst/s) +host_mem_usage 190872 # Number of bytes of host memory used +host_seconds 844.13 # Real time elapsed on the host +host_tick_rate 1131428996 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1603680170 # Number of instructions simulated -sim_seconds 0.954932 # Number of seconds simulated -sim_ticks 954931689000 # Number of ticks simulated +sim_insts 1603968718 # Number of instructions simulated +sim_seconds 0.955076 # Number of seconds simulated +sim_ticks 955075963000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1909863379 # number of cpu cycles simulated -system.cpu.num_insts 1603680170 # Number of instructions executed +system.cpu.numCycles 1910151927 # number of cpu cycles simulated +system.cpu.num_insts 1603968718 # Number of instructions executed system.cpu.num_refs 607157396 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr index cbad25dfb..4cf848bfa 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 1c14170f7..682b64f8a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:59:05 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 954931689000 because target called exit() +Exiting @ tick 955075963000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index e8cd3750d..b1bff08e1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1615040 # Simulator instruction rate (inst/s) -host_mem_usage 325376 # Number of bytes of host memory used -host_seconds 166.96 # Real time elapsed on the host -host_tick_rate 992489174 # Simulator tick rate (ticks/s) +host_inst_rate 1573393 # Simulator instruction rate (inst/s) +host_mem_usage 325380 # Number of bytes of host memory used +host_seconds 171.38 # Real time elapsed on the host +host_tick_rate 966895627 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269642972 # Number of instructions simulated +sim_insts 269643040 # Number of instructions simulated sim_seconds 0.165704 # Number of seconds simulated -sim_ticks 165703617500 # Number of ticks simulated +sim_ticks 165703651500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331407236 # number of cpu cycles simulated -system.cpu.num_insts 269642972 # Number of instructions executed +system.cpu.numCycles 331407304 # number of cpu cycles simulated +system.cpu.num_insts 269643040 # Number of instructions executed system.cpu.num_refs 124052668 # Number of memory references system.cpu.workload.PROG:num_syscalls 429 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index 4bc947613..e519e0a5b 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -21,9 +21,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:59:05 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 165703617500 because target called exit() +Exiting @ tick 165703651500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index 902cda39a..5ab585992 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1972929 # Simulator instruction rate (inst/s) -host_mem_usage 194468 # Number of bytes of host memory used -host_seconds 752.49 # Real time elapsed on the host -host_tick_rate 1147180666 # Simulator tick rate (ticks/s) +host_inst_rate 1959706 # Simulator instruction rate (inst/s) +host_mem_usage 194472 # Number of bytes of host memory used +host_seconds 757.68 # Real time elapsed on the host +host_tick_rate 1139469005 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484611667 # Number of instructions simulated -sim_seconds 0.863243 # Number of seconds simulated -sim_ticks 863243464000 # Number of ticks simulated +sim_insts 1484825787 # Number of instructions simulated +sim_seconds 0.863351 # Number of seconds simulated +sim_ticks 863350524000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726486929 # number of cpu cycles simulated -system.cpu.num_insts 1484611667 # Number of instructions executed +system.cpu.numCycles 1726701049 # number of cpu cycles simulated +system.cpu.num_insts 1484825787 # Number of instructions executed system.cpu.num_refs 533543283 # Number of memory references system.cpu.workload.PROG:num_syscalls 541 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr index 67ea3cc5a..e75f35ba1 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index 7332263ab..b105051a9 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -64,9 +64,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:59:05 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 863243464000 because target called exit() +Exiting @ tick 863350524000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index fbb7f4253..d84d96131 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1920772 # Simulator instruction rate (inst/s) +host_inst_rate 1870134 # Simulator instruction rate (inst/s) host_mem_usage 190768 # Number of bytes of host memory used -host_seconds 2392.62 # Real time elapsed on the host -host_tick_rate 1172956454 # Simulator tick rate (ticks/s) +host_seconds 2457.40 # Real time elapsed on the host +host_tick_rate 1142033656 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4595672204 # Number of instructions simulated +sim_insts 4595673436 # Number of instructions simulated sim_seconds 2.806437 # Number of seconds simulated -sim_ticks 2806436543500 # Number of ticks simulated +sim_ticks 2806437159500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5612873088 # number of cpu cycles simulated -system.cpu.num_insts 4595672204 # Number of instructions executed +system.cpu.numCycles 5612874320 # number of cpu cycles simulated +system.cpu.num_insts 4595673436 # Number of instructions executed system.cpu.num_refs 1686312529 # Number of memory references system.cpu.workload.PROG:num_syscalls 33 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr index e75f35ba1..64c88a35a 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +0: system.remote_gdb.listener: listening for remote gdb on port 7005 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index dd2b3c1b8..01a877484 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -19,9 +19,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:59:05 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2806436543500 because target called exit() +Exiting @ tick 2806437159500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index 47792068c..8ea3b34db 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1448506 # Simulator instruction rate (inst/s) -host_mem_usage 197928 # Number of bytes of host memory used -host_seconds 150.78 # Real time elapsed on the host -host_tick_rate 861614355 # Simulator tick rate (ticks/s) +host_inst_rate 1442472 # Simulator instruction rate (inst/s) +host_mem_usage 197924 # Number of bytes of host memory used +host_seconds 151.41 # Real time elapsed on the host +host_tick_rate 858020061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218399767 # Number of instructions simulated -sim_seconds 0.129911 # Number of seconds simulated -sim_ticks 129910856500 # Number of ticks simulated +sim_insts 218408389 # Number of instructions simulated +sim_seconds 0.129915 # Number of seconds simulated +sim_ticks 129915167500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259821714 # number of cpu cycles simulated -system.cpu.num_insts 218399767 # Number of instructions executed +system.cpu.numCycles 259830336 # number of cpu cycles simulated +system.cpu.num_insts 218408389 # Number of instructions executed system.cpu.num_refs 77164404 # Number of memory references system.cpu.workload.PROG:num_syscalls 395 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr index 1ba198a70..8adaf60da 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index 3e37f91d8..ab6e8b338 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -18,11 +18,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:59:05 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 129910856500 because target called exit() +Exiting @ tick 129915167500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index 647bad718..5fd208e3f 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 13844 # Simulator instruction rate (inst/s) -host_mem_usage 186312 # Number of bytes of host memory used -host_seconds 0.61 # Real time elapsed on the host -host_tick_rate 8053994 # Simulator tick rate (ticks/s) +host_inst_rate 13744 # Simulator instruction rate (inst/s) +host_mem_usage 186320 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host +host_tick_rate 7996070 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 8475 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr index 3d07bd911..e29ceab39 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 065bf1388..80b2e5852 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2008 13:57:00 -M5 started Mon Apr 21 13:57:01 2008 +M5 compiled May 17 2008 13:48:04 +M5 started Sat May 17 13:48:05 2008 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -- cgit v1.2.3 From 6ff4539901c6efa05ecad20149342fe8d64e7ba9 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 17 Jun 2008 20:30:37 -0700 Subject: Change the default output filename for the terminal so it's more obvious. --HG-- rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal --- .../console.system.sim_console | 110 ------------------- .../tsunami-simple-atomic-dual/system.terminal | 110 +++++++++++++++++++ .../console.system.sim_console | 105 ------------------ .../linux/tsunami-simple-atomic/system.terminal | 105 ++++++++++++++++++ .../console.system.sim_console | 110 ------------------- .../tsunami-simple-timing-dual/system.terminal | 110 +++++++++++++++++++ .../console.system.sim_console | 105 ------------------ .../linux/tsunami-simple-timing/system.terminal | 105 ++++++++++++++++++ .../console.drivesys.sim_console | 112 ------------------- .../console.testsys.sim_console | 121 --------------------- .../twosys-tsunami-simple-atomic/drivesys.terminal | 112 +++++++++++++++++++ .../twosys-tsunami-simple-atomic/testsys.terminal | 121 +++++++++++++++++++++ 12 files changed, 663 insertions(+), 663 deletions(-) delete mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console create mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal delete mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console create mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal delete mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console create mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal delete mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console create mode 100644 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal delete mode 100644 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console delete mode 100644 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console create mode 100644 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal create mode 100644 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal (limited to 'tests') diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console deleted file mode 100644 index c2aeea3f1..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ /dev/null @@ -1,110 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 2 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 - Bootstraping CPU 1 with sp=0xFFFFFC0000076000 - unix_boot_mem ends at FFFFFC0000078000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 2 CPUs probed -- cpu_present_mask = 3 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP starting up secondaries. - Slave CPU 1 console command START -SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 - Brought up 2 CPUs - SMP: Total of 2 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal new file mode 100644 index 000000000..c2aeea3f1 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal @@ -0,0 +1,110 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 2 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 + Bootstraping CPU 1 with sp=0xFFFFFC0000076000 + unix_boot_mem ends at FFFFFC0000078000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 2 CPUs probed -- cpu_present_mask = 3 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP starting up secondaries. + Slave CPU 1 console command START +SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 + Brought up 2 CPUs + SMP: Total of 2 processors activated (8000.15 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console deleted file mode 100644 index 7930e9e46..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ /dev/null @@ -1,105 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal new file mode 100644 index 000000000..7930e9e46 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal @@ -0,0 +1,105 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (4002.20 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console deleted file mode 100644 index c2aeea3f1..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ /dev/null @@ -1,110 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 2 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 - Bootstraping CPU 1 with sp=0xFFFFFC0000076000 - unix_boot_mem ends at FFFFFC0000078000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 2 CPUs probed -- cpu_present_mask = 3 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP starting up secondaries. - Slave CPU 1 console command START -SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 - Brought up 2 CPUs - SMP: Total of 2 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal new file mode 100644 index 000000000..c2aeea3f1 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -0,0 +1,110 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 2 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 + Bootstraping CPU 1 with sp=0xFFFFFC0000076000 + unix_boot_mem ends at FFFFFC0000078000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 2 CPUs probed -- cpu_present_mask = 3 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP starting up secondaries. + Slave CPU 1 console command START +SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 + Brought up 2 CPUs + SMP: Total of 2 processors activated (8000.15 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console deleted file mode 100644 index 7930e9e46..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ /dev/null @@ -1,105 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal new file mode 100644 index 000000000..7930e9e46 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -0,0 +1,105 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (4002.20 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console deleted file mode 100644 index 89c68d228..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console +++ /dev/null @@ -1,112 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 1000000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (1998756.81 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... -setting up network... -eth0: link now 1000F mbps, full duplex and up. - running netserver... -Starting netserver at port 12865 -signal client to begin...done. -starting bash... -# \ No newline at end of file diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console deleted file mode 100644 index c1cb6aad0..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console +++ /dev/null @@ -1,121 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 1000000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (1998756.81 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... -setting up network... -eth0: link now 1000F mbps, full duplex and up. - waiting for server...server ready -starting test... -netperf warmup -/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k -TCP STREAM TEST to 10.0.0.1 : dirty data -Recv Send Send -Socket Socket Message Elapsed -Size Size Size Time Throughput -bytes bytes bytes secs. 10^6bits/sec - -5000000 5000000 5000000 1.29 30.91 -netperf benchmark -/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144 -TCP STREAM TEST to 10.0.0.1 : dirty data diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal new file mode 100644 index 000000000..89c68d228 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal @@ -0,0 +1,112 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 1000000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (1998756.81 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. + running netserver... +Starting netserver at port 12865 +signal client to begin...done. +starting bash... +# \ No newline at end of file diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal new file mode 100644 index 000000000..c1cb6aad0 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal @@ -0,0 +1,121 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 1000000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (1998756.81 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. + waiting for server...server ready +starting test... +netperf warmup +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k +TCP STREAM TEST to 10.0.0.1 : dirty data +Recv Send Send +Socket Socket Message Elapsed +Size Size Size Time Throughput +bytes bytes bytes secs. 10^6bits/sec + +5000000 5000000 5000000 1.29 30.91 +netperf benchmark +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144 +TCP STREAM TEST to 10.0.0.1 : dirty data -- cgit v1.2.3 From f24f2c57b6cd8dd45681c08d1ddfbd40a2914987 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 18 Jun 2008 11:00:53 -0400 Subject: tests: update tests for slight changes in nsgige posted interrupts --- .../linux/twosys-tsunami-simple-atomic/config.ini | 102 +++++++++++---------- .../linux/twosys-tsunami-simple-atomic/m5stats.txt | 22 ++--- .../linux/twosys-tsunami-simple-atomic/stderr | 10 +- .../linux/twosys-tsunami-simple-atomic/stdout | 14 ++- 4 files changed, 80 insertions(+), 68 deletions(-) (limited to 'tests') diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 151c1ae57..8acd4fb85 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -5,7 +5,7 @@ dummy=0 [drivesys] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.dev/configs/boot/netperf-server.rcS +readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -118,10 +118,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=drivesys.tsunami.pciconfig.pio -port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.console.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma +port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma [drivesys.membus] type=Bus @@ -129,6 +130,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=drivesys.membus.responder.pio @@ -154,18 +156,12 @@ pio=drivesys.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=drivesys.membus.port[1] -[drivesys.sim_console] -type=SimConsole -append_name=true -intr_control=drivesys.intrctrl -number=0 -output=console -port=3456 - [drivesys.simple_disk] type=SimpleDisk children=disk @@ -177,12 +173,30 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[drivesys.terminal] +type=Terminal +intr_control=drivesys.intrctrl +number=0 +output=true +port=3456 + [drivesys.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=drivesys.intrctrl system=drivesys +[drivesys.tsunami.backdoor] +type=AlphaBackdoor +cpu=drivesys.cpu +disk=drivesys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +terminal=drivesys.terminal +pio=drivesys.iobus.port[25] + [drivesys.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -192,17 +206,6 @@ system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.port[1] -[drivesys.tsunami.console] -type=AlphaConsole -cpu=drivesys.cpu -disk=drivesys.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=drivesys.tsunami -sim_console=drivesys.sim_console -system=drivesys -pio=drivesys.iobus.port[25] - [drivesys.tsunami.ethernet] type=NSGigE BAR0=1 @@ -665,8 +668,8 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=drivesys.tsunami -sim_console=drivesys.sim_console system=drivesys +terminal=drivesys.terminal pio=drivesys.iobus.port[24] [etherdump] @@ -685,7 +688,7 @@ int1=drivesys.tsunami.ethernet.interface [testsys] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -694,7 +697,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.dev/configs/boot/netperf-stream-client.rcS +readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -798,10 +801,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=testsys.tsunami.pciconfig.pio -port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.console.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma +port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma [testsys.membus] type=Bus @@ -809,6 +813,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=testsys.membus.responder.pio @@ -834,18 +839,12 @@ pio=testsys.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=testsys.membus.port[1] -[testsys.sim_console] -type=SimConsole -append_name=true -intr_control=testsys.intrctrl -number=0 -output=console -port=3456 - [testsys.simple_disk] type=SimpleDisk children=disk @@ -857,12 +856,30 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[testsys.terminal] +type=Terminal +intr_control=testsys.intrctrl +number=0 +output=true +port=3456 + [testsys.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=testsys.intrctrl system=testsys +[testsys.tsunami.backdoor] +type=AlphaBackdoor +cpu=testsys.cpu +disk=testsys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +terminal=testsys.terminal +pio=testsys.iobus.port[25] + [testsys.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -872,17 +889,6 @@ system=testsys tsunami=testsys.tsunami pio=testsys.iobus.port[1] -[testsys.tsunami.console] -type=AlphaConsole -cpu=testsys.cpu -disk=testsys.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=testsys.tsunami -sim_console=testsys.sim_console -system=testsys -pio=testsys.iobus.port[25] - [testsys.tsunami.ethernet] type=NSGigE BAR0=1 @@ -1345,7 +1351,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=testsys.tsunami -sim_console=testsys.sim_console system=testsys +terminal=testsys.terminal pio=testsys.iobus.port[24] diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 9f3e96104..03c1ec15e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -91,7 +91,7 @@ drivesys.disk2.dma_read_txs 0 # Nu drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post @@ -105,7 +105,7 @@ drivesys.tsunami.ethernet.descDMAWrites 13 # Nu drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU @@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 129173906 # Simulator instruction rate (inst/s) -host_mem_usage 476620 # Number of bytes of host memory used -host_seconds 2.12 # Real time elapsed on the host -host_tick_rate 94522664540 # Simulator tick rate (ticks/s) +host_inst_rate 222632706 # Simulator instruction rate (inst/s) +host_mem_usage 479796 # Number of bytes of host memory used +host_seconds 1.23 # Real time elapsed on the host +host_tick_rate 162907421274 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294782 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -255,14 +255,14 @@ testsys.tsunami.ethernet.coalescedRxOrn 0 # av testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU @@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 134363216323 # Simulator instruction rate (inst/s) -host_mem_usage 476620 # Number of bytes of host memory used +host_inst_rate 225676946325 # Simulator instruction rate (inst/s) +host_mem_usage 479796 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 362870729 # Simulator tick rate (ticks/s) +host_tick_rate 612132399 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294782 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 891b3e205..66e5a984c 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,6 +1,8 @@ -Listening for testsys connection on port 3456 -Listening for drivesys connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb on port 7001 +warn: kernel located at: /dist/m5/system/binaries/vmlinux +Listening for testsys connection on port 3457 +warn: kernel located at: /dist/m5/system/binaries/vmlinux +Listening for drivesys connection on port 3461 +0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7006 +0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 324ab7868..bc3aa034b 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -1,13 +1,17 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2007 15:42:55 -M5 started Tue Aug 21 15:45:44 2007 -M5 executing on nacho -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Jun 18 2008 01:24:58 +M5 started Wed Jun 18 09:39:49 2008 +M5 executing on zizzer +M5 revision 5485:840f91d062a9bd9c980e5959005329c3ed1bc82e +M5 commit date Tue Jun 17 22:22:44 2008 -0700 +command line: /n/zeep/y/binkertn/build/work/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/work/build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second + 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 + 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 4300235844056 because checkpoint -- cgit v1.2.3 From a8df952dd38cb686c6a795480630649aa51fd894 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 22 Jul 2008 17:00:18 -0400 Subject: tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. --- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 2 + .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 14 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../00.gzip/ref/alpha/tru64/simple-atomic/stdout | 14 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 14 +++++ .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 2 + .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 26 ++++---- .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../00.gzip/ref/sparc/linux/simple-atomic/stdout | 26 ++++---- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../00.gzip/ref/sparc/linux/simple-timing/stdout | 26 ++++---- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 4 +- .../00.gzip/ref/x86/linux/simple-atomic/stdout | 26 ++++---- .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../10.mcf/ref/sparc/linux/simple-atomic/stdout | 26 ++++---- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../10.mcf/ref/sparc/linux/simple-timing/stdout | 26 ++++---- .../10.mcf/ref/x86/linux/simple-atomic/config.ini | 4 +- .../long/10.mcf/ref/x86/linux/simple-atomic/stdout | 26 ++++---- .../ref/x86/linux/simple-atomic/config.ini | 4 +- .../20.parser/ref/x86/linux/simple-atomic/stdout | 28 +++++---- .../30.eon/ref/alpha/tru64/o3-timing/config.ini | 2 + tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 14 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../30.eon/ref/alpha/tru64/simple-atomic/stdout | 14 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../30.eon/ref/alpha/tru64/simple-timing/stdout | 14 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../ref/alpha/tru64/simple-atomic/stdout | 14 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../ref/alpha/tru64/simple-timing/stdout | 14 +++++ .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 2 + .../50.vortex/ref/alpha/tru64/o3-timing/stdout | 14 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../50.vortex/ref/alpha/tru64/simple-atomic/stdout | 14 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 14 +++++ .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../50.vortex/ref/sparc/linux/simple-atomic/stdout | 10 +-- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../50.vortex/ref/sparc/linux/simple-timing/stdout | 8 ++- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 2 + .../long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 14 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../60.bzip2/ref/alpha/tru64/simple-atomic/stdout | 14 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../60.bzip2/ref/alpha/tru64/simple-timing/stdout | 14 +++++ .../ref/x86/linux/simple-atomic/config.ini | 4 +- .../60.bzip2/ref/x86/linux/simple-atomic/stdout | 26 ++++---- .../70.twolf/ref/alpha/tru64/o3-timing/config.ini | 2 + .../long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 16 +++++ .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../70.twolf/ref/alpha/tru64/simple-atomic/stdout | 16 +++++ .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../70.twolf/ref/alpha/tru64/simple-timing/stdout | 16 +++++ .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../70.twolf/ref/sparc/linux/simple-atomic/stdout | 30 +++++---- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../70.twolf/ref/sparc/linux/simple-timing/stdout | 32 +++++----- .../ref/x86/linux/simple-atomic/config.ini | 4 +- .../70.twolf/ref/x86/linux/simple-atomic/stdout | 30 +++++---- .../sparc/solaris/t1000-simple-atomic/config.ini | 37 +++++++---- .../ref/sparc/solaris/t1000-simple-atomic/stdout | 10 +-- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 3 + .../00.hello/ref/alpha/linux/o3-timing/stdout | 8 ++- .../ref/alpha/linux/simple-atomic/config.ini | 8 ++- .../00.hello/ref/alpha/linux/simple-atomic/stdout | 12 ++-- .../ref/alpha/linux/simple-timing/config.ini | 3 + .../00.hello/ref/alpha/linux/simple-timing/stdout | 10 +-- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 3 + .../00.hello/ref/alpha/tru64/o3-timing/stdout | 8 ++- .../ref/alpha/tru64/simple-atomic/config.ini | 8 ++- .../00.hello/ref/alpha/tru64/simple-atomic/stdout | 12 ++-- .../ref/alpha/tru64/simple-timing/config.ini | 3 + .../00.hello/ref/alpha/tru64/simple-timing/stdout | 10 +-- .../ref/mips/linux/simple-atomic/config.ini | 72 +++++++++++++++++++++- .../00.hello/ref/mips/linux/simple-atomic/stdout | 12 ++-- .../ref/mips/linux/simple-timing/config.ini | 3 + .../00.hello/ref/mips/linux/simple-timing/stdout | 10 +-- .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../00.hello/ref/sparc/linux/simple-atomic/stdout | 14 +++-- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../00.hello/ref/sparc/linux/simple-timing/stdout | 12 ++-- .../ref/x86/linux/simple-atomic/config.ini | 4 +- .../00.hello/ref/x86/linux/simple-atomic/stdout | 10 +-- .../ref/alpha/linux/o3-timing/config.ini | 4 ++ .../ref/alpha/linux/o3-timing/stdout | 10 +-- .../ref/sparc/linux/o3-timing/config.ini | 3 + .../02.insttest/ref/sparc/linux/o3-timing/stdout | 26 ++++---- .../ref/sparc/linux/simple-atomic/config.ini | 7 ++- .../ref/sparc/linux/simple-atomic/stdout | 26 ++++---- .../ref/sparc/linux/simple-timing/config.ini | 3 + .../ref/sparc/linux/simple-timing/stdout | 26 ++++---- .../linux/tsunami-simple-atomic-dual/config.ini | 56 +++++++++-------- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 8 ++- .../alpha/linux/tsunami-simple-atomic/config.ini | 53 ++++++++-------- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 8 ++- .../linux/tsunami-simple-timing-dual/config.ini | 47 +++++++------- .../alpha/linux/tsunami-simple-timing-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-timing/config.ini | 47 +++++++------- .../ref/alpha/linux/tsunami-simple-timing/stdout | 8 ++- .../ref/alpha/eio/simple-atomic/config.ini | 8 ++- .../ref/alpha/eio/simple-atomic/stdout | 18 +++--- .../ref/alpha/eio/simple-timing/config.ini | 2 + .../ref/alpha/eio/simple-timing/stdout | 16 ++--- .../50.memtest/ref/alpha/linux/memtest/config.ini | 4 ++ .../50.memtest/ref/alpha/linux/memtest/stdout | 6 +- .../linux/twosys-tsunami-simple-atomic/config.ini | 10 +-- .../linux/twosys-tsunami-simple-atomic/stdout | 12 ++-- 110 files changed, 1006 insertions(+), 418 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 595b91bdc..737f0dea4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index 9aaca3eeb..cbeafd848 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:22:47 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index e21c42f32..471b28d35 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 9aaca3eeb..26bc81b05 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:59 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic tests/run.py long/00.gzip/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 87443a024..0c02ed13c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 9aaca3eeb..1faa3f4e8 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:00 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4e87924ca..4219e15b7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index d3d1e3cfb..ce2e79d1f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:25 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Mar 17 2008 06:14:16 -M5 started Mon Mar 17 06:14:18 2008 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second Exiting @ tick 1102714100000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index b267c8dc4..70a42097e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index 5f4ac4eab..e334149fe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:20 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 744759833500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 6c34c6dee..af1b3a07f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index ce05ca938..5597eb1d2 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:09 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second Exiting @ tick 2070157841000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 3572e375e..7f66790fb 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 682b64f8a..79273f082 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:48:56 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 955075963000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index ef3141a33..5c55bdb1c 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index eb0a0f196..8fdd56739 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:36:22 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 122212687000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index a0f77bf10..a9213133f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 8270f923d..5fdb31dc0 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:32 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:46 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second Exiting @ tick 363652229000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index d878cb424..4ca62bb34 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index e519e0a5b..996ca24f1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:45:29 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 165703651500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index af0a9ce63..0b6f15f38 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index b105051a9..2ab0ba3a2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:45:29 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -57,16 +71,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 863350524000 because target called exit() +Exiting @ tick 863350526500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 56c9263b3..bcc536301 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 50ed34325..53e92e76c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:58 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index bfc3d0e40..f1d9f437d 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 5f057b8dd..285c8d750 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -1,2 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:02 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic tests/run.py long/30.eon/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 6912167e0..4e4683ed6 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index f9d497506..9f21edbf0 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:28 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 9054cf093..68b00e416 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index d4a078b85..e78146575 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:58 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 7985d0869..360603943 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index d4a078b85..722e49f95 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:00 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 78b7f1eec..162b46290 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index e69de29bb..f03ee0333 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -0,0 +1,14 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:19:28 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 4745ee94c..337e5e366 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index e69de29bb..f99b33e5f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout @@ -0,0 +1,14 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:14:04 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic tests/run.py long/50.vortex/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 2aab198c9..99587aea2 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index e69de29bb..c568a72c2 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -0,0 +1,14 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:07 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 973d6211f..b8eed166b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 0a780ccee..b230e2c83 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -1,13 +1,15 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:38:08 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 01fab79ce..77a49bdbd 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 5b4fb94a9..592b35b7a 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:46 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:36:59 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 200790381000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index abff97de4..be4327e6c 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index 0c5c00118..da44e8643 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:17:14 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 378e34da6..0768661a6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index 0c5c00118..469f3b36a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:16:25 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic tests/run.py long/60.bzip2/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6adec3b74..48686792e 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index 0c5c00118..c0a8b63da 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:14:59 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index d18301e7c..989908e23 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index 01a877484..17f5ab40f 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:49:02 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data Input data 1048576 bytes in length @@ -12,16 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 2806437159500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 945804e3d..dbf63ca05 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index f32f0a972..20e9ee506 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:14:27 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 8fbd6f60b..f0ed922b1 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index f32f0a972..0fc73d0d9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:59 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic tests/run.py long/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index fd50e16e0..0190cf0fe 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index f32f0a972..a512928ef 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:15:31 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 31489ec58..a772db39f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 8a70482ca..ab5b187b5 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:08 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 96718067000 because target called exit() +122 123 124 Exiting @ tick 96718067000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index fe6c893b2..77060efdc 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index 0d7eb187f..90bf47617 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:34:33 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,18 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:18:16 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 270416976000 because target called exit() +122 123 124 Exiting @ tick 270416976000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index f3b9dea12..27c1d66f3 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index ab6e8b338..a8e5ba7f4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:50:19 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 129915167500 because target called exit() +122 123 124 Exiting @ tick 129915167500 because target called exit() diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 7369c8a0c..2616832f0 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -65,7 +65,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -109,6 +110,8 @@ read_only=true type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=133446500352:133446508543 zero=false port=system.membus.port[7] @@ -123,6 +126,7 @@ children=responder block_size=64 bus_id=0 clock=2 +header_cycles=1 responder_set=false width=64 default=system.iobus.responder.pio @@ -150,6 +154,7 @@ children=responder block_size=64 bus_id=1 clock=2 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -175,6 +180,8 @@ pio=system.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=133429198848:133429207039 zero=false port=system.membus.port[6] @@ -183,6 +190,8 @@ port=system.membus.port[6] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=133445976064:133445984255 zero=false port=system.membus.port[8] @@ -191,6 +200,8 @@ port=system.membus.port[8] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=1048576:68157439 zero=true port=system.membus.port[3] @@ -199,6 +210,8 @@ port=system.membus.port[3] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=2147483648:2415919103 zero=true port=system.membus.port[4] @@ -207,13 +220,15 @@ port=system.membus.port[4] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=1099243192320:1099251580927 zero=false port=system.membus.port[5] [system.t1000] type=T1000 -children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0 +children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 intrctrl=system.intrctrl system=system @@ -409,12 +424,11 @@ update_data=false warn_access= pio=system.iobus.port[10] -[system.t1000.hconsole] -type=SimConsole -append_name=true +[system.t1000.hterm] +type=Terminal intr_control=system.intrctrl number=0 -output=console +output=true port=3456 [system.t1000.htod] @@ -431,8 +445,8 @@ type=Uart8250 pio_addr=1099255955456 pio_latency=2 platform=system.t1000 -sim_console=system.t1000.hconsole system=system +terminal=system.t1000.hterm pio=system.iobus.port[13] [system.t1000.iob] @@ -442,12 +456,11 @@ platform=system.t1000 system=system pio=system.membus.port[0] -[system.t1000.pconsole] -type=SimConsole -append_name=true +[system.t1000.pterm] +type=Terminal intr_control=system.intrctrl number=0 -output=console +output=true port=3456 [system.t1000.puart0] @@ -455,7 +468,7 @@ type=Uart8250 pio_addr=133412421632 pio_latency=2 platform=system.t1000 -sim_console=system.t1000.pconsole system=system +terminal=system.t1000.pterm pio=system.iobus.port[12] diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout index 4c8cf9392..78a121c17 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -1,13 +1,15 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2007 14:42:25 -M5 started Tue Aug 21 14:44:56 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:41:45 +M5 started Mon Jul 21 20:41:46 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1d32ced97..3db01031d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fc63a59a9..05d3c33eb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -1,4 +1,3 @@ -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:32 2008 +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:18:02 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 5303000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 264bd19de..e68e8bc1c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 9af7c0a45..ae7c0fe57 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -1,14 +1,16 @@ -Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:36:58 -M5 started Tue Aug 14 17:40:03 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:07 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 2833500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 7b95a328d..bbb328185 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 11d2e9b8e..c8cf5ab9d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -1,4 +1,3 @@ -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:22 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:14:04 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 19285000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 26f63e7be..2971dacfa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 95bc632c8..abedce50c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -1,4 +1,3 @@ -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:33 2008 +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:59 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 2700000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index ac0ec32b8..74656d464 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -54,9 +55,11 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index d906bb79e..0f1a816dd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -1,14 +1,16 @@ -Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2007 13:46:37 -M5 started Thu Sep 27 20:06:36 2007 -M5 executing on zeep +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:13:07 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 4f7ec60f2..7d543f47c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index c25792a5f..d1bbc80b8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -1,4 +1,3 @@ -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:25 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:24:22 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 9950000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 653ab3552..11bedc8c7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -11,7 +11,62 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb itb tlb tracer workload +CP0_Config=0 +CP0_Config1=0 +CP0_Config1_C2=false +CP0_Config1_CA=false +CP0_Config1_DA=0 +CP0_Config1_DL=0 +CP0_Config1_DS=0 +CP0_Config1_EP=false +CP0_Config1_FP=false +CP0_Config1_IA=0 +CP0_Config1_IL=0 +CP0_Config1_IS=0 +CP0_Config1_M=0 +CP0_Config1_MD=false +CP0_Config1_MMU=0 +CP0_Config1_PC=false +CP0_Config1_WR=false +CP0_Config2=0 +CP0_Config2_M=false +CP0_Config2_SA=0 +CP0_Config2_SL=0 +CP0_Config2_SS=0 +CP0_Config2_SU=0 +CP0_Config2_TA=0 +CP0_Config2_TL=0 +CP0_Config2_TS=0 +CP0_Config2_TU=0 +CP0_Config3=0 +CP0_Config3_DSPP=false +CP0_Config3_LPA=false +CP0_Config3_M=false +CP0_Config3_MT=false +CP0_Config3_SM=false +CP0_Config3_SP=false +CP0_Config3_TL=false +CP0_Config3_VEIC=false +CP0_Config3_VInt=false +CP0_Config_AR=0 +CP0_Config_AT=0 +CP0_Config_BE=0 +CP0_Config_MT=0 +CP0_Config_VI=0 +CP0_EBase_CPUNum=0 +CP0_IntCtl_IPPCI=0 +CP0_IntCtl_IPTI=0 +CP0_PRId=0 +CP0_PRId_CompanyID=0 +CP0_PRId_CompanyOptions=0 +CP0_PRId_ProcessorID=1 +CP0_PRId_Revision=0 +CP0_PerfCtr_M=false +CP0_PerfCtr_W=false +CP0_SrsCtl_HSS=0 +CP0_WatchHi_M=false +UnifiedTLB=true clock=500 cpu_id=0 defer_registration=false @@ -25,8 +80,10 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system +tlb=system.cpu.tlb tracer=system.cpu.tracer width=1 workload=system.cpu.workload @@ -35,9 +92,15 @@ icache_port=system.membus.port[1] [system.cpu.dtb] type=MipsDTB +size=64 [system.cpu.itb] type=MipsITB +size=64 + +[system.cpu.tlb] +type=MipsUTB +size=64 [system.cpu.tracer] type=ExeTracer @@ -52,9 +115,11 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -63,6 +128,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -71,6 +137,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 1cc3f6662..43b61af39 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -1,14 +1,16 @@ -Hello World! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 22:02:23 -M5 started Tue Aug 14 22:02:24 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:31:07 +M5 started Mon Jul 21 20:31:10 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +Hello World! Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 1b246149f..e5f76a0a8 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -234,6 +234,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -251,6 +252,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 4dcddd5ae..37be8fb0c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -1,4 +1,3 @@ -Hello World! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:24:29 -M5 started Sun Feb 24 13:24:31 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:31:07 +M5 started Mon Jul 21 20:31:09 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second +Hello World! Exiting @ tick 19359000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 73da00d73..d13eeb4e2 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index cf86d0964..b07b710c8 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -1,13 +1,15 @@ -Hello World!M5 Simulator System +M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:18 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2447500 because target called exit() +Hello World!Exiting @ tick 2447500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index ef40ce3fd..092061e7f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 12e9a5d09..4d51e2838 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -1,13 +1,15 @@ -Hello World!M5 Simulator System +M5 Simulator System Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:27:50 -M5 started Sun Feb 24 13:28:47 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:08 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 16662000 because target called exit() +Hello World!Exiting @ tick 16662000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 6d8421e24..569d4b220 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -77,6 +78,7 @@ type=PhysicalMemory file= latency=1 latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 80b2e5852..99e187690 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -1,4 +1,3 @@ -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -6,9 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 17 2008 13:48:04 -M5 started Sat May 17 13:48:05 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:45:28 +M5 started Mon Jul 21 20:50:18 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +Hello world! Exiting @ tick 4932000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index d966db2bf..ca040dc25 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -393,6 +394,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -410,6 +412,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 9d1a14d46..1b77a8f81 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -1,5 +1,3 @@ -Hello world! -Hello world! M5 Simulator System Copyright (c) 2001-2008 @@ -7,9 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:35 2008 +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:12:59 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second +Hello world! +Hello world! Exiting @ tick 6363000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index c6ceaa121..e981744fd 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -376,6 +376,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -393,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index ee061a6c6..e6fab5604 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:19 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -9,16 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:54:12 -M5 started Wed Feb 27 18:07:27 2008 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second Exiting @ tick 15392500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index a1a3cadc4..ba8f324ab 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -58,6 +59,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +68,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index c0bb8f23f..6632a0f07 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:18 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -9,16 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second Exiting @ tick 5514000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index f4a82a8e3..fa313ad0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -174,6 +174,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index a0c51dd80..e7f5d2afa 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 21 2008 20:33:06 +M5 started Mon Jul 21 20:33:19 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -9,16 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 12:26:21 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second Exiting @ tick 25237000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index aaa49012b..ecab1a9a6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -53,7 +53,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu0.tracer width=1 @@ -163,7 +164,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu1.tracer width=1 @@ -300,10 +302,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -383,6 +386,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -408,18 +412,12 @@ pio=system.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -431,12 +429,20 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.toL2Bus.responder.pio @@ -460,10 +466,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -473,17 +490,6 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu0 -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 @@ -945,7 +951,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 5f45dab42..a5a0972a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -1,13 +1,15 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 13 2008 00:33:19 -M5 started Wed Feb 13 00:38:27 2008 +M5 compiled Jul 21 2008 20:27:21 +M5 started Mon Jul 21 20:28:09 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1870335151500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index f47a4495c..4ce652819 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -53,7 +53,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -190,10 +191,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -273,6 +275,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -298,18 +301,12 @@ pio=system.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -321,12 +318,20 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.toL2Bus.responder.pio @@ -350,10 +355,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -363,17 +379,6 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 @@ -835,7 +840,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 830f4d057..ac8785088 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -1,13 +1,15 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 13 2008 00:33:19 -M5 started Wed Feb 13 00:37:45 2008 +M5 compiled Jul 21 2008 20:27:21 +M5 started Mon Jul 21 20:27:46 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1828355496000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 1181dac96..459187376 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -300,7 +300,7 @@ header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -406,18 +406,12 @@ pio=system.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -429,6 +423,13 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder @@ -459,10 +460,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -472,17 +484,6 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu0 -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 @@ -944,7 +945,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 84f4de778..18467c41b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2008 17:52:52 -M5 started Wed Feb 27 18:02:58 2008 +M5 compiled Jul 21 2008 20:27:21 +M5 started Mon Jul 21 20:27:23 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1972679592000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 1b52231ed..66d96d325 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -192,7 +192,7 @@ header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -298,18 +298,12 @@ pio=system.membus.default type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -321,6 +315,13 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder @@ -351,10 +352,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -364,17 +376,6 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 @@ -836,7 +837,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index fee547a1f..a429ac712 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:18:14 -M5 started Sun Feb 24 13:19:10 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:27:21 +M5 started Mon Jul 21 20:28:11 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 1931639667000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 9db92d8dc..a0555b3f3 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -25,7 +25,8 @@ max_loads_all_threads=0 max_loads_any_thread=0 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -48,6 +49,8 @@ type=ExeTracer type=EioProcess chkpt= file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 output=cout system=system @@ -56,6 +59,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -64,6 +68,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index fee99ba99..54f73c06e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -1,15 +1,17 @@ -main dictionary has 1245 entries -49508 bytes wasted ->M5 Simulator System +M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:58:14 -M5 started Tue Aug 14 17:58:32 2007 -M5 executing on nacho +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:16:25 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 250015500 because a thread reached the max instruction count +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 766b954c1..ddf7f50b2 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -183,6 +183,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 870de60ce..3f3a9bccf 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -1,15 +1,17 @@ -main dictionary has 1245 entries -49508 bytes wasted ->M5 Simulator System +M5 Simulator System Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:24 2008 -M5 executing on tater +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:18:02 2008 +M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 707548000 because a thread reached the max instruction count +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 707548000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index e04a78cce..1a7e3807d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -429,6 +429,8 @@ mem_side=system.toL2Bus.port[8] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional @@ -483,6 +485,8 @@ port=system.l2c.mem_side system.physmem.port[0] type=PhysicalMemory file= latency=1 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3088b7501..d0d9bd67d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:37 2008 +M5 compiled Jul 21 2008 20:12:56 +M5 started Mon Jul 21 20:18:03 2008 M5 executing on zizzer +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second Exiting @ tick 113467820 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 8acd4fb85..5ae2e325d 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-server.rcS +readfile=/z/binkertn/regress/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -53,7 +53,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=drivesys tracer=drivesys.cpu.tracer width=1 @@ -697,7 +698,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/.automount/zeep/y/binkertn/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/z/binkertn/regress/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -736,7 +737,8 @@ max_loads_any_thread=0 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=testsys tracer=testsys.cpu.tracer width=1 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index bc3aa034b..c137b03cf 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 18 2008 01:24:58 -M5 started Wed Jun 18 09:39:49 2008 +M5 compiled Jul 21 2008 20:27:21 +M5 started Mon Jul 21 20:27:45 2008 M5 executing on zizzer -M5 revision 5485:840f91d062a9bd9c980e5959005329c3ed1bc82e -M5 commit date Tue Jun 17 22:22:44 2008 -0700 -command line: /n/zeep/y/binkertn/build/work/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/work/build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 +M5 commit date Tue Jul 15 14:38:51 2008 -0400 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 4300235844056 because checkpoint -- cgit v1.2.3 From 771dfecf143c2d12e3823689f349fce334f1d276 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 22 Jul 2008 17:00:45 -0400 Subject: Mips was missing a few stats --- .../ref/mips/linux/simple-atomic/m5stats.txt | 44 ++++++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 23e6b5f2c..7c3074e0a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,18 +1,54 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 9753 # Simulator instruction rate (inst/s) -host_mem_usage 173424 # Number of bytes of host memory used -host_seconds 0.58 # Real time elapsed on the host -host_tick_rate 4872477 # Simulator tick rate (ticks/s) +host_inst_rate 493457 # Simulator instruction rate (inst/s) +host_mem_usage 191128 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 241461749 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated sim_ticks 2828000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5657 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.tlb.write_misses 0 # DTB write misses system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3 From 9389ede894895999bf6cb20da64aa5b4c3a400b0 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 22 Jul 2008 17:01:33 -0400 Subject: tests: There's a small unknown stats difference in 20.parser, accept it. Hopefully if the difference pops back up, we can figure out what it was --- .../20.parser/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index 5ab585992..b17c478f6 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1959706 # Simulator instruction rate (inst/s) -host_mem_usage 194472 # Number of bytes of host memory used -host_seconds 757.68 # Real time elapsed on the host -host_tick_rate 1139469005 # Simulator tick rate (ticks/s) +host_inst_rate 1698420 # Simulator instruction rate (inst/s) +host_mem_usage 197800 # Number of bytes of host memory used +host_seconds 874.24 # Real time elapsed on the host +host_tick_rate 987544116 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484825787 # Number of instructions simulated +sim_insts 1484825792 # Number of instructions simulated sim_seconds 0.863351 # Number of seconds simulated -sim_ticks 863350524000 # Number of ticks simulated +sim_ticks 863350526500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726701049 # number of cpu cycles simulated -system.cpu.num_insts 1484825787 # Number of instructions executed +system.cpu.numCycles 1726701054 # number of cpu cycles simulated +system.cpu.num_insts 1484825792 # Number of instructions executed system.cpu.num_refs 533543283 # Number of memory references system.cpu.workload.PROG:num_syscalls 541 # Number of system calls -- cgit v1.2.3 From 0622eec53ae87e008a8d5e0e685321c69ea401d3 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 24 Jul 2008 16:31:54 -0700 Subject: regress: update regressions for tty emulation fix. --- .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 1 + .../00.gzip/ref/sparc/linux/o3-timing/m5stats.txt | 556 +++++++-------- .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 22 +- .../00.gzip/ref/sparc/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 1 + .../ref/sparc/linux/simple-timing/m5stats.txt | 244 +++---- .../00.gzip/ref/sparc/linux/simple-timing/stdout | 12 +- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 1 + .../ref/x86/linux/simple-atomic/m5stats.txt | 22 +- .../00.gzip/ref/x86/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 22 +- .../10.mcf/ref/sparc/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 1 + .../ref/sparc/linux/simple-timing/m5stats.txt | 220 +++--- .../10.mcf/ref/sparc/linux/simple-timing/stdout | 12 +- .../10.mcf/ref/x86/linux/simple-atomic/config.ini | 1 + .../10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 22 +- .../long/10.mcf/ref/x86/linux/simple-atomic/stdout | 12 +- .../ref/x86/linux/simple-atomic/config.ini | 1 + .../ref/x86/linux/simple-atomic/m5stats.txt | 22 +- .../20.parser/ref/x86/linux/simple-atomic/stdout | 12 +- .../ref/x86/linux/simple-atomic/config.ini | 1 + .../ref/x86/linux/simple-atomic/m5stats.txt | 22 +- .../60.bzip2/ref/x86/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 22 +- .../70.twolf/ref/sparc/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 1 + .../ref/sparc/linux/simple-timing/m5stats.txt | 206 +++--- .../70.twolf/ref/sparc/linux/simple-timing/stdout | 12 +- .../ref/x86/linux/simple-atomic/config.ini | 1 + .../ref/x86/linux/simple-atomic/m5stats.txt | 22 +- .../70.twolf/ref/x86/linux/simple-atomic/stdout | 12 +- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 1 + .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 498 ++++++------- .../00.hello/ref/alpha/linux/o3-timing/stdout | 12 +- .../ref/alpha/linux/simple-atomic/config.ini | 1 + .../ref/alpha/linux/simple-atomic/m5stats.txt | 34 +- .../00.hello/ref/alpha/linux/simple-atomic/stdout | 12 +- .../ref/alpha/linux/simple-timing/config.ini | 1 + .../ref/alpha/linux/simple-timing/m5stats.txt | 190 ++--- .../00.hello/ref/alpha/linux/simple-timing/stdout | 12 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 20 +- .../00.hello/ref/sparc/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 1 + .../ref/sparc/linux/simple-timing/m5stats.txt | 172 ++--- .../00.hello/ref/sparc/linux/simple-timing/stdout | 12 +- .../ref/x86/linux/simple-atomic/config.ini | 1 + .../ref/x86/linux/simple-atomic/m5stats.txt | 20 +- .../00.hello/ref/x86/linux/simple-atomic/stdout | 12 +- .../ref/alpha/linux/o3-timing/config.ini | 2 + .../ref/alpha/linux/o3-timing/m5stats.txt | 769 +++++++++++---------- .../ref/alpha/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/o3-timing/config.ini | 1 + .../ref/sparc/linux/o3-timing/m5stats.txt | 526 +++++++------- .../02.insttest/ref/sparc/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 22 +- .../ref/sparc/linux/simple-atomic/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 1 + .../ref/sparc/linux/simple-timing/m5stats.txt | 220 +++--- .../ref/sparc/linux/simple-timing/stdout | 12 +- 66 files changed, 2092 insertions(+), 2068 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4219e15b7..0b846692f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 623095a72..1aaf64650 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 181883102 # Number of BTB hits -global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups +global.BPredUnit.BTBHits 181900655 # Number of BTB hits +global.BPredUnit.BTBLookups 205112403 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted -global.BPredUnit.lookups 253548806 # Number of BP lookups +global.BPredUnit.condIncorrect 84376140 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 253553370 # Number of conditional branches predicted +global.BPredUnit.lookups 253553370 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 60603 # Simulator instruction rate (inst/s) -host_mem_usage 181372 # Number of bytes of host memory used -host_seconds 23193.76 # Real time elapsed on the host -host_tick_rate 47543564 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit. +host_inst_rate 148554 # Simulator instruction rate (inst/s) +host_mem_usage 214964 # Number of bytes of host memory used +host_seconds 9461.99 # Real time elapsed on the host +host_tick_rate 116526717 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 445262703 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 137431528 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 741823023 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 303434035 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405610550 # Number of instructions simulated -sim_seconds 1.102714 # Number of seconds simulated -sim_ticks 1102714100000 # Number of ticks simulated -system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached +sim_insts 1405618364 # Number of instructions simulated +sim_seconds 1.102575 # Number of seconds simulated +sim_ticks 1102574586000 # Number of ticks simulated +system.cpu.commit.COM:branches 86248929 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 8144949 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1965947566 +system.cpu.commit.COM:committed_per_cycle.samples 1965667914 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1089819992 5543.48% - 1 575192807 2925.78% - 2 120683737 613.87% - 3 121997081 620.55% - 4 27903521 141.93% - 5 7399306 37.64% - 6 10435277 53.08% - 7 4371587 22.24% - 8 8144258 41.43% + 0 1089833449 5544.34% + 1 574599936 2923.18% + 2 120982749 615.48% + 3 121997991 620.64% + 4 27903349 141.95% + 5 7399398 37.64% + 6 10434529 53.08% + 7 4371564 22.24% + 8 8144949 41.44% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489528973 # Number of instructions committed -system.cpu.commit.COM:loads 402516086 # Number of loads committed +system.cpu.commit.COM:count 1489537507 # Number of instructions committed +system.cpu.commit.COM:loads 402517242 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569373868 # Number of memory references committed +system.cpu.commit.COM:refs 569375198 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405610550 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated -system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 431513840 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5832.966573 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles +system.cpu.commit.branchMispredicts 84376140 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537507 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1379626157 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618364 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618364 # Number of Instructions Simulated +system.cpu.cpi 1.568811 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568811 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 431515523 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5833.098785 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.922588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 430678453 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4882712000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 837060 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 837070 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 610026 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 676346500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 227044 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency @@ -72,51 +72,51 @@ system.cpu.dcache.SwapReq_misses 40 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166856456 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 10313.606533 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 10313.448208 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.282564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164722472 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22010528000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2134144 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002050 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_misses 2134158 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1792190 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2651716500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002049 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 341968 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1192.980326 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1192.957701 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 598370296 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9051.301930 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004965 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2971204 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 598372153 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9051.220573 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency +system.cpu.dcache.demand_hits 595400925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26893240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.004966 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2971228 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2402216 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3328063000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 569012 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 598370296 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9051.301930 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 598372153 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9051.220573 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595399092 # number of overall hits -system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004965 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2971204 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 595400925 # number of overall hits +system.cpu.dcache.overall_miss_latency 26893240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.004966 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2971228 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2402216 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3328063000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 569012 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 495151 # number of replacements -system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 495162 # number of replacements +system.cpu.dcache.sampled_refs 499258 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use -system.cpu.dcache.total_refs 595591849 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338813 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched -system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.748023 # Cycle average of tags in use +system.cpu.dcache.total_refs 595593676 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87021000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338803 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 411671419 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3446173364 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 768410177 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782727450 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239480011 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2858868 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 253553370 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 356679957 # Number of cache lines fetched +system.cpu.fetch.Cycles 1203446624 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10248361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3739591650 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 90314479 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114982 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 356679957 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 181900655 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.695845 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2205426950 +system.cpu.fetch.rateDist.samples 2205147925 system.cpu.fetch.rateDist.min_value 0 - 0 1358665764 6160.56% - 1 256941668 1165.04% - 2 81115553 367.80% - 3 38329197 173.79% - 4 87812032 398.16% - 5 41184299 186.74% - 6 30948569 140.33% - 7 20663338 93.69% - 8 289766530 1313.88% + 0 1358381303 6160.05% + 1 256975915 1165.35% + 2 81117048 367.85% + 3 38328968 173.82% + 4 87811486 398.21% + 5 41185341 186.77% + 6 30948688 140.35% + 7 20663450 93.71% + 8 289735726 1313.91% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 356679455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8992.990654 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 356679957 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8956.578947 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6409.949165 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 356678437 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13614000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1498 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1520 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 8826500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1377 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 259025.734931 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356679455 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8992.990654 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency -system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 356679957 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8956.578947 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency +system.cpu.icache.demand_hits 356678437 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13614000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1498 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1520 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 8826500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1377 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 356679455 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8992.990654 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency +system.cpu.icache.overall_accesses 356679957 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8956.578947 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 356677957 # number of overall hits -system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles +system.cpu.icache.overall_hits 356678437 # number of overall hits +system.cpu.icache.overall_miss_latency 13614000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1498 # number of overall misses -system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1520 # number of overall misses +system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 8826500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1377 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -222,180 +222,180 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 208 # number of replacements -system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. +system.cpu.icache.replacements 225 # number of replacements +system.cpu.icache.sampled_refs 1377 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use -system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1055.483361 # Cycle average of tags in use +system.cpu.icache.total_refs 356678437 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 127605912 # Number of branches executed -system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate -system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 205327510 # Number of stores executed +system.cpu.idleCycles 1248 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 127608554 # Number of branches executed +system.cpu.iew.EXEC:nop 350339648 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.854427 # Inst execution rate +system.cpu.iew.EXEC:refs 751913263 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 205327824 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value -system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back +system.cpu.iew.WB:consumers 1480064020 # num instructions consuming a value +system.cpu.iew.WB:count 1846024853 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.961974 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1423779046 # num instructions producing a value -system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle -system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1423783452 # num instructions producing a value +system.cpu.iew.WB:rate 0.837143 # insts written-back per cycle +system.cpu.iew.WB:sent 1859136578 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 92169933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 589367 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 741823023 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21373777 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17132653 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 303434035 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2869227464 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 546585439 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 102564755 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1884138731 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 34478 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6242 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239480011 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64953 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115050896 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 46197 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 6187252 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 339305781 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 136576079 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6187252 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1512583 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90657350 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637426 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1986703486 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1179867838 59.39% # Type of FU issued + IntAlu 1179878973 59.39% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3034528 0.15% # Type of FU issued + FloatAdd 3034527 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 573302529 28.86% # Type of FU issued - MemWrite 230484959 11.60% # Type of FU issued + MemRead 573304663 28.86% # Type of FU issued + MemWrite 230485323 11.60% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 3941252 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143231 3.63% # attempts to use FU when none available + IntAlu 143239 3.63% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 224126 5.69% # attempts to use FU when none available + FloatAdd 224135 5.69% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3231195 81.98% # attempts to use FU when none available - MemWrite 342659 8.69% # attempts to use FU when none available + MemRead 3231256 81.99% # attempts to use FU when none available + MemWrite 342622 8.69% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2205147925 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1088269781 4934.51% - 1 585554812 2655.06% - 2 294018661 1333.16% - 3 167298864 758.58% - 4 47518780 215.46% - 5 16542191 75.01% - 6 5287334 23.97% - 7 801167 3.63% - 8 135360 0.61% + 0 1087983599 4933.83% + 1 585856114 2656.77% + 2 293424201 1330.63% + 3 167599230 760.04% + 4 47518525 215.49% + 5 16542278 75.02% + 6 5287445 23.98% + 7 801144 3.63% + 8 135389 0.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate -system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.900938 # Inst issue rate +system.cpu.iq.iqInstsAdded 2497217188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1986703486 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21670628 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1069660701 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 613054 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19426957 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1294993120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 272214 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 5811.034701 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2811.034701 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1581845000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 272214 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 765203000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 272214 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 228421 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5108.517819 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.517819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 193459 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 178604000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153059 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73718000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34962 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 69801 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.620192 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.777783 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 363706500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 69801 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154314500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 69801 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338803 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338803 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.926755 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 500635 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5731.075996 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 193459 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1760449000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.613573 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 307176 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 838921000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.613573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 307176 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 500635 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5731.075996 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 193435 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 307165 # number of overall misses +system.cpu.l2cache.overall_hits 193459 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1760449000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.613573 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 307176 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 838921000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.613573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 307176 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -407,32 +407,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84439 # number of replacements -system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84458 # number of replacements +system.cpu.l2cache.sampled_refs 99911 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use -system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16412.598383 # Cycle average of tags in use +system.cpu.l2cache.total_refs 392326 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61955 # number of writebacks -system.cpu.numCycles 2205428201 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed +system.cpu.l2cache.writebacks 61939 # number of writebacks +system.cpu.numCycles 2205149173 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14473235 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779248 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed -system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.rename.RENAME:IQFullEvents 33041 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 831090066 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23088137 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4934375551 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3102245036 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2427299354 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 719533567 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239480011 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32278503 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1182520106 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 368292543 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 22008551 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170259176 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21764852 # count of temporary serializing insts renamed +system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index ce2e79d1f..e3c9fc9e3 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:25 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:54 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1102714100000 because target called exit() +Exiting @ tick 1102574586000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 70a42097e..ea30aeebe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index a5fcdb950..7483949da 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3930303 # Simulator instruction rate (inst/s) -host_mem_usage 176592 # Number of bytes of host memory used -host_seconds 378.98 # Real time elapsed on the host -host_tick_rate 1965156849 # Simulator tick rate (ticks/s) +host_inst_rate 4187360 # Simulator instruction rate (inst/s) +host_mem_usage 206704 # Number of bytes of host memory used +host_seconds 355.72 # Real time elapsed on the host +host_tick_rate 2093685937 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 0.744760 # Number of seconds simulated -sim_ticks 744759833500 # Number of ticks simulated +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 0.744764 # Number of seconds simulated +sim_ticks 744764119000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489519668 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index e334149fe..f085a464a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:20 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:03:21 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 744759833500 because target called exit() +Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index af1b3a07f..f120ae25d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 49a7103b2..db0a24071 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1554729 # Simulator instruction rate (inst/s) -host_mem_usage 223840 # Number of bytes of host memory used -host_seconds 958.05 # Real time elapsed on the host -host_tick_rate 2160793398 # Simulator tick rate (ticks/s) +host_inst_rate 2417575 # Simulator instruction rate (inst/s) +host_mem_usage 214112 # Number of bytes of host memory used +host_seconds 616.12 # Real time elapsed on the host +host_tick_rate 3359990664 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070158 # Number of seconds simulated -sim_ticks 2070157841000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.070168 # Number of seconds simulated +sim_ticks 2070168106000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16193.228451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13193.228451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3133163000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2552705000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency @@ -28,50 +28,50 @@ system.cpu.dcache.SwapReq_misses 40 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 8629063000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7670278000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22924.696101 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 11762226000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10222983000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22924.696101 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 11762226000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513071 # number of overall misses +system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10222983000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,57 +83,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449114 # number of replacements -system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316430 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4095.496088 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 375475000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316420 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26953.026197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.026197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29837000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 26516000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26953.026197 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 29837000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26516000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26953.026197 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles +system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_miss_latency 29837000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_misses 1107 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26516000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -145,78 +145,78 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 115 # number of replacements -system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use -system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.562887 # Cycle average of tags in use +system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5973905000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857085000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 776158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 371206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232053 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1377654000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658900000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316430 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.429642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6750063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3228181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3228291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160837 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293471 # number of overall misses +system.cpu.l2cache.overall_hits 160847 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6750063000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293481 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3228181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3228291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,17 +228,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82889 # number of replacements -system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82905 # number of replacements +system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16362.166769 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61877 # number of writebacks +system.cpu.l2cache.writebacks 61861 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4140315682 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 4140336212 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 5597eb1d2..ee95b95c4 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:09 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:02:08 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2070157841000 because target called exit() +Exiting @ tick 2070168106000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 7f66790fb..7cc249f17 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=gzip input.log 1 cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index 1dc72cfa0..9e6571b45 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1900139 # Simulator instruction rate (inst/s) -host_mem_usage 190872 # Number of bytes of host memory used -host_seconds 844.13 # Real time elapsed on the host -host_tick_rate 1131428996 # Simulator tick rate (ticks/s) +host_inst_rate 2111657 # Simulator instruction rate (inst/s) +host_mem_usage 206000 # Number of bytes of host memory used +host_seconds 759.59 # Real time elapsed on the host +host_tick_rate 1257375756 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1603968718 # Number of instructions simulated -sim_seconds 0.955076 # Number of seconds simulated -sim_ticks 955075963000 # Number of ticks simulated +sim_insts 1603986018 # Number of instructions simulated +sim_seconds 0.955086 # Number of seconds simulated +sim_ticks 955086010500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1910151927 # number of cpu cycles simulated -system.cpu.num_insts 1603968718 # Number of instructions executed -system.cpu.num_refs 607157396 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu.numCycles 1910172022 # number of cpu cycles simulated +system.cpu.num_insts 1603986018 # Number of instructions executed +system.cpu.num_refs 607160103 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 79273f082..cca1d58a5 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:48:56 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:08:42 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 955075963000 because target called exit() +Exiting @ tick 955086010500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 5c55bdb1c..b08c16b82 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=mcf mcf.in cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 15b900ea5..f2490f7d0 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3600198 # Simulator instruction rate (inst/s) -host_mem_usage 308780 # Number of bytes of host memory used -host_seconds 67.73 # Real time elapsed on the host -host_tick_rate 1804495302 # Simulator tick rate (ticks/s) +host_inst_rate 3434883 # Simulator instruction rate (inst/s) +host_mem_usage 338884 # Number of bytes of host memory used +host_seconds 70.99 # Real time elapsed on the host +host_tick_rate 1721637062 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.122213 # Number of seconds simulated -sim_ticks 122212687000 # Number of ticks simulated +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.122216 # Number of seconds simulated +sim_ticks 122215830000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 244425375 # number of cpu cycles simulated -system.cpu.num_insts 243829010 # Number of instructions executed -system.cpu.num_refs 105710359 # Number of memory references -system.cpu.workload.PROG:num_syscalls 428 # Number of system calls +system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index 8fdd56739..772308160 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:36:22 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:56 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 122212687000 because target called exit() +Exiting @ tick 122215830000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index a9213133f..a9975c5c8 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=mcf mcf.in cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 7fe2ea602..797c83359 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 892340 # Simulator instruction rate (inst/s) -host_mem_usage 338704 # Number of bytes of host memory used -host_seconds 273.25 # Real time elapsed on the host -host_tick_rate 1330855666 # Simulator tick rate (ticks/s) +host_inst_rate 2198270 # Simulator instruction rate (inst/s) +host_mem_usage 346304 # Number of bytes of host memory used +host_seconds 110.92 # Real time elapsed on the host +host_tick_rate 3278529226 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.363652 # Number of seconds simulated -sim_ticks 363652229000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14002.970284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.970284 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12502468000 # number of ReadReq miss cycles +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.363660 # Number of seconds simulated +sim_ticks 363659868000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14002.999360 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.999360 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12502676000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9823936000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9824105000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency @@ -28,10 +28,10 @@ system.cpu.dcache.SwapReq_misses 8 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 192000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 22806873 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2564001000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses @@ -40,38 +40,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # m system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 110.887563 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15252.442026 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency -system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15066469000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 15252.451864 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency +system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15066677000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses -system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12103048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 12103217000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15252.442026 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 15252.451864 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 104133498 # number of overall hits -system.cpu.dcache.overall_miss_latency 15066469000 # number of overall miss cycles +system.cpu.dcache.overall_hits 104134565 # number of overall hits +system.cpu.dcache.overall_miss_latency 15066677000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses -system.cpu.dcache.overall_misses 987807 # number of overall misses +system.cpu.dcache.overall_misses 987820 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12103048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 12103217000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,57 +83,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 935465 # number of replacements -system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 935475 # number of replacements +system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3567.172946 # Cycle average of tags in use -system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134200939000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 3566.422282 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134205827000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26970.420933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.420933 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23707000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26970.521542 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.521542 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 23788000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 21070000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 21142000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 278071.060296 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26970.420933 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency -system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23707000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26970.521542 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency +system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 23788000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 879 # number of demand (read+write) misses +system.cpu.icache.demand_misses 882 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21070000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21142000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26970.420933 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency +system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26970.521542 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244424462 # number of overall hits -system.cpu.icache.overall_miss_latency 23707000 # number of overall miss cycles +system.cpu.icache.overall_hits 244430745 # number of overall hits +system.cpu.icache.overall_miss_latency 23788000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 879 # number of overall misses +system.cpu.icache.overall_misses 882 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21070000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21142000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -146,77 +146,77 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.881678 # Cycle average of tags in use -system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 725.877742 # Cycle average of tags in use +system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 46717 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1074491000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1074422000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 46717 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 513887000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 513854000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 46717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 892642 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 24863000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11891000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 24978000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1109842000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1109911000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 48254 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530827000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 51.564846 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 892642 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1099354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.050825 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 47798 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1099400000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 525778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.050825 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 47798 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 525800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 940440 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 892642 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1099354000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.050825 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 47798 # number of overall misses +system.cpu.l2cache.overall_hits 892653 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1099400000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47800 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 525778000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.050825 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 47798 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 525800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,17 +228,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 877 # number of replacements -system.cpu.l2cache.sampled_refs 15560 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 891 # number of replacements +system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8941.212243 # Cycle average of tags in use -system.cpu.l2cache.total_refs 802349 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8943.216339 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 727304458 # number of cpu cycles simulated -system.cpu.num_insts 243829010 # Number of instructions executed -system.cpu.num_refs 105710359 # Number of memory references -system.cpu.workload.PROG:num_syscalls 428 # Number of system calls +system.cpu.numCycles 727319736 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 5fdb31dc0..66cc737ad 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:32 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:53 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 363652229000 because target called exit() +Exiting @ tick 363659868000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 4ca62bb34..e2db98cec 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=mcf mcf.in cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index b1bff08e1..e2d716404 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1573393 # Simulator instruction rate (inst/s) -host_mem_usage 325380 # Number of bytes of host memory used -host_seconds 171.38 # Real time elapsed on the host -host_tick_rate 966895627 # Simulator tick rate (ticks/s) +host_inst_rate 2310204 # Simulator instruction rate (inst/s) +host_mem_usage 340492 # Number of bytes of host memory used +host_seconds 116.72 # Real time elapsed on the host +host_tick_rate 1419682765 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269643040 # Number of instructions simulated -sim_seconds 0.165704 # Number of seconds simulated -sim_ticks 165703651500 # Number of ticks simulated +sim_insts 269654744 # Number of instructions simulated +sim_seconds 0.165710 # Number of seconds simulated +sim_ticks 165710415000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331407304 # number of cpu cycles simulated -system.cpu.num_insts 269643040 # Number of instructions executed -system.cpu.num_refs 124052668 # Number of memory references -system.cpu.workload.PROG:num_syscalls 429 # Number of system calls +system.cpu.numCycles 331420831 # number of cpu cycles simulated +system.cpu.num_insts 269654744 # Number of instructions executed +system.cpu.num_refs 124054658 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index 996ca24f1..ac908f417 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:45:29 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:09:15 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165703651500 because target called exit() +Exiting @ tick 165710415000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 0b6f15f38..3a3046603 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=parser 2.1.dict -batch cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index b17c478f6..9ef50e95e 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1698420 # Simulator instruction rate (inst/s) -host_mem_usage 197800 # Number of bytes of host memory used -host_seconds 874.24 # Real time elapsed on the host -host_tick_rate 987544116 # Simulator tick rate (ticks/s) +host_inst_rate 2071310 # Simulator instruction rate (inst/s) +host_mem_usage 209664 # Number of bytes of host memory used +host_seconds 716.88 # Real time elapsed on the host +host_tick_rate 1204360345 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484825792 # Number of instructions simulated -sim_seconds 0.863351 # Number of seconds simulated -sim_ticks 863350526500 # Number of ticks simulated +sim_insts 1484872746 # Number of instructions simulated +sim_seconds 0.863378 # Number of seconds simulated +sim_ticks 863377516000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726701054 # number of cpu cycles simulated -system.cpu.num_insts 1484825792 # Number of instructions executed -system.cpu.num_refs 533543283 # Number of memory references -system.cpu.workload.PROG:num_syscalls 541 # Number of system calls +system.cpu.numCycles 1726755033 # number of cpu cycles simulated +system.cpu.num_insts 1484872746 # Number of instructions executed +system.cpu.num_refs 533549003 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index 2ab0ba3a2..ea6ac1298 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:45:29 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:09:17 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 863350526500 because target called exit() +Exiting @ tick 863377516000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 989908e23..3ebce331c 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=bzip2 input.source 1 cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index d84d96131..9b7f29b45 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1870134 # Simulator instruction rate (inst/s) -host_mem_usage 190768 # Number of bytes of host memory used -host_seconds 2457.40 # Real time elapsed on the host -host_tick_rate 1142033656 # Simulator tick rate (ticks/s) +host_inst_rate 2222828 # Simulator instruction rate (inst/s) +host_mem_usage 206012 # Number of bytes of host memory used +host_seconds 2067.49 # Real time elapsed on the host +host_tick_rate 1357412596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4595673436 # Number of instructions simulated -sim_seconds 2.806437 # Number of seconds simulated -sim_ticks 2806437159500 # Number of ticks simulated +sim_insts 4595681265 # Number of instructions simulated +sim_seconds 2.806442 # Number of seconds simulated +sim_ticks 2806441694500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5612874320 # number of cpu cycles simulated -system.cpu.num_insts 4595673436 # Number of instructions executed -system.cpu.num_refs 1686312529 # Number of memory references -system.cpu.workload.PROG:num_syscalls 33 # Number of system calls +system.cpu.numCycles 5612883390 # number of cpu cycles simulated +system.cpu.num_insts 4595681265 # Number of instructions executed +system.cpu.num_refs 1686313784 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index 17f5ab40f..32d78ce58 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:49:02 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:11:12 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2806437159500 because target called exit() +Exiting @ tick 2806441694500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index a772db39f..217cd2719 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=twolf smred cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 241142dbb..e8167a62f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2449488 # Simulator instruction rate (inst/s) -host_mem_usage 181120 # Number of bytes of host memory used -host_seconds 78.97 # Real time elapsed on the host -host_tick_rate 1224747555 # Simulator tick rate (ticks/s) +host_inst_rate 3028318 # Simulator instruction rate (inst/s) +host_mem_usage 211228 # Number of bytes of host memory used +host_seconds 63.88 # Real time elapsed on the host +host_tick_rate 1514162901 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435005 # Number of instructions simulated -sim_seconds 0.096718 # Number of seconds simulated -sim_ticks 96718067000 # Number of ticks simulated +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722951500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 193436135 # number of cpu cycles simulated -system.cpu.num_insts 193435005 # Number of instructions executed -system.cpu.num_refs 76733003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 396 # Number of system calls +system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index ab5b187b5..0ed160885 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:08 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:04:15 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96718067000 because target called exit() +122 123 124 Exiting @ tick 96722951500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 77060efdc..a7e0f9783 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=twolf smred cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index b8ccd7e90..6a57afc45 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1067073 # Simulator instruction rate (inst/s) -host_mem_usage 203488 # Number of bytes of host memory used -host_seconds 181.28 # Real time elapsed on the host -host_tick_rate 1491737734 # Simulator tick rate (ticks/s) +host_inst_rate 1517830 # Simulator instruction rate (inst/s) +host_mem_usage 218636 # Number of bytes of host memory used +host_seconds 127.45 # Real time elapsed on the host +host_tick_rate 2121861871 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435005 # Number of instructions simulated -sim_seconds 0.270417 # Number of seconds simulated -sim_ticks 270416976000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.270428 # Number of seconds simulated +sim_ticks 270428013000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses @@ -28,50 +28,50 @@ system.cpu.dcache.SwapReq_misses 2 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 29970000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 29916000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 26640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 26592000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 48472.729627 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43416000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 43362000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 38592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 38544000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76708944 # number of overall hits -system.cpu.dcache.overall_miss_latency 43416000 # number of overall miss cycles +system.cpu.dcache.overall_hits 76709902 # number of overall hits +system.cpu.dcache.overall_miss_latency 43362000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1608 # number of overall misses +system.cpu.dcache.overall_misses 1606 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 38592000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 38544000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -84,56 +84,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 26 # number of replacements -system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.389513 # Cycle average of tags in use -system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1235.387438 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks -system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 17803.146397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 14803.146397 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 218409000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 181605000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 17805.419922 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 14805.419922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 218793000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 181929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15766.526736 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 17803.146397 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency -system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 218409000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses -system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 17805.419922 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency +system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 218793000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 181605000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 181929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 17803.146397 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency +system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 17805.419922 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193423750 # number of overall hits -system.cpu.icache.overall_miss_latency 218409000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses -system.cpu.icache.overall_misses 12268 # number of overall misses +system.cpu.icache.overall_hits 193433499 # number of overall hits +system.cpu.icache.overall_miss_latency 218793000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_misses 12288 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 181605000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 181929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -145,33 +145,33 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 10342 # number of replacements -system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. +system.cpu.icache.replacements 10362 # number of replacements +system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.711897 # Cycle average of tags in use -system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.780933 # Cycle average of tags in use +system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 25001000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 24955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 11935000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94001000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 94185000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 45045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -185,38 +185,38 @@ system.cpu.l2cache.Writeback_accesses 23 # nu system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.128249 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.127019 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 119002000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 119140000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 56914000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373493 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 56980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8679 # number of overall hits -system.cpu.l2cache.overall_miss_latency 119002000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5174 # number of overall misses +system.cpu.l2cache.overall_hits 8691 # number of overall hits +system.cpu.l2cache.overall_miss_latency 119140000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5180 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 56914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.373493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 56980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,16 +229,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2649.681897 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2657.731325 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 540833952 # number of cpu cycles simulated -system.cpu.num_insts 193435005 # Number of instructions executed -system.cpu.num_refs 76733003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 396 # Number of system calls +system.cpu.numCycles 540856026 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index 90bf47617..bac654c3b 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:34:33 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:02:07 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 270416976000 because target called exit() +122 123 124 Exiting @ tick 270428013000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index 27c1d66f3..bdad08432 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=twolf smred cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index 8ea3b34db..3c3b5e445 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1442472 # Simulator instruction rate (inst/s) -host_mem_usage 197924 # Number of bytes of host memory used -host_seconds 151.41 # Real time elapsed on the host -host_tick_rate 858020061 # Simulator tick rate (ticks/s) +host_inst_rate 1772433 # Simulator instruction rate (inst/s) +host_mem_usage 213128 # Number of bytes of host memory used +host_seconds 123.23 # Real time elapsed on the host +host_tick_rate 1054286984 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218408389 # Number of instructions simulated -sim_seconds 0.129915 # Number of seconds simulated -sim_ticks 129915167500 # Number of ticks simulated +sim_insts 218419088 # Number of instructions simulated +sim_seconds 0.129921 # Number of seconds simulated +sim_ticks 129921260000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259830336 # number of cpu cycles simulated -system.cpu.num_insts 218408389 # Number of instructions executed -system.cpu.num_refs 77164404 # Number of memory references -system.cpu.workload.PROG:num_syscalls 395 # Number of system calls +system.cpu.numCycles 259842521 # number of cpu cycles simulated +system.cpu.num_insts 218419088 # Number of instructions executed +system.cpu.num_refs 77165367 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index a8e5ba7f4..793e5c943 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:50:19 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:12:24 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 129915167500 because target called exit() +122 123 124 Exiting @ tick 129921260000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 3db01031d..f857ba9ca 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cd104d2c8..dd4839763 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 574 # Number of BTB hits -global.BPredUnit.BTBLookups 1715 # Number of BTB lookups -global.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 425 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted -global.BPredUnit.lookups 2013 # Number of BP lookups -global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44727 # Simulator instruction rate (inst/s) -host_mem_usage 151980 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 42091644 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1228 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 665 # Number of BTB hits +global.BPredUnit.BTBLookups 1852 # Number of BTB lookups +global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted +global.BPredUnit.lookups 2168 # Number of BP lookups +global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target. +host_inst_rate 54768 # Simulator instruction rate (inst/s) +host_mem_usage 209744 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 47820234 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 112 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5303000 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 89 # number cycles where commit BW limit reached +sim_insts 6297 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5506500 # Number of ticks simulated +system.cpu.commit.COM:branches 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9365 +system.cpu.commit.COM:committed_per_cycle.samples 9764 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7035 7512.01% - 1 1204 1285.64% - 2 411 438.87% - 3 192 205.02% - 4 145 154.83% - 5 90 96.10% - 6 97 103.58% - 7 102 108.92% - 8 89 95.03% + 0 7128 7300.29% + 1 1385 1418.48% + 2 452 462.93% + 3 225 230.44% + 4 157 160.79% + 5 102 104.47% + 6 106 108.56% + 7 96 98.32% + 8 113 115.73% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 6314 # Number of instructions committed +system.cpu.commit.COM:loads 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 353 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4190 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses +system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6297 # Number of Instructions Simulated +system.cpu.committedInsts_total 6297 # Number of Instructions Simulated +system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses -system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses +system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1874 # number of overall hits -system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses -system.cpu.dcache.overall_misses 504 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2117 # number of overall hits +system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses +system.cpu.dcache.overall_misses 503 # number of overall misses +system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use +system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 163 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11516 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6794 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2076 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2663 # DTB accesses +system.cpu.dtb.accesses 2901 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2604 # DTB hits -system.cpu.dtb.misses 59 # DTB misses -system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.hits 2837 # DTB hits +system.cpu.dtb.misses 64 # DTB misses +system.cpu.dtb.read_accesses 1842 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1614 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses -system.cpu.dtb.write_accesses 1011 # DTB write accesses +system.cpu.dtb.read_hits 1799 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.write_accesses 1059 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 990 # DTB write hits +system.cpu.dtb.write_hits 1038 # DTB write hits system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2013 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1565 # Number of cache lines fetched -system.cpu.fetch.Cycles 3769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched +system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189780 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 844 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.174507 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10158 +system.cpu.fetch.rateDist.samples 10556 system.cpu.fetch.rateDist.min_value 0 - 0 7986 7861.78% - 1 184 181.14% - 2 171 168.34% - 3 148 145.70% - 4 221 217.56% - 5 166 163.42% - 6 188 185.08% - 7 106 104.35% - 8 988 972.63% + 0 8192 7760.52% + 1 236 223.57% + 2 214 202.73% + 3 172 162.94% + 4 242 229.25% + 5 149 141.15% + 6 203 192.31% + 7 118 111.78% + 8 1030 975.75% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.935484 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses +system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency +system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1220 # number of overall hits -system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses +system.cpu.icache.overall_hits 1325 # number of overall hits +system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 162.483905 # Cycle average of tags in use -system.cpu.icache.total_refs 1220 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use +system.cpu.icache.total_refs 1325 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 449 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1210 # Number of branches executed -system.cpu.iew.EXEC:nop 70 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.759310 # Inst execution rate -system.cpu.iew.EXEC:refs 2668 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1014 # Number of stores executed +system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1365 # Number of branches executed +system.cpu.iew.EXEC:nop 69 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate +system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1061 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5427 # num instructions consuming a value -system.cpu.iew.WB:count 7728 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.742583 # average fanout of values written-back +system.cpu.iew.WB:consumers 5886 # num instructions consuming a value +system.cpu.iew.WB:count 8407 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4030 # num instructions producing a value -system.cpu.iew.WB:rate 0.728575 # insts written-back per cycle -system.cpu.iew.WB:sent 7840 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 420 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 4386 # num instructions producing a value +system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle +system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1228 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9927 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8054 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 792 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1034 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 416 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.530122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.530122 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8404 # Type of FU issued +system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5587 66.48% # Type of FU issued + IntAlu 6020 66.28% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1774 21.11% # Type of FU issued - MemWrite 1038 12.35% # Type of FU issued + MemRead 1973 21.72% # Type of FU issued + MemWrite 1085 11.95% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012256 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.97% # attempts to use FU when none available + IntAlu 1 0.93% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,38 +309,38 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 68 66.02% # attempts to use FU when none available - MemWrite 34 33.01% # attempts to use FU when none available + MemRead 72 67.29% # attempts to use FU when none available + MemWrite 34 31.78% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10158 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10556 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6739 6634.18% - 1 1163 1144.91% - 2 838 824.97% - 3 636 626.11% - 4 450 443.00% - 5 195 191.97% - 6 92 90.57% - 7 30 29.53% - 8 15 14.77% + 0 6842 6481.62% + 1 1288 1220.16% + 2 888 841.23% + 3 723 684.92% + 4 456 431.98% + 5 198 187.57% + 6 106 100.42% + 7 40 37.89% + 8 15 14.21% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.792307 # Inst issue rate -system.cpu.iq.iqInstsAdded 9833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8404 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate +system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3830 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1597 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1700 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1565 # ITB hits -system.cpu.itb.misses 32 # ITB misses +system.cpu.itb.hits 1670 # ITB hits +system.cpu.itb.misses 30 # ITB misses system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency @@ -350,59 +350,59 @@ system.cpu.l2cache.ReadExReq_misses 72 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5733.415233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2733.415233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5433.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2433.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 81500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1336500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2773500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 479 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1336500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 215.878593 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 10607 # number of cpu cycles simulated +system.cpu.numCycles 11014 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 6962 # Number of cycles rename is idle +system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14001 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10976 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8169 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 792 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4118 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 79 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 05d3c33eb..2c5a26de6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:18:02 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:48:39 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5303000 because target called exit() +Exiting @ tick 5506500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index e68e8bc1c..5214649cb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index c89057e77..6f4810c44 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274181 # Simulator instruction rate (inst/s) -host_mem_usage 172576 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135418658 # Simulator tick rate (ticks/s) +host_inst_rate 74368 # Simulator instruction rate (inst/s) +host_mem_usage 201628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 37260110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated +sim_insts 6315 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2833500 # Number of ticks simulated -system.cpu.dtb.accesses 1801 # DTB accesses +sim_ticks 3170500 # Number of ticks simulated +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.accesses 6342 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.hits 6325 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5668 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 6342 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index ae7c0fe57..7e1e7de26 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 2833500 because target called exit() +Exiting @ tick 3170500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index bbb328185..43431aef9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index d791e0a2e..22e685732 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11324 # Simulator instruction rate (inst/s) -host_mem_usage 193960 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host -host_tick_rate 38693743 # Simulator tick rate (ticks/s) +host_inst_rate 65172 # Simulator instruction rate (inst/s) +host_mem_usage 209040 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 208535003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19285000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) +sim_insts 6315 # Number of instructions simulated +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20250000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.303030 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1612 # number of overall hits +system.cpu.dcache.overall_hits 1851 # number of overall hits system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses system.cpu.dcache.overall_misses 179 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,66 +76,66 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use -system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use +system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.673835 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency -system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses -system.cpu.icache.demand_misses 277 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency +system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5375 # number of overall hits -system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses -system.cpu.icache.overall_misses 277 # number of overall misses +system.cpu.icache.overall_hits 6047 # number of overall hits +system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses +system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -148,16 +148,16 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use -system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use +system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.accesses 6343 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.hits 6326 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 73 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -189,38 +189,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002809 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 441 # number of overall misses +system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -233,16 +233,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38570 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 40500 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index c8cf5ab9d..a4ec269db 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:04 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 19285000 because target called exit() +Exiting @ tick 20250000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index d13eeb4e2..a80c5cabd 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 9a9ac5a12..c2853cc3f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1230 # Simulator instruction rate (inst/s) -host_mem_usage 173824 # Number of bytes of host memory used -host_seconds 3.93 # Real time elapsed on the host -host_tick_rate 622698 # Simulator tick rate (ticks/s) +host_inst_rate 31798 # Simulator instruction rate (inst/s) +host_mem_usage 202884 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 16065810 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2447500 # Number of ticks simulated +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2701000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4896 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index b07b710c8..c0e107ab6 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:55 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 2447500 because target called exit() +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 092061e7f..834e9fbf3 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 08e810a08..132891c92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153074 # Simulator instruction rate (inst/s) -host_mem_usage 195092 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 524572616 # Simulator tick rate (ticks/s) +host_inst_rate 56962 # Simulator instruction rate (inst/s) +host_mem_usage 210220 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 184294275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated +sim_insts 5340 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16662000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) +sim_ticks 17315000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.400000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1119 # number of overall hits +system.cpu.dcache.overall_hits 1239 # number of overall hits system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use -system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency -system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses -system.cpu.icache.demand_misses 256 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4621 # number of overall hits -system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses -system.cpu.icache.overall_misses 256 # number of overall misses +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -136,10 +136,10 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use -system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -152,16 +152,16 @@ system.cpu.l2cache.ReadExReq_misses 81 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -173,38 +173,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4268000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 388 # number of overall misses +system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4268000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -217,16 +217,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 33324 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 4d51e2838..9fab97574 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:08 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:56 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 16662000 because target called exit() +Hello World!Exiting @ tick 17315000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 569d4b220..40d1ca238 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index 5fd208e3f..ef5ccc7e6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 13744 # Simulator instruction rate (inst/s) -host_mem_usage 186320 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -host_tick_rate 7996070 # Simulator tick rate (ticks/s) +host_inst_rate 69477 # Simulator instruction rate (inst/s) +host_mem_usage 201612 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 40336760 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 8475 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4932000 # Number of ticks simulated +sim_insts 9511 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5529000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9865 # number of cpu cycles simulated -system.cpu.num_insts 8475 # Number of instructions executed -system.cpu.num_refs 1765 # Number of memory references +system.cpu.numCycles 11059 # number of cpu cycles simulated +system.cpu.num_insts 9511 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 99e187690..ada9a56fb 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:50:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:14:28 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 4932000 because target called exit() +Exiting @ tick 5529000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index ca040dc25..fc5cea346 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -386,6 +387,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 4a5d707e1..28f9f7577 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 722 # Number of BTB hits -global.BPredUnit.BTBLookups 3569 # Number of BTB lookups -global.BPredUnit.RASInCorrect 133 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1125 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2392 # Number of conditional branches predicted -global.BPredUnit.lookups 4127 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 41846 # Simulator instruction rate (inst/s) -host_mem_usage 152588 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 23650670 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 33 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 36 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1975 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2036 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1163 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1158 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 817 # Number of BTB hits +global.BPredUnit.BTBLookups 4239 # Number of BTB lookups +global.BPredUnit.RASInCorrect 150 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2870 # Number of conditional branches predicted +global.BPredUnit.lookups 4960 # Number of BP lookups +global.BPredUnit.usedRAS 590 # Number of times the RAS was used to get a target. +host_inst_rate 59476 # Simulator instruction rate (inst/s) +host_mem_usage 210328 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 33433367 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 46 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2257 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2354 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1267 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1298 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 6363000 # Number of ticks simulated -system.cpu.commit.COM:branches 1724 # Number of branches committed -system.cpu.commit.COM:branches_0 862 # Number of branches committed -system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 145 # number cycles where commit BW limit reached +sim_insts 12595 # Number of instructions simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7085500 # Number of ticks simulated +system.cpu.commit.COM:branches 2024 # Number of branches committed +system.cpu.commit.COM:branches_0 1012 # Number of branches committed +system.cpu.commit.COM:branches_1 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 152 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12623 +system.cpu.commit.COM:committed_per_cycle.samples 14074 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7897 6256.04% - 1 2220 1758.69% - 2 993 786.66% - 3 507 401.65% - 4 332 263.01% - 5 219 173.49% - 6 199 157.65% - 7 111 87.93% - 8 145 114.87% + 0 8763 6226.37% + 1 2528 1796.22% + 2 1133 805.03% + 3 504 358.11% + 4 369 262.19% + 5 263 186.87% + 6 218 154.90% + 7 144 102.32% + 8 152 108.00% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5640 # Number of instructions committed -system.cpu.commit.COM:count_1 5641 # Number of instructions committed -system.cpu.commit.COM:loads 1958 # Number of loads committed -system.cpu.commit.COM:loads_0 979 # Number of loads committed -system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:count 12629 # Number of instructions committed +system.cpu.commit.COM:count_0 6314 # Number of instructions committed +system.cpu.commit.COM:count_1 6315 # Number of instructions committed +system.cpu.commit.COM:loads 2336 # Number of loads committed +system.cpu.commit.COM:loads_0 1168 # Number of loads committed +system.cpu.commit.COM:loads_1 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3582 # Number of memory references committed -system.cpu.commit.COM:refs_0 1791 # Number of memory references committed -system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:refs 4060 # Number of memory references committed +system.cpu.commit.COM:refs_0 2030 # Number of memory references committed +system.cpu.commit.COM:refs_1 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 885 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.branchMispredicts 1036 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8502 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5623 # Number of Instructions Simulated -system.cpu.committedInsts_1 5624 # Number of Instructions Simulated -system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 2.263383 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.262980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.131591 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.093212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.063982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 9139.837398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8686.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.378695 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 9674 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6297 # Number of Instructions Simulated +system.cpu.committedInsts_1 6298 # Number of Instructions Simulated +system.cpu.committedInsts_total 12595 # Number of Instructions Simulated +system.cpu.cpi_0 2.250596 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.250238 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.125208 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12250.889680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10641.025641 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.076546 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.053119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 195 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 9093.800979 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8701.149425 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.355568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.266082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.379412 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4703 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5395 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4501 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4501 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9098500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 9017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 9017000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.165709 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 894 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 525 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3585500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3589000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 3589000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.068397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 369 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5395 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3801 # number of overall hits -system.cpu.dcache.overall_hits_0 3801 # number of overall hits +system.cpu.dcache.overall_hits 4501 # number of overall hits +system.cpu.dcache.overall_hits_0 4501 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9098500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 9017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 9017000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.165709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 902 # number of overall misses -system.cpu.dcache.overall_misses_0 902 # number of overall misses +system.cpu.dcache.overall_misses 894 # number of overall misses +system.cpu.dcache.overall_misses_0 894 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 525 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3585500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3589000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 3589000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.068397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 369 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in use -system.cpu.dcache.total_refs 3853 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.357154 # Cycle average of tags in use +system.cpu.dcache.total_refs 4549 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2156 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 253 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 362 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22792 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 17306 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3860 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1667 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 387 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 2189 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 393 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 537 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 25750 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 19285 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4519 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1860 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 5201 # DTB accesses +system.cpu.dtb.accesses 5942 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5076 # DTB hits +system.cpu.dtb.hits 5817 # DTB hits system.cpu.dtb.misses 125 # DTB misses -system.cpu.dtb.read_accesses 3261 # DTB read accesses +system.cpu.dtb.read_accesses 3857 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3178 # DTB read hits -system.cpu.dtb.read_misses 83 # DTB read misses -system.cpu.dtb.write_accesses 1940 # DTB write accesses +system.cpu.dtb.read_hits 3775 # DTB read hits +system.cpu.dtb.read_misses 82 # DTB read misses +system.cpu.dtb.write_accesses 2085 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1898 # DTB write hits -system.cpu.dtb.write_misses 42 # DTB write misses -system.cpu.fetch.Branches 4127 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3105 # Number of cache lines fetched -system.cpu.fetch.Cycles 7305 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 481 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25026 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.324271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1272 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.966371 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 2042 # DTB write hits +system.cpu.dtb.write_misses 43 # DTB write misses +system.cpu.fetch.Branches 4960 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3670 # Number of cache lines fetched +system.cpu.fetch.Cycles 8581 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 538 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 28943 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1537 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.349986 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1407 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.042266 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 12676 +system.cpu.fetch.rateDist.samples 14126 system.cpu.fetch.rateDist.min_value 0 - 0 8531 6730.04% - 1 309 243.77% - 2 245 193.28% - 3 260 205.11% - 4 342 269.80% - 5 308 242.98% - 6 324 255.60% - 7 261 205.90% - 8 2096 1653.52% + 0 9265 6558.83% + 1 397 281.04% + 2 297 210.25% + 3 373 264.05% + 4 393 278.21% + 5 288 203.88% + 6 408 288.83% + 7 267 189.01% + 8 2438 1725.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7742.694805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.226731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 10197.443182 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7726.171244 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.191826 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.198390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 616 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 616 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.168665 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.897727 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.791599 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3105 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3105 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3670 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2401 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2401 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2966 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2966 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7161000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 7179000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 7179000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.226731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.191826 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.icache.demand_misses 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 85 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 85 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 4782500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.198390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.168665 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 616 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 616 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3105 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3105 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3670 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2401 # number of overall hits -system.cpu.icache.overall_hits_0 2401 # number of overall hits +system.cpu.icache.overall_hits 2966 # number of overall hits +system.cpu.icache.overall_hits_0 2966 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7161000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 7179000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 7179000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.226731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.191826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses system.cpu.icache.overall_misses 704 # number of overall misses system.cpu.icache.overall_misses_0 704 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 85 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 85 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4769500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4769500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4782500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 4782500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.198390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.168665 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 616 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 616 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.replacements_0 7 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 616 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 313.697202 # Cycle average of tags in use -system.cpu.icache.total_refs 2401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 335.078862 # Cycle average of tags in use +system.cpu.icache.total_refs 2966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 51 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2444 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1228 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1216 # Number of branches executed -system.cpu.iew.EXEC:nop 128 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 67 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate -system.cpu.iew.EXEC:refs 5219 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2580 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2639 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1956 # Number of stores executed -system.cpu.iew.EXEC:stores_0 977 # Number of stores executed -system.cpu.iew.EXEC:stores_1 979 # Number of stores executed +system.cpu.idleCycles 46 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2896 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1452 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1444 # Number of branches executed +system.cpu.iew.EXEC:nop 125 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 59 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.282811 # Inst execution rate +system.cpu.iew.EXEC:refs 5961 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2937 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3024 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2102 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1047 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1055 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10432 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5228 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5204 # num instructions consuming a value -system.cpu.iew.WB:count 15495 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7763 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7732 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.540838 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.769893 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.770945 # average fanout of values written-back +system.cpu.iew.WB:consumers 11655 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5835 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5820 # num instructions consuming a value +system.cpu.iew.WB:count 17454 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8729 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8725 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.541828 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.770865 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.770962 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8037 # num instructions producing a value -system.cpu.iew.WB:producers_0 4025 # num instructions producing a value -system.cpu.iew.WB:producers_1 4012 # num instructions producing a value -system.cpu.iew.WB:rate 1.217490 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.609963 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.607527 # insts written-back per cycle -system.cpu.iew.WB:sent 15706 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7855 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7851 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1023 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 34 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4011 # Number of dispatched load instructions +system.cpu.iew.WB:producers 8985 # num instructions producing a value +system.cpu.iew.WB:producers_0 4498 # num instructions producing a value +system.cpu.iew.WB:producers_1 4487 # num instructions producing a value +system.cpu.iew.WB:rate 1.231583 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.615933 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.615651 # insts written-back per cycle +system.cpu.iew.WB:sent 17676 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 8819 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 8857 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4611 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2321 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19928 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3263 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1603 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1660 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 892 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16126 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 648 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2565 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22432 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3859 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1890 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1127 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18180 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 18 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1667 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1860 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 996 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1089 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 405 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 53 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 70 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1057 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 346 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 133 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 810 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.441817 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.441895 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.883712 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8497 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1186 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 436 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 137 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.444327 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.444397 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.888724 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9630 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5747 67.64% # Type of FU issued + IntAlu 6491 67.40% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1738 20.45% # Type of FU issued - MemWrite 1007 11.85% # Type of FU issued + MemRead 2024 21.02% # Type of FU issued + MemWrite 1110 11.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8521 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 9677 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5702 66.92% # Type of FU issued + IntAlu 6446 66.61% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1797 21.09% # Type of FU issued - MemWrite 1017 11.94% # Type of FU issued + MemRead 2105 21.75% # Type of FU issued + MemWrite 1121 11.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17018 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 19307 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11449 67.28% # Type of FU issued + IntAlu 12937 67.01% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3535 20.77% # Type of FU issued - MemWrite 2024 11.89% # Type of FU issued + MemRead 4129 21.39% # Type of FU issued + MemWrite 2231 11.56% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 83 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010577 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004877 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005700 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 191 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009893 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004558 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005335 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 9 5.00% # attempts to use FU when none available + IntAlu 10 5.24% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,107 +543,107 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 107 59.44% # attempts to use FU when none available - MemWrite 64 35.56% # attempts to use FU when none available + MemRead 116 60.73% # attempts to use FU when none available + MemWrite 65 34.03% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 12676 +system.cpu.iq.ISSUE:issued_per_cycle.samples 14126 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6060 4780.69% - 1 2068 1631.43% - 2 1684 1328.49% - 3 1173 925.37% - 4 835 658.73% - 5 514 405.49% - 6 255 201.17% - 7 73 57.59% - 8 14 11.04% + 0 6647 4705.51% + 1 2379 1684.13% + 2 1804 1277.08% + 3 1327 939.40% + 4 983 695.88% + 5 624 441.74% + 6 265 187.60% + 7 79 55.93% + 8 18 12.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.337157 # Inst issue rate -system.cpu.iq.iqInstsAdded 19755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17018 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.362334 # Inst issue rate +system.cpu.iq.iqInstsAdded 22262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19307 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8627 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4636 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3160 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 5151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3720 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3105 # ITB hits -system.cpu.itb.misses 55 # ITB misses +system.cpu.itb.hits 3670 # ITB hits +system.cpu.itb.misses 50 # ITB misses system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6844.827586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3844.827586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 992500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6824.137931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3824.137931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 989500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 989500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 557500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 557500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 554500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 554500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6525.277435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3525.277435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997540 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 6515.413070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3515.413070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.996314 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997540 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996314 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6103.448276 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3103.448276 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 177000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 177000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6344.827586 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3344.827586 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 184000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 184000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 90000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 90000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 97000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003836 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 958 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 959 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6273500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 6273500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.996872 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses @@ -651,11 +651,11 @@ system.cpu.l2cache.demand_misses_1 0 # nu system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3416500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3416500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3405500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 3405500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.996872 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses @@ -665,26 +665,26 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 958 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 959 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 959 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6273500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 6273500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.996872 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 956 # number of overall misses system.cpu.l2cache.overall_misses_0 956 # number of overall misses @@ -692,11 +692,11 @@ system.cpu.l2cache.overall_misses_1 0 # nu system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3416500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3416500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3405500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 3405500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.996872 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses @@ -723,29 +723,30 @@ system.cpu.l2cache.sampled_refs 782 # Sa system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 419.781607 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 444.416250 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 12727 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 743 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 17661 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 854 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 27553 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21741 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 16306 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3686 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1667 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 906 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8204 # Number of HB maps that are undone due to squashing +system.cpu.numCycles 14172 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 760 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 19739 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 868 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 30813 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 24390 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18197 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4242 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1860 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 926 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2524 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 15 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 1b77a8f81..1c27475d4 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:49:40 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 6363000 because target called exit() +Exiting @ tick 7085500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index e981744fd..13cb0931f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 29c5e75be..d4ce934cb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2713 # Number of BTB hits -global.BPredUnit.BTBLookups 6851 # Number of BTB lookups +global.BPredUnit.BTBHits 4364 # Number of BTB hits +global.BPredUnit.BTBLookups 10024 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2011 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7546 # Number of conditional branches predicted -global.BPredUnit.lookups 7546 # Number of BP lookups +global.BPredUnit.condIncorrect 2911 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 11601 # Number of conditional branches predicted +global.BPredUnit.lookups 11601 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 33487 # Simulator instruction rate (inst/s) -host_mem_usage 153160 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 49468437 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. +host_inst_rate 6832 # Simulator instruction rate (inst/s) +host_mem_usage 210732 # Number of bytes of host memory used +host_seconds 2.11 # Real time elapsed on the host +host_tick_rate 10370738 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2926 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4977 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3503 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10411 # Number of instructions simulated -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15392500 # Number of ticks simulated -system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 88 # number cycles where commit BW limit reached +sim_insts 14449 # Number of instructions simulated +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21933500 # Number of ticks simulated +system.cpu.commit.COM:branches 3359 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 27698 +system.cpu.commit.COM:committed_per_cycle.samples 39346 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22133 7990.83% - 1 3105 1121.02% - 2 1159 418.44% - 3 591 213.37% - 4 306 110.48% - 5 82 29.61% - 6 196 70.76% - 7 38 13.72% - 8 88 31.77% + 0 31195 7928.38% + 1 4789 1217.15% + 2 1729 439.43% + 3 717 182.23% + 4 416 105.73% + 5 147 37.36% + 6 198 50.32% + 7 50 12.71% + 8 105 26.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 10976 # Number of instructions committed -system.cpu.commit.COM:loads 1462 # Number of loads committed +system.cpu.commit.COM:count 15175 # Number of instructions committed +system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2760 # Number of memory references committed +system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2011 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13116 # The number of squashed insts skipped by commit -system.cpu.committedInsts 10411 # Number of Instructions Simulated -system.cpu.committedInsts_total 10411 # Number of Instructions Simulated -system.cpu.cpi 2.957065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.957065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9364.130435 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7068.181818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2205 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 861500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.040052 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 466500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.028733 # mshr miss rate for ReadReq accesses +system.cpu.commit.branchMispredicts 2911 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 20100 # The number of squashed insts skipped by commit +system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedInsts_total 14449 # Number of Instructions Simulated +system.cpu.cpi 3.036058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.036058 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9408.602151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7113.636364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3751 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 875000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.024194 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.017170 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9880.434783 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6966.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1062 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2272500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.178019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 230 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 125 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 731500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 9957.589286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1218 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2230500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.155340 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 224 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 714000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.736842 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 33.590604 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3589 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3267 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.089719 # miss rate for demand accesses -system.cpu.dcache.demand_misses 322 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 151 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1198000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047646 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9796.529968 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4969 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3105500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.059970 # miss rate for demand accesses +system.cpu.dcache.demand_misses 317 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 149 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1183500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031782 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3589 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9796.529968 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3267 # number of overall hits -system.cpu.dcache.overall_miss_latency 3134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.089719 # miss rate for overall accesses -system.cpu.dcache.overall_misses 322 # number of overall misses -system.cpu.dcache.overall_mshr_hits 151 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1198000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047646 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 4969 # number of overall hits +system.cpu.dcache.overall_miss_latency 3105500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.059970 # miss rate for overall accesses +system.cpu.dcache.overall_misses 317 # number of overall misses +system.cpu.dcache.overall_mshr_hits 149 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1183500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031782 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.780967 # Cycle average of tags in use -system.cpu.dcache.total_refs 3304 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 114.768529 # Cycle average of tags in use +system.cpu.dcache.total_refs 5005 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4065 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 37568 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13467 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 10101 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2901 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7546 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4905 # Number of cache lines fetched -system.cpu.fetch.Cycles 16129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 41611 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2098 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.245111 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4905 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2713 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.351621 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 5414 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 52959 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 18733 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 15067 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4338 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11601 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7392 # Number of cache lines fetched +system.cpu.fetch.Cycles 24155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 764 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 59501 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.264452 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7392 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4364 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.356365 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30599 +system.cpu.fetch.rateDist.samples 43684 system.cpu.fetch.rateDist.min_value 0 - 0 19398 6339.42% - 1 4890 1598.09% - 2 619 202.29% - 3 711 232.36% - 4 788 257.52% - 5 642 209.81% - 6 612 200.01% - 7 196 64.05% - 8 2743 896.43% + 0 26944 6167.93% + 1 7490 1714.59% + 2 1209 276.76% + 3 1044 238.99% + 4 1055 241.51% + 5 1191 272.64% + 6 698 159.78% + 7 326 74.63% + 8 3727 853.17% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 4905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8897.590361 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6462.162162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4490 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3692500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.084608 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 415 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.075433 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 7392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8917.690418 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6472.527473 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6985 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3629500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.055060 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.049242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 364 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.135135 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.189560 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4905 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency -system.cpu.icache.demand_hits 4490 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3692500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.084608 # miss rate for demand accesses -system.cpu.icache.demand_misses 415 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.075433 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 7392 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8917.690418 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency +system.cpu.icache.demand_hits 6985 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3629500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.055060 # miss rate for demand accesses +system.cpu.icache.demand_misses 407 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.049242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 364 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4905 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency +system.cpu.icache.overall_accesses 7392 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8917.690418 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4490 # number of overall hits -system.cpu.icache.overall_miss_latency 3692500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.084608 # miss rate for overall accesses -system.cpu.icache.overall_misses 415 # number of overall misses -system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.075433 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses +system.cpu.icache.overall_hits 6985 # number of overall hits +system.cpu.icache.overall_miss_latency 3629500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.055060 # miss rate for overall accesses +system.cpu.icache.overall_misses 407 # number of overall misses +system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.049242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 230.770092 # Cycle average of tags in use -system.cpu.icache.total_refs 4490 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 247.187481 # Cycle average of tags in use +system.cpu.icache.total_refs 6985 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3077 # Number of branches executed -system.cpu.iew.EXEC:nop 1794 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.558825 # Inst execution rate -system.cpu.iew.EXEC:refs 4529 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2104 # Number of stores executed +system.cpu.idleCycles 184 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4855 # Number of branches executed +system.cpu.iew.EXEC:nop 2093 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.570211 # Inst execution rate +system.cpu.iew.EXEC:refs 6456 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2482 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9158 # num instructions consuming a value -system.cpu.iew.WB:count 16580 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.828347 # average fanout of values written-back +system.cpu.iew.WB:consumers 13185 # num instructions consuming a value +system.cpu.iew.WB:count 24031 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.826773 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7586 # num instructions producing a value -system.cpu.iew.WB:rate 0.538556 # insts written-back per cycle -system.cpu.iew.WB:sent 16781 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2212 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 10901 # num instructions producing a value +system.cpu.iew.WB:rate 0.547802 # insts written-back per cycle +system.cpu.iew.WB:sent 24254 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3206 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2926 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24197 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2425 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2802 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17204 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 4977 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 772 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3503 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 35402 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 25014 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2901 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4338 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 58 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1596 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1628 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1523 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.338173 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.338173 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 20006 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 2751 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2055 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 58 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 769 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2437 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.329374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.329374 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 29431 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 14491 72.43% # Type of FU issued + IntAlu 21547 73.21% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2890 14.45% # Type of FU issued - MemWrite 2625 13.12% # Type of FU issued + MemRead 4739 16.10% # Type of FU issued + MemWrite 3145 10.69% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009347 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006388 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 51 27.27% # attempts to use FU when none available + IntAlu 49 26.06% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,96 +296,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 24 12.83% # attempts to use FU when none available - MemWrite 112 59.89% # attempts to use FU when none available + MemRead 25 13.30% # attempts to use FU when none available + MemWrite 114 60.64% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30599 +system.cpu.iq.ISSUE:issued_per_cycle.samples 43684 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 21747 7107.10% - 1 3624 1184.35% - 2 2137 698.39% - 3 1557 508.84% - 4 751 245.43% - 5 397 129.74% - 6 290 94.77% - 7 60 19.61% - 8 36 11.77% + 0 30754 7040.11% + 1 5431 1243.25% + 2 3052 698.65% + 3 2131 487.82% + 4 1026 234.87% + 5 660 151.09% + 6 361 82.64% + 7 219 50.13% + 8 50 11.45% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.649841 # Inst issue rate -system.cpu.iq.iqInstsAdded 21791 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20006 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 10183 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 8044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5755.813953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2755.813953 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 495000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.670899 # Inst issue rate +system.cpu.iq.iqInstsAdded 32537 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29431 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 772 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 16058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 297 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12535 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 5795.180723 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2795.180723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 481000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 237000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 232000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5417.824074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2417.824074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 430 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5433.098592 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2433.098592 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2340500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2314500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990698 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1036500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990698 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5631.578947 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2631.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 107000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5578.947368 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2578.947368 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 49000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009828 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5492.141454 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992203 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 509 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1281500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 509 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5492.141454 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 518 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2795500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992203 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 509 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1281500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1268500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992203 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,27 +398,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 257.005987 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 273.898723 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30786 # number of cpu cycles simulated -system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 14813 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 51330 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29671 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 24234 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8843 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2901 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14366 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 3812 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 646 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4446 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 683 # count of temporary serializing insts renamed +system.cpu.numCycles 43868 # number of cpu cycles simulated +system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 20565 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 76206 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 43436 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 36362 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13390 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4338 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 306 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 22530 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5085 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 899 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5188 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 833 # count of temporary serializing insts renamed system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index e6fab5604..502cab72d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:19 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:53 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 15392500 because target called exit() +Exiting @ tick 21933500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index ba8f324ab..fe774ce88 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index da5a7c7d1..8d9b3b609 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2595 # Simulator instruction rate (inst/s) -host_mem_usage 173616 # Number of bytes of host memory used -host_seconds 4.23 # Real time elapsed on the host -host_tick_rate 1303618 # Simulator tick rate (ticks/s) +host_inst_rate 15225 # Simulator instruction rate (inst/s) +host_mem_usage 202592 # Number of bytes of host memory used +host_seconds 1.00 # Real time elapsed on the host +host_tick_rate 7641899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5514000 # Number of ticks simulated +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11029 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 6632a0f07..91b36f948 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:02:07 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 5514000 because target called exit() +Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index fa313ad0d..d0972f695 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 882e0c177..27bd0c98d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23807 # Simulator instruction rate (inst/s) -host_mem_usage 194964 # Number of bytes of host memory used -host_seconds 0.46 # Real time elapsed on the host -host_tick_rate 54716973 # Simulator tick rate (ticks/s) +host_inst_rate 26211 # Simulator instruction rate (inst/s) +host_mem_usage 210104 # Number of bytes of host memory used +host_seconds 0.58 # Real time elapsed on the host +host_tick_rate 52105150 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25237000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30178000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1431000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2835000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2754000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2448000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4293000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses -system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4185000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses +system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 3720000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2595 # number of overall hits -system.cpu.dcache.overall_miss_latency 4293000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses -system.cpu.dcache.overall_misses 159 # number of overall misses +system.cpu.dcache.overall_hits 3513 # number of overall hits +system.cpu.dcache.overall_miss_latency 4185000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses +system.cpu.dcache.overall_misses 155 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 3720000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -76,56 +76,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 99.913779 # Cycle average of tags in use -system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.837167 # Cycle average of tags in use +system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26908.127208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7615000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6766000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26907.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6694000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency -system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7615000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses -system.cpu.icache.demand_misses 283 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26907.142857 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency +system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_misses 280 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6766000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6694000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency +system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26907.142857 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10729 # number of overall hits -system.cpu.icache.overall_miss_latency 7615000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses -system.cpu.icache.overall_misses 283 # number of overall misses +system.cpu.icache.overall_hits 14941 # number of overall hits +system.cpu.icache.overall_miss_latency 7534000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_misses 280 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6766000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6694000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -138,32 +138,32 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 154.924957 # Cycle average of tags in use -system.cpu.icache.total_refs 10729 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.376172 # Cycle average of tags in use +system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2024000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 935000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 7613000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3641000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -175,38 +175,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9729000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4576000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9729000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 423 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 416 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4576000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -219,16 +219,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 176.975795 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 187.735043 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 50474 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.numCycles 60356 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index e7f5d2afa..2511a0e62 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:19 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:03:20 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25237000 because target called exit() +Exiting @ tick 30178000 because target called exit() -- cgit v1.2.3 From 62c08a75ad18fda5d06d919db6d8d31a79be9630 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 3 Aug 2008 18:13:29 -0400 Subject: Make default PhysicalMemory latency slightly more realistic. Also update stats to reflect change. --- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 597 ++++++------ .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 +- .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 118 +-- .../00.gzip/ref/alpha/tru64/simple-timing/stderr | 2 +- .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 8 +- .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 2 +- .../00.gzip/ref/sparc/linux/o3-timing/m5stats.txt | 579 +++++------ .../long/00.gzip/ref/sparc/linux/o3-timing/stderr | 2 +- .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 126 +-- .../00.gzip/ref/sparc/linux/simple-timing/stderr | 2 +- .../00.gzip/ref/sparc/linux/simple-timing/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 126 +-- .../10.mcf/ref/sparc/linux/simple-timing/stderr | 2 +- .../10.mcf/ref/sparc/linux/simple-timing/stdout | 12 +- .../30.eon/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../30.eon/ref/alpha/tru64/o3-timing/m5stats.txt | 603 ++++++------ tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 116 +-- .../30.eon/ref/alpha/tru64/simple-timing/stderr | 2 +- .../30.eon/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 118 +-- .../ref/alpha/tru64/simple-timing/stderr | 2 +- .../ref/alpha/tru64/simple-timing/stdout | 8 +- .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 627 ++++++------ .../50.vortex/ref/alpha/tru64/o3-timing/stderr | 2 +- .../50.vortex/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 118 +-- .../50.vortex/ref/alpha/tru64/simple-timing/stderr | 2 +- .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 3 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 128 +-- .../50.vortex/ref/sparc/linux/simple-timing/stderr | 2 +- .../50.vortex/ref/sparc/linux/simple-timing/stdout | 10 +- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt | 608 ++++++------ .../long/60.bzip2/ref/alpha/tru64/o3-timing/stderr | 2 +- .../long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 120 +-- .../60.bzip2/ref/alpha/tru64/simple-timing/stderr | 2 +- .../60.bzip2/ref/alpha/tru64/simple-timing/stdout | 8 +- .../70.twolf/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt | 602 ++++++------ .../long/70.twolf/ref/alpha/tru64/o3-timing/stderr | 2 +- .../long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 116 +-- .../70.twolf/ref/alpha/tru64/simple-timing/stderr | 2 +- .../70.twolf/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 124 +-- .../70.twolf/ref/sparc/linux/simple-timing/stderr | 2 +- .../70.twolf/ref/sparc/linux/simple-timing/stdout | 12 +- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 2 +- .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 553 +++++------ .../00.hello/ref/alpha/linux/o3-timing/stderr | 2 +- .../00.hello/ref/alpha/linux/o3-timing/stdout | 12 +- .../ref/alpha/linux/simple-timing/config.ini | 2 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 116 +-- .../00.hello/ref/alpha/linux/simple-timing/stderr | 2 +- .../00.hello/ref/alpha/linux/simple-timing/stdout | 12 +- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 3 +- .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 492 +++++----- .../00.hello/ref/alpha/tru64/o3-timing/stderr | 2 +- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 10 +- .../ref/alpha/tru64/simple-timing/config.ini | 3 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 114 +-- .../00.hello/ref/alpha/tru64/simple-timing/stderr | 2 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 10 +- .../ref/mips/linux/simple-timing/config.ini | 3 +- .../ref/mips/linux/simple-timing/m5stats.txt | 116 +-- .../00.hello/ref/mips/linux/simple-timing/stderr | 2 +- .../00.hello/ref/mips/linux/simple-timing/stdout | 10 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 116 +-- .../00.hello/ref/sparc/linux/simple-timing/stderr | 2 +- .../00.hello/ref/sparc/linux/simple-timing/stdout | 12 +- .../ref/alpha/linux/o3-timing/config.ini | 2 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 816 ++++++++-------- .../ref/alpha/linux/o3-timing/stderr | 4 +- .../ref/alpha/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/o3-timing/config.ini | 2 +- .../ref/sparc/linux/o3-timing/m5stats.txt | 499 +++++----- .../02.insttest/ref/sparc/linux/o3-timing/stderr | 2 +- .../02.insttest/ref/sparc/linux/o3-timing/stdout | 12 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 116 +-- .../ref/sparc/linux/simple-timing/stderr | 2 +- .../ref/sparc/linux/simple-timing/stdout | 12 +- .../linux/tsunami-simple-atomic-dual/config.ini | 2 +- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 248 ++--- .../alpha/linux/tsunami-simple-atomic-dual/stderr | 6 +- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 10 +- .../alpha/linux/tsunami-simple-atomic/config.ini | 2 +- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 194 ++-- .../ref/alpha/linux/tsunami-simple-atomic/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 10 +- .../linux/tsunami-simple-timing-dual/config.ini | 2 +- .../linux/tsunami-simple-timing-dual/m5stats.txt | 822 ++++++++-------- .../alpha/linux/tsunami-simple-timing-dual/stderr | 8 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 10 +- .../tsunami-simple-timing-dual/system.terminal | 1 + .../alpha/linux/tsunami-simple-timing/config.ini | 2 +- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 488 +++++----- .../ref/alpha/linux/tsunami-simple-timing/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 10 +- .../linux/tsunami-simple-timing/system.terminal | 1 + .../ref/alpha/eio/simple-timing/config.ini | 3 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 116 +-- .../ref/alpha/eio/simple-timing/stderr | 2 +- .../ref/alpha/eio/simple-timing/stdout | 10 +- .../50.memtest/ref/alpha/linux/memtest/config.ini | 4 +- .../50.memtest/ref/alpha/linux/memtest/m5stats.txt | 1002 ++++++++++---------- .../50.memtest/ref/alpha/linux/memtest/stderr | 146 +-- .../50.memtest/ref/alpha/linux/memtest/stdout | 10 +- .../linux/twosys-tsunami-simple-atomic/config.ini | 8 +- .../linux/twosys-tsunami-simple-atomic/m5stats.txt | 92 +- .../linux/twosys-tsunami-simple-atomic/stderr | 10 +- .../linux/twosys-tsunami-simple-atomic/stdout | 10 +- 130 files changed, 5697 insertions(+), 5669 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 737f0dea4..2cac9c854 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index ca33458cb..c09103f51 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65739146 # Number of BTB hits -global.BPredUnit.BTBLookups 73253175 # Number of BTB lookups -global.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4205990 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted -global.BPredUnit.lookups 76112488 # Number of BP lookups -global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target. -host_inst_rate 131337 # Simulator instruction rate (inst/s) -host_mem_usage 179084 # Number of bytes of host memory used -host_seconds 4306.11 # Real time elapsed on the host -host_tick_rate 38417331 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43192001 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65718863 # Number of BTB hits +global.BPredUnit.BTBLookups 73181378 # Number of BTB lookups +global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted +global.BPredUnit.lookups 76039028 # Number of BP lookups +global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. +host_inst_rate 225803 # Simulator instruction rate (inst/s) +host_mem_usage 201396 # Number of bytes of host memory used +host_seconds 2504.62 # Real time elapsed on the host +host_tick_rate 66707870 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.165429 # Number of seconds simulated -sim_ticks 165429421500 # Number of ticks simulated +sim_seconds 0.167078 # Number of seconds simulated +sim_ticks 167078186500 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20148945 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 320950455 +system.cpu.commit.COM:committed_per_cycle.samples 322711309 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 102049912 3179.62% - 1 106118520 3306.38% - 2 36548740 1138.77% - 3 11550344 359.88% - 4 9951958 310.08% - 5 22152324 690.21% - 6 10779065 335.85% - 7 1650647 51.43% - 8 20148945 627.79% + 0 108088817 3349.40% + 1 100475751 3113.49% + 2 37367184 1157.91% + 3 9733028 301.60% + 4 10676883 330.85% + 5 22147835 686.30% + 6 13251874 410.64% + 7 3269687 101.32% + 8 17700250 548.49% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4205367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61707712 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61418223 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.585019 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads +system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 115038352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6257.587595 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008111 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 933102 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 113146791 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.218520 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.236909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293702 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853089 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636812 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688309500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7448.640662 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.056001 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2209327 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 321.245700 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.179200 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154489673 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7094.973483 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency -system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020341 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3142429 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003583 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 152598112 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.568696 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415338 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177518881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3182774 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629219 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708104495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154489673 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7094.973483 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 152598112 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.568696 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 151347244 # number of overall hits -system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020341 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3142429 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003583 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149415338 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177518881 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3182774 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629219 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708104495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,102 +120,102 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468826 # number of replacements -system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 468828 # number of replacements +system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use -system.cpu.dcache.total_refs 151924159 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334126 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 645 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4161088 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 690019158 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 145191324 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123829448 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9907520 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1984 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5507398 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163087430 # DTB accesses +system.cpu.dcache.tagsinuse 4094.202443 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001656 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126621000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334123 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 49202535 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689696251 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199512 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896072 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869869 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 163077395 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163038163 # DTB hits -system.cpu.dtb.misses 49267 # DTB misses -system.cpu.dtb.read_accesses 122338189 # DTB read accesses +system.cpu.dtb.hits 163013885 # DTB hits +system.cpu.dtb.misses 63510 # DTB misses +system.cpu.dtb.read_accesses 122284114 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122317544 # DTB read hits -system.cpu.dtb.read_misses 20645 # DTB read misses -system.cpu.dtb.write_accesses 40749241 # DTB write accesses +system.cpu.dtb.read_hits 122260501 # DTB read hits +system.cpu.dtb.read_misses 23613 # DTB read misses +system.cpu.dtb.write_accesses 40793281 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40720619 # DTB write hits -system.cpu.dtb.write_misses 28622 # DTB write misses -system.cpu.fetch.Branches 76112488 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66025670 # Number of cache lines fetched -system.cpu.fetch.Cycles 197184214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1351502 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 699221634 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4235220 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230045 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66025670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67431719 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.113353 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 40753384 # DTB write hits +system.cpu.dtb.write_misses 39897 # DTB write misses +system.cpu.fetch.Branches 76039028 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014416 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 698864070 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 66014416 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411082 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091428 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 330857976 +system.cpu.fetch.rateDist.samples 332581179 system.cpu.fetch.rateDist.min_value 0 - 0 199699470 6035.81% - 1 10371896 313.48% - 2 15863038 479.45% - 3 14602598 441.36% - 4 12358229 373.52% - 5 14818818 447.89% - 6 6010699 181.67% - 7 3341156 100.98% - 8 53792072 1625.84% + 0 201466276 6057.66% + 1 10360751 311.53% + 2 15882086 477.54% + 3 14599006 438.96% + 4 12362950 371.73% + 5 14822133 445.67% + 6 6008311 180.66% + 7 3307530 99.45% + 8 53772136 1616.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66025670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9355.263158 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1026 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 66014416 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36203.165098 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35497.228381 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013247 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32018500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73198.053215 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73185.417960 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66025670 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9355.263158 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency -system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_misses 1026 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 66014416 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36203.165098 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013247 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32018500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66025670 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9355.263158 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency +system.cpu.icache.overall_accesses 66014416 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36203.165098 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66024644 # number of overall hits -system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_misses 1026 # number of overall misses -system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 66013247 # number of overall hits +system.cpu.icache.overall_miss_latency 42321500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 1169 # number of overall misses +system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32018500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -229,63 +229,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.239178 # Cycle average of tags in use -system.cpu.icache.total_refs 66024644 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 769.803769 # Cycle average of tags in use +system.cpu.icache.total_refs 66013247 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 868 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67336673 # Number of branches executed -system.cpu.iew.EXEC:nop 43018581 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.810881 # Inst execution rate -system.cpu.iew.EXEC:refs 164027135 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41145337 # Number of stores executed +system.cpu.idleCycles 1575195 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316863 # Number of branches executed +system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate +system.cpu.iew.EXEC:refs 164017998 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41189464 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 491694974 # num instructions consuming a value -system.cpu.iew.WB:count 595952322 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.808476 # average fanout of values written-back +system.cpu.iew.WB:consumers 487237026 # num instructions consuming a value +system.cpu.iew.WB:count 596051181 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 397523802 # num instructions producing a value -system.cpu.iew.WB:rate 1.801228 # insts written-back per cycle -system.cpu.iew.WB:sent 597113280 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671395 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 85472 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 127086189 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3259094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43192001 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663707703 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122881798 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6536173 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599145915 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1317 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 395375822 # num instructions producing a value +system.cpu.iew.WB:rate 1.783749 # insts written-back per cycle +system.cpu.iew.WB:sent 597227214 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671564 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251991 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977207 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663380014 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828534 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459967 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258177 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2444 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9907520 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4668 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9869869 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84553 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4162 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7269203 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14266 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 32461 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5902 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 12036679 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3379478 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 32461 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540781 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4130614 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.709347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.709347 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605682088 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11927697 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540318 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692478 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692478 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718144 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438760030 72.44% # Type of FU issued - IntMult 6517 0.00% # Type of FU issued + IntAlu 438834867 72.45% # Type of FU issued + IntMult 6546 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -293,17 +293,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124950238 20.63% # Type of FU issued - MemWrite 41965260 6.93% # Type of FU issued + MemRead 124855458 20.61% # Type of FU issued + MemWrite 42021230 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6912738 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011413 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 7232327 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5342591 77.29% # attempts to use FU when none available - IntMult 72 0.00% # attempts to use FU when none available + IntAlu 5390835 74.54% # attempts to use FU when none available + IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 924602 13.38% # attempts to use FU when none available - MemWrite 645473 9.34% # attempts to use FU when none available + MemRead 1490139 20.60% # attempts to use FU when none available + MemWrite 351286 4.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 330857976 +system.cpu.iq.ISSUE:issued_per_cycle.samples 332581179 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 90630363 2739.25% - 1 66723730 2016.69% - 2 79382589 2399.30% - 3 36274593 1096.38% - 4 32477730 981.62% - 5 12845074 388.24% - 6 10946309 330.85% - 7 1065447 32.20% - 8 512141 15.48% + 0 92203834 2772.37% + 1 67051351 2016.09% + 2 80133785 2409.45% + 3 36043476 1083.75% + 4 30084945 904.59% + 5 14579095 438.36% + 6 10850498 326.25% + 7 1143008 34.37% + 8 491187 14.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.830636 # Inst issue rate -system.cpu.iq.iqInstsAdded 620689100 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605682088 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53858401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 17774 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29864580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66025708 # ITB accesses +system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate +system.cpu.iq.iqInstsAdded 620382610 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718144 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53519343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29313590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014456 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66025670 # ITB hits -system.cpu.itb.misses 38 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256615 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5221.239990 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2221.239990 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1339848500 # number of ReadExReq miss cycles +system.cpu.itb.hits 66014416 # ITB hits +system.cpu.itb.misses 40 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256615 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 570003500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256615 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5324.201615 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2324.201615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181418 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 190558500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164777 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83185500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80676 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5165.743220 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2166.071694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 416751500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.958543 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.588334 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1227944500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110234000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80676 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 174750000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80676 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334126 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334126 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.724082 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473824 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5233.842671 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181418 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1530407000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617119 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292406 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.680834 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10020758500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 653189000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292406 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9102616500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473824 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5233.842671 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.680834 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181418 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1530407000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617119 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292406 # number of overall misses +system.cpu.l2cache.overall_hits 181383 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10020758500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 653189000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292406 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9102616500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 85250 # number of replacements -system.cpu.l2cache.sampled_refs 100885 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 85262 # number of replacements +system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16355.319881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16333.158558 # Cycle average of tags in use +system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63237 # number of writebacks -system.cpu.numCycles 330858844 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11109833 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 63236 # number of writebacks +system.cpu.numCycles 334156374 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214869 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 34908767 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 152607206 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 316634 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 896955924 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680550426 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519573186 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116670528 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9907520 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 40562533 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55718297 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 356 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 79715664 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.timesIdled 189 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31587364 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899466 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 896816435 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424801 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473844 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116401000 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869869 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195269 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618955 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 77660301 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.timesIdled 36535 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index 8053728f7..337694eda 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index cbeafd848..069608705 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:22:47 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:11:39 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 0c02ed13c..2080bc2a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 7a8a25a24..5ddd02f93 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1122189 # Simulator instruction rate (inst/s) -host_mem_usage 222560 # Number of bytes of host memory used -host_seconds 536.32 # Real time elapsed on the host -host_tick_rate 1430957420 # Simulator tick rate (ticks/s) +host_inst_rate 1676744 # Simulator instruction rate (inst/s) +host_mem_usage 200380 # Number of bytes of host memory used +host_seconds 358.94 # Real time elapsed on the host +host_tick_rate 2167478980 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.767457 # Number of seconds simulated -sim_ticks 767457055000 # Number of ticks simulated +sim_seconds 0.778004 # Number of seconds simulated +sim_ticks 778003833000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16196.211338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13196.211338 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3259196000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2655500000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.984797 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8880052000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7893379000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22898.927230 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12139248000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10548879000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22898.927230 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 12139248000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses system.cpu.dcache.overall_misses 530123 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10548879000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.918042 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 357644000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.dtb.accesses 153970296 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 39451321 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21465000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 19080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21465000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.overall_miss_latency 21465000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.689179 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.225224 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 601861898 # ITB hits system.cpu.itb.misses 20 # ITB misses system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5845749000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 800193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22998.461086 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1718629000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6645942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3178494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6645942000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses system.cpu.l2cache.overall_misses 288954 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3178494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 84513 # number of replacements system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16357.683393 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 63194 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1534914110 # number of cpu cycles simulated +system.cpu.numCycles 1556007666 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 598fc86c0..26249ed90 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 1faa3f4e8..1e55b6a1c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:00 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:24 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 0b846692f..497d0c7b3 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 1aaf64650..38b460055 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 181900655 # Number of BTB hits -global.BPredUnit.BTBLookups 205112403 # Number of BTB lookups +global.BPredUnit.BTBHits 182414509 # Number of BTB hits +global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84376140 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 253553370 # Number of conditional branches predicted -global.BPredUnit.lookups 253553370 # Number of BP lookups +global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted +global.BPredUnit.lookups 254458067 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 148554 # Simulator instruction rate (inst/s) -host_mem_usage 214964 # Number of bytes of host memory used -host_seconds 9461.99 # Real time elapsed on the host -host_tick_rate 116526717 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 445262703 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 137431528 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 741823023 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303434035 # Number of stores inserted to the mem dependence unit. +host_inst_rate 99984 # Simulator instruction rate (inst/s) +host_mem_usage 203500 # Number of bytes of host memory used +host_seconds 14058.38 # Real time elapsed on the host +host_tick_rate 78434309 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618364 # Number of instructions simulated -sim_seconds 1.102575 # Number of seconds simulated -sim_ticks 1102574586000 # Number of ticks simulated +sim_insts 1405618365 # Number of instructions simulated +sim_seconds 1.102659 # Number of seconds simulated +sim_ticks 1102659164000 # Number of ticks simulated system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8144949 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1965667914 +system.cpu.commit.COM:committed_per_cycle.samples 1964055138 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1089833449 5544.34% - 1 574599936 2923.18% - 2 120982749 615.48% - 3 121997991 620.64% - 4 27903349 141.95% - 5 7399398 37.64% - 6 10434529 53.08% - 7 4371564 22.24% - 8 8144949 41.44% + 0 1088074348 5539.94% + 1 575643775 2930.89% + 2 120435536 613.20% + 3 120975808 615.95% + 4 27955061 142.33% + 5 8084154 41.16% + 6 10447088 53.19% + 7 4343249 22.11% + 8 8096119 41.22% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489537507 # Number of instructions committed -system.cpu.commit.COM:loads 402517242 # Number of loads committed +system.cpu.commit.COM:count 1489537508 # Number of instructions committed +system.cpu.commit.COM:loads 402517243 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375198 # Number of memory references committed +system.cpu.commit.COM:refs 569375199 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84376140 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537507 # The number of committed instructions +system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1379626157 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618364 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618364 # Number of Instructions Simulated -system.cpu.cpi 1.568811 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.568811 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 431515523 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5833.098785 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.922588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 430678453 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4882712000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 837070 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 610026 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 676346500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 227044 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618365 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated +system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 10313.448208 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.282564 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164722472 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22010528000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2134158 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1792190 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2651716500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002049 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 341968 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1192.957701 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 598372153 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9051.220573 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595400925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26893240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004966 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2971228 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2402216 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3328063000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 569012 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 598372153 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9051.220573 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595400925 # number of overall hits -system.cpu.dcache.overall_miss_latency 26893240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004966 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2971228 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2402216 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3328063000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 569012 # number of overall MSHR misses +system.cpu.dcache.overall_hits 589980362 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3138202 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 495162 # number of replacements -system.cpu.dcache.sampled_refs 499258 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 523278 # number of replacements +system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.748023 # Cycle average of tags in use -system.cpu.dcache.total_refs 595593676 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87021000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338803 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411671419 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3446173364 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 768410177 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782727450 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239480011 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2858868 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 253553370 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 356679957 # Number of cache lines fetched -system.cpu.fetch.Cycles 1203446624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10248361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3739591650 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90314479 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114982 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 356679957 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 181900655 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.695845 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use +system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 348745 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2205147925 +system.cpu.fetch.rateDist.samples 2203815119 system.cpu.fetch.rateDist.min_value 0 - 0 1358381303 6160.05% - 1 256975915 1165.35% - 2 81117048 367.85% - 3 38328968 173.82% - 4 87811486 398.21% - 5 41185341 186.77% - 6 30948688 140.35% - 7 20663450 93.71% - 8 289735726 1313.91% + 0 1359103013 6167.05% + 1 256500552 1163.89% + 2 81150170 368.23% + 3 38425919 174.36% + 4 85384466 387.44% + 5 41200028 186.95% + 6 32567288 147.78% + 7 20688755 93.88% + 8 288794928 1310.43% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 356679957 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8956.578947 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6409.949165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 356678437 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13614000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1520 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 8826500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1377 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 259025.734931 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356679957 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8956.578947 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency -system.cpu.icache.demand_hits 356678437 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13614000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1520 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 8826500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1377 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 356679957 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8956.578947 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency +system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 356678437 # number of overall hits -system.cpu.icache.overall_miss_latency 13614000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1520 # number of overall misses -system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 8826500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 354586500 # number of overall hits +system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 2127 # number of overall misses +system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1377 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -222,180 +222,180 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 225 # number of replacements -system.cpu.icache.sampled_refs 1377 # Sample count of references to valid blocks. +system.cpu.icache.replacements 222 # number of replacements +system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1055.483361 # Cycle average of tags in use -system.cpu.icache.total_refs 356678437 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use +system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1248 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 127608554 # Number of branches executed -system.cpu.iew.EXEC:nop 350339648 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.854427 # Inst execution rate -system.cpu.iew.EXEC:refs 751913263 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 205327824 # Number of stores executed +system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128154505 # Number of branches executed +system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate +system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207432555 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1480064020 # num instructions consuming a value -system.cpu.iew.WB:count 1846024853 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961974 # average fanout of values written-back +system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value +system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1423783452 # num instructions producing a value -system.cpu.iew.WB:rate 0.837143 # insts written-back per cycle -system.cpu.iew.WB:sent 1859136578 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 92169933 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 589367 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 741823023 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21373777 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17132653 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303434035 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2869227464 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 546585439 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102564755 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884138731 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 34478 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1435567316 # num instructions producing a value +system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle +system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6242 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239480011 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 64953 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115050896 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46197 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6187252 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 339305781 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 136576079 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6187252 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1512583 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90657350 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637426 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637426 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1986703486 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1179878973 59.39% # Type of FU issued + IntAlu 1186637130 59.65% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3034527 0.15% # Type of FU issued + FloatAdd 2990817 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 573304663 28.86% # Type of FU issued - MemWrite 230485323 11.60% # Type of FU issued + MemRead 571681967 28.74% # Type of FU issued + MemWrite 227997762 11.46% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3941252 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143239 3.63% # attempts to use FU when none available + IntAlu 142220 3.54% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 224135 5.69% # attempts to use FU when none available + FloatAdd 232758 5.80% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3231256 81.99% # attempts to use FU when none available - MemWrite 342622 8.69% # attempts to use FU when none available + MemRead 3328923 82.92% # attempts to use FU when none available + MemWrite 310728 7.74% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2205147925 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1087983599 4933.83% - 1 585856114 2656.77% - 2 293424201 1330.63% - 3 167599230 760.04% - 4 47518525 215.49% - 5 16542278 75.02% - 6 5287445 23.98% - 7 801144 3.63% - 8 135389 0.61% + 0 1083882017 4918.21% + 1 586425796 2660.96% + 2 298714416 1355.44% + 3 164995052 748.68% + 4 47215795 214.25% + 5 14943133 67.81% + 6 6716024 30.47% + 7 790185 3.59% + 8 132701 0.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.900938 # Inst issue rate -system.cpu.iq.iqInstsAdded 2497217188 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1986703486 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21670628 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1069660701 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 613054 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19426957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1294993120 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 272214 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5811.034701 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2811.034701 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1581845000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate +system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 272214 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 765203000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 272214 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 228421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5108.517819 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.517819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 193459 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 178604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.153059 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34962 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73718000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153059 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34962 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69801 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.620192 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.777783 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 363706500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69801 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154314500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69801 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338803 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338803 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.926755 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500635 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5731.075996 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 193459 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1760449000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.613573 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 307176 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 838921000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.613573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 307176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 500635 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5731.075996 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 193459 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1760449000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.613573 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 307176 # number of overall misses +system.cpu.l2cache.overall_hits 214675 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314078 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 838921000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.613573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 307176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -407,32 +407,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84458 # number of replacements -system.cpu.l2cache.sampled_refs 99911 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84497 # number of replacements +system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16412.598383 # Cycle average of tags in use -system.cpu.l2cache.total_refs 392326 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61939 # number of writebacks -system.cpu.numCycles 2205149173 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14473235 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779248 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 33041 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 831090066 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23088137 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4934375551 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3102245036 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2427299354 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 719533567 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239480011 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32278503 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1182520106 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368292543 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22008551 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170259176 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21764852 # count of temporary serializing insts renamed -system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.numCycles 2205318329 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed +system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index 320065be7..22ad4f8ac 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7005 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index e3c9fc9e3..331ed166e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:54 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:21:17 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1102574586000 because target called exit() +Exiting @ tick 1102659164000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index f120ae25d..2047c5ea9 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index db0a24071..da605e80a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2417575 # Simulator instruction rate (inst/s) -host_mem_usage 214112 # Number of bytes of host memory used -host_seconds 616.12 # Real time elapsed on the host -host_tick_rate 3359990664 # Simulator tick rate (ticks/s) +host_inst_rate 1927863 # Simulator instruction rate (inst/s) +host_mem_usage 202560 # Number of bytes of host memory used +host_seconds 772.63 # Real time elapsed on the host +host_tick_rate 2692643700 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.070168 # Number of seconds simulated -sim_ticks 2070168106000 # Number of ticks simulated +sim_seconds 2.080416 # Number of seconds simulated +sim_ticks 2080416155000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16193.228451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13193.228451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3133163000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2552705000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8629063000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7670278000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22924.696101 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 11762226000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10222983000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22924.696101 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568846579 # number of overall hits -system.cpu.dcache.overall_miss_latency 11762226000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10222983000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.496088 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 375475000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316420 # number of writebacks system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.026197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.026197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29837000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.026197 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29837000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.026197 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489527099 # number of overall hits -system.cpu.icache.overall_miss_latency 29837000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1107 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.562887 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5973905000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857085000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 776158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 371206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232053 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1377654000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658900000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6750063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3228291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 160847 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6750063000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses system.cpu.l2cache.overall_misses 293481 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3228291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 82905 # number of replacements system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16362.166769 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61861 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4140336212 # number of cpu cycles simulated +system.cpu.numCycles 4160832310 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index 2a6ac4135..cdd59eda7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index ee95b95c4..78d24c8c9 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:02:08 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:23:47 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2070168106000 because target called exit() +Exiting @ tick 2080416155000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index a9975c5c8..0493cbfab 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:268435455 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 797c83359..eb056d4cc 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2198270 # Simulator instruction rate (inst/s) -host_mem_usage 346304 # Number of bytes of host memory used -host_seconds 110.92 # Real time elapsed on the host -host_tick_rate 3278529226 # Simulator tick rate (ticks/s) +host_inst_rate 1384402 # Simulator instruction rate (inst/s) +host_mem_usage 334744 # Number of bytes of host memory used +host_seconds 176.13 # Real time elapsed on the host +host_tick_rate 2080531769 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.363660 # Number of seconds simulated -sim_ticks 363659868000 # Number of ticks simulated +sim_seconds 0.366446 # Number of seconds simulated +sim_ticks 366445521000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14002.999360 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.999360 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12502676000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9824105000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 216000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 192000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2564001000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2279112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15252.451864 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15066677000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12103217000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15252.451864 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 104134565 # number of overall hits -system.cpu.dcache.overall_miss_latency 15066677000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses system.cpu.dcache.overall_misses 987820 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12103217000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3566.422282 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134205827000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26970.521542 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.521542 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23788000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 21142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26970.521542 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23788000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 882 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26970.521542 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 244430745 # number of overall hits -system.cpu.icache.overall_miss_latency 23788000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 882 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 725.877742 # Cycle average of tags in use +system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1074422000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 513854000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 24978000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1109911000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530827000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1099400000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 525800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 892653 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1099400000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses system.cpu.l2cache.overall_misses 47800 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 525800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8943.216339 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 727319736 # number of cpu cycles simulated +system.cpu.numCycles 732891042 # number of cpu cycles simulated system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_refs 105711442 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index c59920875..320065be7 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 66cc737ad..1d6b63175 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:53 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:25:03 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 363659868000 because target called exit() +Exiting @ tick 366445521000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index bcc536301..67cb70d64 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index c2cc5eeb4..ec7c6b89a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 37055347 # Number of BTB hits -global.BPredUnit.BTBLookups 45947414 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1096 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5691744 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted -global.BPredUnit.lookups 62480259 # Number of BP lookups -global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target. -host_inst_rate 99164 # Simulator instruction rate (inst/s) -host_mem_usage 157680 # Number of bytes of host memory used -host_seconds 3787.43 # Real time elapsed on the host -host_tick_rate 35615266 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92782205 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 38296034 # Number of BTB hits +global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted +global.BPredUnit.lookups 62209737 # Number of BP lookups +global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. +host_inst_rate 169173 # Simulator instruction rate (inst/s) +host_mem_usage 208828 # Number of bytes of host memory used +host_seconds 2220.07 # Real time elapsed on the host +host_tick_rate 60807494 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134890 # Number of seconds simulated -sim_ticks 134890208500 # Number of ticks simulated +sim_seconds 0.134997 # Number of seconds simulated +sim_ticks 134996684500 # Number of ticks simulated system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13065530 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 254286247 +system.cpu.commit.COM:committed_per_cycle.samples 254545672 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123470433 4855.57% - 1 49744073 1956.22% - 2 18820215 740.12% - 3 19293865 758.75% - 4 12510791 492.00% - 5 8575068 337.22% - 6 5688152 223.69% - 7 3118120 122.62% - 8 13065530 513.81% + 0 123085209 4835.49% + 1 50466868 1982.63% + 2 18758377 736.94% + 3 19955031 783.95% + 4 11844121 465.30% + 5 8478667 333.09% + 6 5819307 228.62% + 7 2974518 116.86% + 8 13163574 517.14% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 100651995 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5687554 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 96777858 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads +system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95885716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9843.626807 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1522 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33012.273524 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95499598 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1711 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9673.649142 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000149 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 10956 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40554.032799 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40460.273163 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169406445 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9694.382113 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000074 # miss rate for demand accesses -system.cpu.dcache.demand_misses 12478 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169002314 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602471492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses +system.cpu.dcache.demand_misses 19724 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169406445 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9694.382113 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169393967 # number of overall hits -system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000074 # miss rate for overall accesses -system.cpu.dcache.overall_misses 12478 # number of overall misses -system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169002314 # number of overall hits +system.cpu.dcache.overall_miss_latency 602471492 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses +system.cpu.dcache.overall_misses 19724 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15431 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.replacements 782 # number of replacements system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use -system.cpu.dcache.total_refs 169394195 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use +system.cpu.dcache.total_refs 169002561 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 636 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4312 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11369096 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 533723337 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 133094788 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 100949486 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15490881 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12729 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1286410 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 186077432 # DTB accesses -system.cpu.dtb.acv 11216 # DTB access violations -system.cpu.dtb.hits 186006805 # DTB hits -system.cpu.dtb.misses 70627 # DTB misses -system.cpu.dtb.read_accesses 104841123 # DTB read accesses -system.cpu.dtb.read_acv 11216 # DTB read access violations -system.cpu.dtb.read_hits 104772046 # DTB read hits -system.cpu.dtb.read_misses 69077 # DTB read misses -system.cpu.dtb.write_accesses 81236309 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 81234759 # DTB write hits -system.cpu.dtb.write_misses 1550 # DTB write misses -system.cpu.fetch.Branches 62480259 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 64020665 # Number of cache lines fetched -system.cpu.fetch.Cycles 168778939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1468351 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 547045642 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6042059 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.231597 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 64020665 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 49453854 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.027744 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 635 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 185115437 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 185076670 # DTB hits +system.cpu.dtb.misses 38767 # DTB misses +system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 104412186 # DTB read hits +system.cpu.dtb.read_misses 37313 # DTB read misses +system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80664484 # DTB write hits +system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched +system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 269777129 +system.cpu.fetch.rateDist.samples 269852647 system.cpu.fetch.rateDist.min_value 0 - 0 165019149 6116.87% - 1 11208105 415.46% - 2 10970042 406.63% - 3 7809028 289.46% - 4 16007682 593.37% - 5 8770390 325.10% - 6 6686429 247.85% - 7 3981315 147.58% - 8 39324989 1457.68% + 0 164102333 6081.18% + 1 12367121 458.29% + 2 12410556 459.90% + 3 6615129 245.14% + 4 15923029 590.06% + 5 8709903 322.77% + 6 6580254 243.85% + 7 4007808 148.52% + 8 39136514 1450.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 64020665 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8765.688380 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4191 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3895 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16435.551733 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 64020665 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8765.688380 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency -system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_misses 4191 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3895 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 64020665 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8765.688380 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency +system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 64016474 # number of overall hits -system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_misses 4191 # number of overall misses -system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 63861348 # number of overall hits +system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.overall_misses 4841 # number of overall misses +system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3895 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1973 # number of replacements -system.cpu.icache.sampled_refs 3895 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1826.958701 # Cycle average of tags in use -system.cpu.icache.total_refs 64016474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use +system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 3290 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51062363 # Number of branches executed -system.cpu.iew.EXEC:nop 27214999 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.560789 # Inst execution rate -system.cpu.iew.EXEC:refs 192842691 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 81246989 # Number of stores executed +system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50976852 # Number of branches executed +system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate +system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80676625 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 287107823 # num instructions consuming a value -system.cpu.iew.WB:count 417299912 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702706 # average fanout of values written-back +system.cpu.iew.WB:consumers 285463488 # num instructions consuming a value +system.cpu.iew.WB:count 415481244 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 201752289 # num instructions producing a value -system.cpu.iew.WB:rate 1.546813 # insts written-back per cycle -system.cpu.iew.WB:sent 418066212 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6311133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2198946 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125306666 # Number of dispatched load instructions +system.cpu.iew.WB:producers 200770523 # num instructions producing a value +system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle +system.cpu.iew.WB:sent 416287471 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390314 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6339692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92782205 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 495443138 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111595702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10411801 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 421070304 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 127438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10261542 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338657 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15490881 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 491568 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8710387 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3327 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 505299 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 175942 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24654671 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19250803 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 505299 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 821714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5489419 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.392150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.392150 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 431482105 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542510 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 429600199 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 167002612 38.70% # Type of FU issued - IntMult 2153139 0.50% # Type of FU issued + IntAlu 166319017 38.71% # Type of FU issued + IntMult 2152935 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34874757 8.08% # Type of FU issued - FloatCmp 7889981 1.83% # Type of FU issued - FloatCvt 2903377 0.67% # Type of FU issued - FloatMult 16803027 3.89% # Type of FU issued - FloatDiv 1591666 0.37% # Type of FU issued + FloatAdd 35077566 8.17% # Type of FU issued + FloatCmp 7830879 1.82% # Type of FU issued + FloatCvt 2898460 0.67% # Type of FU issued + FloatMult 16788316 3.91% # Type of FU issued + FloatDiv 1569716 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114230521 26.47% # Type of FU issued - MemWrite 83999444 19.47% # Type of FU issued + MemRead 113503270 26.42% # Type of FU issued + MemWrite 83426459 19.42% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10446664 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024211 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 32363 0.31% # attempts to use FU when none available + IntAlu 40640 0.39% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 95689 0.92% # attempts to use FU when none available - FloatCmp 7492 0.07% # attempts to use FU when none available - FloatCvt 12721 0.12% # attempts to use FU when none available - FloatMult 1683122 16.11% # attempts to use FU when none available - FloatDiv 1408746 13.49% # attempts to use FU when none available + FloatAdd 76056 0.73% # attempts to use FU when none available + FloatCmp 13381 0.13% # attempts to use FU when none available + FloatCvt 12891 0.12% # attempts to use FU when none available + FloatMult 1723474 16.48% # attempts to use FU when none available + FloatDiv 1473560 14.09% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5941492 56.87% # attempts to use FU when none available - MemWrite 1265039 12.11% # attempts to use FU when none available + MemRead 5907144 56.49% # attempts to use FU when none available + MemWrite 1209900 11.57% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 269777129 +system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99508340 3688.54% - 1 57898126 2146.15% - 2 39403533 1460.60% - 3 28850583 1069.42% - 4 24598298 911.80% - 5 10625217 393.85% - 6 6146486 227.84% - 7 2145397 79.52% - 8 601149 22.28% + 0 99465935 3685.94% + 1 57766030 2140.65% + 2 39984555 1481.72% + 3 29664957 1099.30% + 4 23966119 888.12% + 5 10452564 387.34% + 6 5712017 211.67% + 7 2252970 83.49% + 8 587500 21.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.599383 # Inst issue rate -system.cpu.iq.iqInstsAdded 468227900 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 431482105 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate +system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 429600199 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 91553989 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1306748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68680838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 64020959 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 68228106 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63866476 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 64020665 # ITB hits -system.cpu.itb.misses 294 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6098.591549 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3098.591549 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 19485000 # number of ReadExReq miss cycles +system.cpu.itb.hits 63866189 # ITB hits +system.cpu.itb.misses 287 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9900000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5592.080378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2592.080378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 647 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 23654500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.867336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4230 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10964500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4230 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5698.347107 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2698.347107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 689500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.128309 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8072 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 647 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 43139500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.919846 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7425 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 20864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.919846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8072 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 647 # number of overall hits -system.cpu.l2cache.overall_miss_latency 43139500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.919846 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7425 # number of overall misses +system.cpu.l2cache.overall_hits 655 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7418 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 20864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.919846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 15 # number of replacements -system.cpu.l2cache.sampled_refs 4684 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 14 # number of replacements +system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3884.477480 # Cycle average of tags in use -system.cpu.l2cache.total_refs 601 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use +system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 269780419 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8898218 # Number of cycles rename is blocking +system.cpu.numCycles 269993372 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1493929 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 138057394 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7378387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 685335905 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 519882318 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 336260549 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96875532 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15490881 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10098203 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76728208 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 356901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37939 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22218757 # count of insts added to the skid buffer +system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index 56a19a708..982c0e2fd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 53e92e76c..bdcee079b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:58 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:19 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 4e4683ed6..77ba42098 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index f6e3615e0..193a2e752 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 948947 # Simulator instruction rate (inst/s) -host_mem_usage 204452 # Number of bytes of host memory used -host_seconds 420.11 # Real time elapsed on the host -host_tick_rate 1349967290 # Simulator tick rate (ticks/s) +host_inst_rate 1657758 # Simulator instruction rate (inst/s) +host_mem_usage 207956 # Number of bytes of host memory used +host_seconds 240.48 # Real time elapsed on the host +host_tick_rate 2359203743 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567139 # Number of seconds simulated -sim_ticks 567138642000 # Number of ticks simulated +sim_seconds 0.567352 # Number of seconds simulated +sim_ticks 567351850000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24129000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 79536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 113607000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 100815000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 113607000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4264 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100815000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.418113 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 73520730 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25343.588347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 93087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 82068000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 93087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 82068000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.overall_miss_latency 93087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 82068000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.354000 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 398664666 # ITB hits system.cpu.itb.misses 173 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 73646000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 92874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2576000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 166520000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 585 # number of overall hits -system.cpu.l2cache.overall_miss_latency 166520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses system.cpu.l2cache.overall_misses 7240 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 15 # number of replacements system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3714.818787 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134277284 # number of cpu cycles simulated +system.cpu.numCycles 1134703700 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 57ac24419..292df496c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7005 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 9f21edbf0..0958fd3e9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:28 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:16:23 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 360603943..edda67681 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=perlbmk -I. -I lib lgred.makerand.pl cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 6e1f5bd66..a29c5dd96 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1017888 # Simulator instruction rate (inst/s) -host_mem_usage 209744 # Number of bytes of host memory used -host_seconds 1973.68 # Real time elapsed on the host -host_tick_rate 1403993769 # Simulator tick rate (ticks/s) +host_inst_rate 1695111 # Simulator instruction rate (inst/s) +host_mem_usage 207112 # Number of bytes of host memory used +host_seconds 1185.17 # Real time elapsed on the host +host_tick_rate 2375153470 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.771038 # Number of seconds simulated -sim_ticks 2771037759000 # Number of ticks simulated +sim_seconds 2.814951 # Number of seconds simulated +sim_ticks 2814951154000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26811.881426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23811.881426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 39096871000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 34722295000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.692460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.692460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2019226000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1794865000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26821.043863 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 41116097000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 36517160000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26821.043863 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720331943 # number of overall hits -system.cpu.dcache.overall_miss_latency 41116097000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses system.cpu.dcache.overall_misses 1532979 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 36517160000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.350762 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 812770000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.dtb.accesses 722298387 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 210794896 # DTB write hits system.cpu.dtb.write_misses 14581 # DTB write misses system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 16916.289166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13916.289166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 179245000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147457000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 16916.289166 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 179245000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147457000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 16916.289166 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2009410475 # number of overall hits -system.cpu.icache.overall_miss_latency 179245000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147457000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.550297 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2009421071 # ITB hits system.cpu.itb.misses 105 # ITB misses system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1654896000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 791472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 33107764000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22813.403880 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 64676000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 34762660000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16625620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 29320 # number of overall hits -system.cpu.l2cache.overall_miss_latency 34762660000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1511420 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16625620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1473608 # number of replacements system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31923.721558 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66899 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5542075518 # number of cpu cycles simulated +system.cpu.numCycles 5629902308 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index fc28a8ff6..ef87f0bcb 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index 722e49f95..f85223189 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:00 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:20 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second 1375000: 2038431008 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 162b46290..8de3e1042 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 2e39bfe33..6cd7ed43b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8028209 # Number of BTB hits -global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted -global.BPredUnit.lookups 16239906 # Number of BP lookups -global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target. -host_inst_rate 108698 # Simulator instruction rate (inst/s) -host_mem_usage 171788 # Number of bytes of host memory used -host_seconds 732.23 # Real time elapsed on the host -host_tick_rate 34286652 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 8039248 # Number of BTB hits +global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted +global.BPredUnit.lookups 16249458 # Number of BP lookups +global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +host_inst_rate 176565 # Simulator instruction rate (inst/s) +host_mem_usage 212168 # Number of bytes of host memory used +host_seconds 450.78 # Real time elapsed on the host +host_tick_rate 60195419 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.025106 # Number of seconds simulated -sim_ticks 25105678500 # Number of ticks simulated +sim_seconds 0.027135 # Number of seconds simulated +sim_ticks 27134783500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 48941983 +system.cpu.commit.COM:committed_per_cycle.samples 51751153 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 20096984 4106.29% - 1 10996856 2246.92% - 2 5104227 1042.91% - 3 3459002 706.76% - 4 2556441 522.34% - 5 1507300 307.98% - 6 975853 199.39% - 7 821586 167.87% - 8 3423734 699.55% + 0 22506428 4348.97% + 1 11357580 2194.65% + 2 5114502 988.29% + 3 3560855 688.07% + 4 2552506 493.23% + 5 1532718 296.17% + 6 1008932 194.96% + 7 796739 153.96% + 8 3320893 641.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20452895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8143.771495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007108 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 145380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses +system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7484.182742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069117 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1010036 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.460856 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35066272 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7567.175372 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.032949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1155416 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35066272 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7567.175372 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33910856 # number of overall hits -system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.032949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1155416 # number of overall misses -system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33838927 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1199961 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200914 # number of replacements -system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200933 # number of replacements +system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use -system.cpu.dcache.total_refs 33921130 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147756 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36627367 # DTB accesses +system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147760 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599686 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36456086 # DTB hits -system.cpu.dtb.misses 171281 # DTB misses -system.cpu.dtb.read_accesses 21562223 # DTB read accesses +system.cpu.dtb.hits 36425478 # DTB hits +system.cpu.dtb.misses 174208 # DTB misses +system.cpu.dtb.read_accesses 21541286 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21405571 # DTB read hits -system.cpu.dtb.read_misses 156652 # DTB read misses -system.cpu.dtb.write_accesses 15065144 # DTB write accesses +system.cpu.dtb.read_hits 21383018 # DTB read hits +system.cpu.dtb.read_misses 158268 # DTB read misses +system.cpu.dtb.write_accesses 15058400 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15050515 # DTB write hits -system.cpu.dtb.write_misses 14629 # DTB write misses -system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched -system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 15042460 # DTB write hits +system.cpu.dtb.write_misses 15940 # DTB write misses +system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched +system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 50204254 +system.cpu.fetch.rateDist.samples 53041252 system.cpu.fetch.rateDist.min_value 0 - 0 30393344 6053.94% - 1 1855009 369.49% - 2 1535971 305.94% - 3 1792342 357.01% - 4 4000264 796.80% - 5 1878750 374.22% - 6 697475 138.93% - 7 1087494 216.61% - 8 6963605 1387.05% + 0 33206262 6260.46% + 1 1871594 352.86% + 2 1529415 288.34% + 3 1809626 341.17% + 4 3985239 751.35% + 5 1867237 352.03% + 6 695846 131.19% + 7 1111736 209.60% + 8 6964297 1313.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13373612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5755.491777 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 86584 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006388 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13373612 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5755.491777 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency -system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006474 # miss rate for demand accesses -system.cpu.icache.demand_misses 86584 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006388 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses +system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13373612 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5755.491777 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13287028 # number of overall hits -system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006474 # miss rate for overall accesses -system.cpu.icache.overall_misses 86584 # number of overall misses -system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006388 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses +system.cpu.icache.overall_hits 13297365 # number of overall hits +system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses +system.cpu.icache.overall_misses 88707 # number of overall misses +system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83382 # number of replacements -system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83888 # number of replacements +system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use -system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use +system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14739955 # Number of branches executed -system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate -system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15298022 # Number of stores executed +system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745483 # Number of branches executed +system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate +system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291391 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value -system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back +system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value +system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32426009 # num instructions producing a value -system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle -system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32396966 # num instructions producing a value +system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle +system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47875288 56.09% # Type of FU issued - IntMult 42930 0.05% # Type of FU issued + IntAlu 47898540 56.12% # Type of FU issued + IntMult 42953 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 121387 0.14% # Type of FU issued - FloatCmp 87 0.00% # Type of FU issued - FloatCvt 121941 0.14% # Type of FU issued - FloatMult 50 0.00% # Type of FU issued - FloatDiv 38534 0.05% # Type of FU issued + FloatAdd 121655 0.14% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122104 0.14% # Type of FU issued + FloatMult 53 0.00% # Type of FU issued + FloatDiv 38535 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21778158 25.51% # Type of FU issued - MemWrite 15380330 18.02% # Type of FU issued + MemRead 21753620 25.49% # Type of FU issued + MemWrite 15368768 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 96046 9.70% # attempts to use FU when none available + IntAlu 97095 9.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 442273 44.69% # attempts to use FU when none available - MemWrite 451365 45.61% # attempts to use FU when none available + MemRead 470602 48.04% # attempts to use FU when none available + MemWrite 411938 42.05% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254 +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 15297066 3046.97% - 1 13336776 2656.50% - 2 8168141 1626.98% - 3 4718425 939.85% - 4 4728752 941.90% - 5 2063960 411.11% - 6 1191217 237.27% - 7 451074 89.85% - 8 248843 49.57% + 0 17563400 3311.27% + 1 13937997 2627.77% + 2 8266118 1558.43% + 3 4784811 902.09% + 4 4627571 872.45% + 5 2066742 389.65% + 6 1112371 209.72% + 7 454506 85.69% + 8 227736 42.94% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate -system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13398974 # ITB accesses +system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate +system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13412237 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13373612 # ITB hits -system.cpu.itb.misses 25362 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles +system.cpu.itb.hits 13386072 # ITB hits +system.cpu.itb.misses 26165 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102374 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188067 # number of overall misses +system.cpu.l2cache.overall_hits 102894 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188071 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 148782 # number of replacements -system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148779 # number of replacements +system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use -system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120646 # number of writebacks -system.cpu.numCycles 50211358 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.numCycles 54269568 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed -system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed +system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index 5992f7131..d6124e8ba 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7005 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index f03ee0333..103f04999 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:19:28 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:52 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 99587aea2..8d7054aba 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 068d99b92..fcf32cd99 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 866615 # Simulator instruction rate (inst/s) -host_mem_usage 218536 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host -host_tick_rate 1271060462 # Simulator tick rate (ticks/s) +host_inst_rate 1478736 # Simulator instruction rate (inst/s) +host_mem_usage 210524 # Number of bytes of host memory used +host_seconds 59.74 # Real time elapsed on the host +host_tick_rate 2262580844 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.129569 # Number of seconds simulated -sim_ticks 129569130000 # Number of ticks simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168711000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210558 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 88438074 # ITB hits system.cpu.itb.misses 3934 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses system.cpu.l2cache.overall_misses 186874 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 147560 # number of replacements system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259138260 # number of cpu cycles simulated +system.cpu.numCycles 270337422 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index 26249ed90..598fc86c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index c568a72c2..82f9f1165 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:10:35 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 77a49bdbd..b127e5d20 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=vortex bendian.raw cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 89c35043c..398922df0 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 809753 # Simulator instruction rate (inst/s) -host_mem_usage 216324 # Number of bytes of host memory used -host_seconds 168.12 # Real time elapsed on the host -host_tick_rate 1194295397 # Simulator tick rate (ticks/s) +host_inst_rate 1368614 # Simulator instruction rate (inst/s) +host_mem_usage 211448 # Number of bytes of host memory used +host_seconds 99.47 # Real time elapsed on the host +host_tick_rate 2062044712 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.200790 # Number of seconds simulated -sim_ticks 200790381000 # Number of ticks simulated +sim_seconds 0.205117 # Number of seconds simulated +sim_ticks 205116920000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1594175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses system.cpu.l2cache.overall_misses 144925 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1594175000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 401580762 # number of cpu cycles simulated +system.cpu.numCycles 410233840 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index b5ea49da4..fc5baf4b1 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 592b35b7a..dd1bc90df 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:36:59 2008 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:28:00 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200790381000 because target called exit() +Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index be4327e6c..26fa15dd4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 98a4ae9ba..3ee235d33 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 298925307 # Number of BTB hits -global.BPredUnit.BTBLookups 307254403 # Number of BTB lookups -global.BPredUnit.RASInCorrect 123 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19461333 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 256954278 # Number of conditional branches predicted -global.BPredUnit.lookups 332748805 # Number of BP lookups -global.BPredUnit.usedRAS 23332154 # Number of times the RAS was used to get a target. -host_inst_rate 98561 # Simulator instruction rate (inst/s) -host_mem_usage 329172 # Number of bytes of host memory used -host_seconds 17613.94 # Real time elapsed on the host -host_tick_rate 37548074 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 73213571 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 37308198 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 599919223 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 223513381 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 312845728 # Number of BTB hits +global.BPredUnit.BTBLookups 319575550 # Number of BTB lookups +global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19647323 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 266741487 # Number of conditional branches predicted +global.BPredUnit.lookups 345502581 # Number of BP lookups +global.BPredUnit.usedRAS 23750301 # Number of times the RAS was used to get a target. +host_inst_rate 237180 # Simulator instruction rate (inst/s) +host_mem_usage 201180 # Number of bytes of host memory used +host_seconds 7319.53 # Real time elapsed on the host +host_tick_rate 101414942 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 67515290 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 621608429 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 234046219 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.661370 # Number of seconds simulated -sim_ticks 661369625500 # Number of ticks simulated +sim_seconds 0.742309 # Number of seconds simulated +sim_ticks 742309410500 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 64339411 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 62782580 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1246869641 +system.cpu.commit.COM:committed_per_cycle.samples 1379215313 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 606206692 4861.83% - 1 260350579 2088.03% - 2 123843780 993.24% - 3 79587483 638.30% - 4 49145226 394.15% - 5 29422011 235.97% - 6 23247922 186.45% - 7 10726537 86.03% - 8 64339411 516.01% + 0 736540795 5340.29% + 1 260049510 1885.49% + 2 126970462 920.60% + 3 77723430 563.53% + 4 51327443 372.15% + 5 27759546 201.27% + 6 26179569 189.81% + 7 9881978 71.65% + 8 62782580 455.21% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,80 +43,80 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19460831 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19646822 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 498311436 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 627314196 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.761927 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.761927 # CPI: Total CPI of All Threads +system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 6500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 9500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 6500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 514699566 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6709.313547 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3665.501336 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 505997425 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 58385392500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016907 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 8702141 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1427526 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 26665111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014134 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7274615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 523259958 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16887.800030 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.117004 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 512954318 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 174039587500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 10305640 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3030506 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 81969786000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7275134 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 10289.713687 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 156501908 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 43490442133 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.026296 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4226594 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1977957 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 22750942389 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 33917.186217 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824413 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155297499 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 184204340094 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5431003 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 83541340193 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248637 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2040.681665 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2667.920935 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.404790 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 71409 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 145723037 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 173711000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 2248526 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 73.053389 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 675428068 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7879.799117 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency -system.cpu.dcache.demand_hits 662499333 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 101875834633 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019142 # miss rate for demand accesses -system.cpu.dcache.demand_misses 12928735 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3405483 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 49416053389 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014100 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523252 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 683988460 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22764.952321 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668251817 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 358243927594 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses +system.cpu.dcache.demand_misses 15736643 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6212983 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 165511126193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9523660 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 675428068 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7879.799117 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 683988460 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22764.952321 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 662499333 # number of overall hits -system.cpu.dcache.overall_miss_latency 101875834633 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019142 # miss rate for overall accesses -system.cpu.dcache.overall_misses 12928735 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3405483 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 49416053389 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014100 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523252 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668251817 # number of overall hits +system.cpu.dcache.overall_miss_latency 358243927594 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses +system.cpu.dcache.overall_misses 15736643 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6212983 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 165511126193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9523660 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,104 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155291 # number of replacements -system.cpu.dcache.sampled_refs 9159387 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9155770 # number of replacements +system.cpu.dcache.sampled_refs 9159866 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377148 # Cycle average of tags in use -system.cpu.dcache.total_refs 663183492 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6956358000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245548 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25695554 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 564 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 51842469 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2704061258 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 689853878 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 528999718 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 75857193 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1673 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2320492 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 762597100 # DTB accesses +system.cpu.dcache.tagsinuse 4082.023671 # Cycle average of tags in use +system.cpu.dcache.total_refs 669159252 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245448 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 98604485 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2810650716 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 726334598 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 549143095 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 93084197 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 768331628 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 747387018 # DTB hits -system.cpu.dtb.misses 15210082 # DTB misses -system.cpu.dtb.read_accesses 561654782 # DTB read accesses +system.cpu.dtb.hits 752318827 # DTB hits +system.cpu.dtb.misses 16012801 # DTB misses +system.cpu.dtb.read_accesses 566617541 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 552717840 # DTB read hits -system.cpu.dtb.read_misses 8936942 # DTB read misses -system.cpu.dtb.write_accesses 200942318 # DTB write accesses +system.cpu.dtb.read_hits 557381515 # DTB read hits +system.cpu.dtb.read_misses 9236026 # DTB read misses +system.cpu.dtb.write_accesses 201714087 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 194669178 # DTB write hits -system.cpu.dtb.write_misses 6273140 # DTB write misses -system.cpu.fetch.Branches 332748805 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 340572268 # Number of cache lines fetched -system.cpu.fetch.Cycles 882406365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8482299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2756699547 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 26531665 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.251560 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 340572268 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 322257461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.084084 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 194937312 # DTB write hits +system.cpu.dtb.write_misses 6776775 # DTB write misses +system.cpu.fetch.Branches 345502581 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355180514 # Number of cache lines fetched +system.cpu.fetch.Cycles 920206753 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7941780 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2863046416 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28103164 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 355180514 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336596029 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1322726835 +system.cpu.fetch.rateDist.samples 1472299511 system.cpu.fetch.rateDist.min_value 0 - 0 780892776 5903.66% - 1 46232823 349.53% - 2 32110220 242.76% - 3 49083369 371.08% - 4 120415668 910.36% - 5 67469038 510.08% - 6 46013556 347.87% - 7 40168101 303.68% - 8 140341284 1061.00% + 0 907273306 6162.29% + 1 47886355 325.25% + 2 34613457 235.10% + 3 52095475 353.84% + 4 125971052 855.61% + 5 69335096 470.93% + 6 50458684 342.72% + 7 40993758 278.43% + 8 143672328 975.84% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 340572268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9183.349374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6758.046615 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 340571229 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 9541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 355180514 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 355179280 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1039 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 138 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 377992.485017 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 393768.603104 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 340572268 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9183.349374 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency -system.cpu.icache.demand_hits 340571229 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 9541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 355180514 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency +system.cpu.icache.demand_hits 355179280 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 1039 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 138 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 340572268 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9183.349374 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency +system.cpu.icache.overall_accesses 355180514 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 340571229 # number of overall hits -system.cpu.icache.overall_miss_latency 9541500 # number of overall miss cycles +system.cpu.icache.overall_hits 355179280 # number of overall hits +system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 1039 # number of overall misses -system.cpu.icache.overall_mshr_hits 138 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1234 # number of overall misses +system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -238,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 708.208043 # Cycle average of tags in use -system.cpu.icache.total_refs 340571229 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 711.425376 # Cycle average of tags in use +system.cpu.icache.total_refs 355179280 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12417 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 272957078 # Number of branches executed -system.cpu.iew.EXEC:nop 123939642 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.684042 # Inst execution rate -system.cpu.iew.EXEC:refs 763895221 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 201165010 # Number of stores executed +system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 282186317 # Number of branches executed +system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate +system.cpu.iew.EXEC:refs 769619313 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 201925300 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1488939134 # num instructions consuming a value -system.cpu.iew.WB:count 2188676291 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.814314 # average fanout of values written-back +system.cpu.iew.WB:consumers 1531990742 # num instructions consuming a value +system.cpu.iew.WB:count 2240290220 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1212463676 # num instructions producing a value -system.cpu.iew.WB:rate 1.654654 # insts written-back per cycle -system.cpu.iew.WB:sent 2210006196 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21034553 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251453 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 599919223 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 23371349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 223513381 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2521543989 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 562730211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 40765112 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2227547936 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36991 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1243717846 # num instructions producing a value +system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle +system.cpu.iew.WB:sent 2261678921 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21342133 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 621608429 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 234046219 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2621719070 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 567694013 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 36858072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2278986798 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5661 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 75857193 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 176880 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 93084197 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 196633 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 37920789 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 331554 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 33889592 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 439987 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 154252862 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62608399 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 439987 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 706308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20328245 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.312461 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.312461 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2268313048 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 175942068 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 73141237 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20638337 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2315844870 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1489479679 65.66% # Type of FU issued - IntMult 80 0.00% # Type of FU issued + IntAlu 1532920234 66.19% # Type of FU issued + IntMult 99 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 221 0.00% # Type of FU issued - FloatCmp 17 0.00% # Type of FU issued + FloatAdd 234 0.00% # Type of FU issued + FloatCmp 20 0.00% # Type of FU issued FloatCvt 143 0.00% # Type of FU issued - FloatMult 14 0.00% # Type of FU issued + FloatMult 16 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 574434192 25.32% # Type of FU issued - MemWrite 204398678 9.01% # Type of FU issued + MemRead 577889725 24.95% # Type of FU issued + MemWrite 205034375 8.85% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 16429831 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007243 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2410991 14.67% # attempts to use FU when none available + IntAlu 2738956 19.03% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -319,102 +319,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 10617024 64.62% # attempts to use FU when none available - MemWrite 3401816 20.71% # attempts to use FU when none available + MemRead 9224843 64.09% # attempts to use FU when none available + MemWrite 2429770 16.88% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1322726835 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299511 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 474192746 3584.96% - 1 247291499 1869.56% - 2 221816340 1676.96% - 3 137127863 1036.71% - 4 113209815 855.88% - 5 74495950 563.20% - 6 43530199 329.09% - 7 8994308 68.00% - 8 2068115 15.64% + 0 577695747 3923.77% + 1 271543753 1844.35% + 2 242868164 1649.58% + 3 139713871 948.95% + 4 122021081 828.78% + 5 69652696 473.09% + 6 39670195 269.44% + 7 8017830 54.46% + 8 1116174 7.58% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.714860 # Inst issue rate -system.cpu.iq.iqInstsAdded 2397604305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2268313048 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 649290621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 732371 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 261741042 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 340572306 # ITB accesses +system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate +system.cpu.iq.iqInstsAdded 2492922470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2315844870 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 739697575 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1501742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 329349436 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 355180548 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 340572268 # ITB hits -system.cpu.itb.misses 38 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1884772 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5864.888697 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2864.888697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 11053978000 # number of ReadExReq miss cycles +system.cpu.itb.hits 355180514 # ITB hits +system.cpu.itb.misses 34 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884772 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5399662000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884772 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7275516 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5386.307802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2386.307802 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5387207 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10171013500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259543 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1888309 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4506086500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1888309 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363870 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5746.245912 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2753.549345 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2090886500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7276037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5387449 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 363810 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.097532 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459886 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 12488541353 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363870 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1001934000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 363810 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373231721 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363870 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245548 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2245548 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 363810 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245448 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2245448 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.418060 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.417948 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160288 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5625.373932 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5387207 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21224991500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3773081 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9160768 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5387449 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9905748500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.411895 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3773081 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160288 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5625.373932 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 9160768 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5387207 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21224991500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3773081 # number of overall misses +system.cpu.l2cache.overall_hits 5387449 # number of overall hits +system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3773319 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9905748500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411895 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3773081 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -426,32 +426,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2759208 # number of replacements -system.cpu.l2cache.sampled_refs 2783806 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2759426 # number of replacements +system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25817.282629 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6731411 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 140102368000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1195679 # number of writebacks -system.cpu.numCycles 1322739252 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 10423216 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 25902.034995 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6731616 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1195718 # number of writebacks +system.cpu.numCycles 1484618822 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 68342800 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 3385420 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 705442707 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9460872 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 157269 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3423780434 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2645446907 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1985349974 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 515854810 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 75857193 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15148388 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 609147011 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 521 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 744648223 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 20682073 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3556218268 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2749142878 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2059304818 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 535957515 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 93084197 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 30265718 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 683101855 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 33326787 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 60936720 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.timesIdled 4373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index 256a7f3be..11628a59e 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index da44e8643..b38f0f385 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:17:14 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:50 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 48686792e..95f20bb49 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 69139eb9a..0c5d69c2d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1098189 # Simulator instruction rate (inst/s) -host_mem_usage 373972 # Number of bytes of host memory used -host_seconds 1657.07 # Real time elapsed on the host -host_tick_rate 1574114309 # Simulator tick rate (ticks/s) +host_inst_rate 2488083 # Simulator instruction rate (inst/s) +host_mem_usage 200292 # Number of bytes of host memory used +host_seconds 731.40 # Real time elapsed on the host +host_tick_rate 3729826518 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.608424 # Number of seconds simulated -sim_ticks 2608424230000 # Number of ticks simulated +sim_seconds 2.727991 # Number of seconds simulated +sim_ticks 2727990505000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 17373.778213 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14373.778213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 125480619000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 103813377000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.842958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.842958 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 60690301000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 53946895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 19658.571674 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 186170920000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 157760272000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 19658.571674 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 186170920000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470216 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 157760272000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.381693 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40744129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dtb.accesses 611922547 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21654000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 19248000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21654000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19248000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.overall_miss_latency 21654000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19248000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.562745 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 1826378510 # ITB hits system.cpu.itb.misses 18 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 43454360000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 43128979000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22977.351722 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 8236967000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 86583339000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 41409423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 86583339000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3764493 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 41409423000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2751986 # number of replacements system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25389.772813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 574940849000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1194738 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5216848460 # number of cpu cycles simulated +system.cpu.numCycles 5455981010 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 0efe6eafa..660aa118b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index c0a8b63da..7e1135f7a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:59 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:11:35 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index dbf63ca05..3d1cca219 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 4231c8e95..36295ae14 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13021521 # Number of BTB hits -global.BPredUnit.BTBLookups 16952662 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1212 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1950052 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted -global.BPredUnit.lookups 19451761 # Number of BP lookups -global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target. -host_inst_rate 82033 # Simulator instruction rate (inst/s) -host_mem_usage 156240 # Number of bytes of host memory used -host_seconds 1026.17 # Real time elapsed on the host -host_tick_rate 39719192 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10604217 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 13008791 # Number of BTB hits +global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted +global.BPredUnit.lookups 19468548 # Number of BP lookups +global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. +host_inst_rate 157592 # Simulator instruction rate (inst/s) +host_mem_usage 206456 # Number of bytes of host memory used +host_seconds 534.16 # Real time elapsed on the host +host_tick_rate 76416157 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040758 # Number of seconds simulated -sim_ticks 40758469000 # Number of ticks simulated +sim_seconds 0.040819 # Number of seconds simulated +sim_ticks 40818658500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2850471 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73485570 +system.cpu.commit.COM:committed_per_cycle.samples 73457195 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36241200 4931.74% - 1 18077968 2460.07% - 2 7549008 1027.28% - 3 4015107 546.38% - 4 2030060 276.25% - 5 1302937 177.31% - 6 688676 93.72% - 7 730143 99.36% - 8 2850471 387.90% + 0 36278942 4938.79% + 1 18156305 2471.69% + 2 7455514 1014.95% + 3 3880418 528.26% + 4 2046448 278.59% + 5 1301140 177.13% + 6 721823 98.26% + 7 760802 103.57% + 8 2855803 388.77% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1937588 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55772540 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.968368 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads +system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23271115 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9301.109350 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 631 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7925.428784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8046 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13269.627731 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29772218 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 8025.469632 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8677 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2362 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29772218 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 8025.469632 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29763541 # number of overall hits -system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8677 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 29894354 # number of overall hits +system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9171 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2362 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,103 +121,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use -system.cpu.dcache.total_refs 29763775 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use +system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12627 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3048985 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162336287 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39537926 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29896024 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8028470 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189320 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 31783723 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31911121 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 31332689 # DTB hits -system.cpu.dtb.misses 451034 # DTB misses -system.cpu.dtb.read_accesses 24575603 # DTB read accesses +system.cpu.dtb.hits 31454022 # DTB hits +system.cpu.dtb.misses 457099 # DTB misses +system.cpu.dtb.read_accesses 24718123 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24125563 # DTB read hits -system.cpu.dtb.read_misses 450040 # DTB read misses -system.cpu.dtb.write_accesses 7208120 # DTB write accesses +system.cpu.dtb.read_hits 24262026 # DTB read hits +system.cpu.dtb.read_misses 456097 # DTB read misses +system.cpu.dtb.write_accesses 7192998 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7207126 # DTB write hits -system.cpu.dtb.write_misses 994 # DTB write misses -system.cpu.fetch.Branches 19451761 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19219800 # Number of cache lines fetched -system.cpu.fetch.Cycles 50154718 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 536931 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167137455 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2059472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238622 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19219800 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14743121 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.050340 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 7191996 # DTB write hits +system.cpu.dtb.write_misses 1002 # DTB write misses +system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched +system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81514041 +system.cpu.fetch.rateDist.samples 81528342 system.cpu.fetch.rateDist.min_value 0 - 0 50579197 6204.97% - 1 3119637 382.71% - 2 2009848 246.56% - 3 3519871 431.81% - 4 4617609 566.48% - 5 1511564 185.44% - 6 2006119 246.11% - 7 1828029 224.26% - 8 12322167 1511.66% + 0 50560377 6201.57% + 1 3114212 381.98% + 2 2012618 246.86% + 3 3505366 429.96% + 4 4590613 563.07% + 5 1506961 184.84% + 6 2028359 248.79% + 7 1846743 226.52% + 8 12363093 1516.42% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19219800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 6448.716735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000549 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10559 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10102 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1901.528509 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19219800 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 6448.716735 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency -system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000549 # miss rate for demand accesses -system.cpu.icache.demand_misses 10559 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10102 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses +system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19219800 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 6448.716735 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency +system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19209241 # number of overall hits -system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000549 # miss rate for overall accesses -system.cpu.icache.overall_misses 10559 # number of overall misses -system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10102 # number of overall MSHR misses +system.cpu.icache.overall_hits 19218965 # number of overall hits +system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses +system.cpu.icache.overall_misses 11038 # number of overall misses +system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8191 # number of replacements -system.cpu.icache.sampled_refs 10102 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8143 # number of replacements +system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1547.575549 # Cycle average of tags in use -system.cpu.icache.total_refs 19209241 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use +system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2898 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12781978 # Number of branches executed -system.cpu.iew.EXEC:nop 12589139 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.246896 # Inst execution rate -system.cpu.iew.EXEC:refs 31834864 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7209747 # Number of stores executed +system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12812003 # Number of branches executed +system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate +system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7194632 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91092089 # num instructions consuming a value -system.cpu.iew.WB:count 99774116 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721851 # average fanout of values written-back +system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value +system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65754876 # num instructions producing a value -system.cpu.iew.WB:rate 1.223968 # insts written-back per cycle -system.cpu.iew.WB:sent 100649675 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2112266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 284242 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33854360 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1723654 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10604217 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147674740 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24625117 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2113526 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101643128 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 120911 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65837671 # num instructions producing a value +system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle +system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8028470 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 165624 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 844640 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2772 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 223466 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13819947 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4101522 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 223466 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 201477 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1910789 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.032665 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.032665 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 103756654 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued - IntAlu 64328227 62.00% # Type of FU issued - IntMult 474807 0.46% # Type of FU issued + IntAlu 64430040 61.93% # Type of FU issued + IntMult 475055 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2783435 2.68% # Type of FU issued - FloatCmp 115619 0.11% # Type of FU issued - FloatCvt 2381566 2.30% # Type of FU issued - FloatMult 305730 0.29% # Type of FU issued - FloatDiv 755065 0.73% # Type of FU issued - FloatSqrt 322 0.00% # Type of FU issued - MemRead 25279956 24.36% # Type of FU issued - MemWrite 7331920 7.07% # Type of FU issued + FloatAdd 2782164 2.67% # Type of FU issued + FloatCmp 115645 0.11% # Type of FU issued + FloatCvt 2377276 2.29% # Type of FU issued + FloatMult 305748 0.29% # Type of FU issued + FloatDiv 755245 0.73% # Type of FU issued + FloatSqrt 323 0.00% # Type of FU issued + MemRead 25462424 24.48% # Type of FU issued + MemWrite 7324714 7.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1948888 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018783 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 297234 15.25% # attempts to use FU when none available + IntAlu 274346 14.19% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 492 0.03% # attempts to use FU when none available + FloatAdd 31 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 3359 0.17% # attempts to use FU when none available - FloatMult 1274 0.07% # attempts to use FU when none available - FloatDiv 828421 42.51% # attempts to use FU when none available + FloatCvt 6547 0.34% # attempts to use FU when none available + FloatMult 2333 0.12% # attempts to use FU when none available + FloatDiv 832912 43.09% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 745957 38.28% # attempts to use FU when none available - MemWrite 72151 3.70% # attempts to use FU when none available + MemRead 743147 38.44% # attempts to use FU when none available + MemWrite 73812 3.82% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81514041 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35401194 4342.96% - 1 18638593 2286.55% - 2 11850080 1453.75% - 3 6738129 826.62% - 4 5072118 622.24% - 5 2314380 283.92% - 6 1219789 149.64% - 7 213656 26.21% - 8 66102 8.11% + 0 35305774 4330.49% + 1 18904883 2318.81% + 2 11574998 1419.75% + 3 6762756 829.50% + 4 5075415 622.53% + 5 2394533 293.71% + 6 1208963 148.29% + 7 250769 30.76% + 8 50251 6.16% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.272823 # Inst issue rate -system.cpu.iq.iqInstsAdded 135085172 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103756654 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50298713 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 225846 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47102449 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 19219874 # ITB accesses +system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate +system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19230073 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 19219800 # ITB hits -system.cpu.itb.misses 74 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5751.440092 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2751.440092 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9984500 # number of ReadExReq miss cycles +system.cpu.itb.hits 19230003 # ITB hits +system.cpu.itb.misses 70 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4776500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5363.488784 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.488784 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 18171500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8007500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 122 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5704.918033 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2704.918033 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 696000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 122 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 330000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 122 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.154260 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12345 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5494.925839 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 28156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415067 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12784000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415067 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12345 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5494.925839 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7221 # number of overall hits -system.cpu.l2cache.overall_miss_latency 28156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415067 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5124 # number of overall misses +system.cpu.l2cache.overall_hits 7186 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5110 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12784000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415067 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -419,30 +419,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2257.557113 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7206 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81516939 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1780351 # Number of cycles rename is blocking +system.cpu.numCycles 81637318 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1047628 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40793393 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 942240 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202632347 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157116893 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115707927 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28822360 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8028470 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2084695 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47280566 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4772 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 463 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4626500 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed -system.cpu.timesIdled 687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed +system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index 5992f7131..8053728f7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index 20e9ee506..d1a734653 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:27 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:15:05 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 0190cf0fe..0a4a7ae02 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index a1b1d8e71..58a892eca 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1053450 # Simulator instruction rate (inst/s) -host_mem_usage 201692 # Number of bytes of host memory used -host_seconds 87.24 # Real time elapsed on the host -host_tick_rate 1359521857 # Simulator tick rate (ticks/s) +host_inst_rate 1888440 # Simulator instruction rate (inst/s) +host_mem_usage 205224 # Number of bytes of host memory used +host_seconds 48.67 # Real time elapsed on the host +host_tick_rate 2440025498 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118605 # Number of seconds simulated -sim_ticks 118605062000 # Number of ticks simulated +sim_seconds 0.118747 # Number of seconds simulated +sim_ticks 118747191000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2333 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 91903090 # ITB hits system.cpu.itb.misses 47 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4790 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237210124 # number of cpu cycles simulated +system.cpu.numCycles 237494382 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index 26249ed90..337694eda 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index a512928ef..77554b01e 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:15:31 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:25 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index a7e0f9783..cf8698574 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 6a57afc45..40cd826e7 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1517830 # Simulator instruction rate (inst/s) -host_mem_usage 218636 # Number of bytes of host memory used -host_seconds 127.45 # Real time elapsed on the host -host_tick_rate 2121861871 # Simulator tick rate (ticks/s) +host_inst_rate 1409829 # Simulator instruction rate (inst/s) +host_mem_usage 207084 # Number of bytes of host memory used +host_seconds 137.21 # Real time elapsed on the host +host_tick_rate 1971980655 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270428 # Number of seconds simulated -sim_ticks 270428013000 # Number of ticks simulated +sim_seconds 0.270579 # Number of seconds simulated +sim_ticks 270578958000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 29916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 26592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43362000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 89936000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 38544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 85118000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76709902 # number of overall hits -system.cpu.dcache.overall_miss_latency 43362000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 89936000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1606 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 38544000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 85118000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1235.387438 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1235.200907 # Cycle average of tags in use system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 17805.419922 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 14805.419922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 218793000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 181929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 17805.419922 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 218793000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 181929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 17805.419922 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193433499 # number of overall hits -system.cpu.icache.overall_miss_latency 218793000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses system.cpu.icache.overall_misses 12288 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 181929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.780933 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.567399 # Cycle average of tags in use system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 24955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 56420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 11935000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94185000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 45045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 119140000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 269360000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 56980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 207200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.overall_miss_latency 119140000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 269360000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5180 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 56980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 207200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.731325 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.336317 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 540856026 # number of cpu cycles simulated +system.cpu.numCycles 541157916 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index d6124e8ba..047da0c93 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index bac654c3b..88fe50099 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:02:07 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:26 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 270428013000 because target called exit() +122 123 124 Exiting @ tick 270578958000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index f857ba9ca..80cb33a4e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index dd4839763..684f7196b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 665 # Number of BTB hits -global.BPredUnit.BTBLookups 1852 # Number of BTB lookups +global.BPredUnit.BTBHits 649 # Number of BTB hits +global.BPredUnit.BTBLookups 1748 # Number of BTB lookups global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted -global.BPredUnit.lookups 2168 # Number of BP lookups -global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target. -host_inst_rate 54768 # Simulator instruction rate (inst/s) -host_mem_usage 209744 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 47820234 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 112 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted +global.BPredUnit.lookups 2108 # Number of BP lookups +global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target. +host_inst_rate 87257 # Simulator instruction rate (inst/s) +host_mem_usage 198272 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 171219532 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 28 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6297 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5506500 # Number of ticks simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12391500 # Number of ticks simulated system.cpu.commit.COM:branches 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9764 +system.cpu.commit.COM:committed_per_cycle.samples 12114 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7128 7300.29% - 1 1385 1418.48% - 2 452 462.93% - 3 225 230.44% - 4 157 160.79% - 5 102 104.47% - 6 106 108.56% - 7 96 98.32% - 8 113 115.73% + 0 9249 7634.97% + 1 1607 1326.56% + 2 479 395.41% + 3 271 223.71% + 4 137 113.09% + 5 121 99.88% + 6 87 71.82% + 7 43 35.50% + 8 120 99.06% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 1168 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit system.cpu.committedInsts 6297 # Number of Instructions Simulated system.cpu.committedInsts_total 6297 # Number of Instructions Simulated -system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses +system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses -system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses +system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2117 # number of overall hits -system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses -system.cpu.dcache.overall_misses 503 # number of overall misses -system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2058 # number of overall hits +system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses +system.cpu.dcache.overall_misses 542 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,103 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use -system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use +system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2901 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 2892 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2837 # DTB hits -system.cpu.dtb.misses 64 # DTB misses -system.cpu.dtb.read_accesses 1842 # DTB read accesses +system.cpu.dtb.hits 2831 # DTB hits +system.cpu.dtb.misses 61 # DTB misses +system.cpu.dtb.read_accesses 1821 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1799 # DTB read hits -system.cpu.dtb.read_misses 43 # DTB read misses -system.cpu.dtb.write_accesses 1059 # DTB write accesses +system.cpu.dtb.read_hits 1785 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.write_accesses 1071 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1038 # DTB write hits -system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched -system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 1046 # DTB write hits +system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched +system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10556 +system.cpu.fetch.rateDist.samples 12970 system.cpu.fetch.rateDist.min_value 0 - 0 8192 7760.52% - 1 236 223.57% - 2 214 202.73% - 3 172 162.94% - 4 242 229.25% - 5 149 141.15% - 6 203 192.31% - 7 118 111.78% - 8 1030 975.75% + 0 10663 8221.28% + 1 241 185.81% + 2 214 165.00% + 3 169 130.30% + 4 208 160.37% + 5 163 125.67% + 6 215 165.77% + 7 128 98.69% + 8 969 747.11% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency -system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses -system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency +system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1325 # number of overall hits -system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses -system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses +system.cpu.icache.overall_hits 1278 # number of overall hits +system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use -system.cpu.icache.total_refs 1325 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use +system.cpu.icache.total_refs 1278 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1365 # Number of branches executed -system.cpu.iew.EXEC:nop 69 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate -system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1061 # Number of stores executed +system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1375 # Number of branches executed +system.cpu.iew.EXEC:nop 76 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate +system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1073 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5886 # num instructions consuming a value -system.cpu.iew.WB:count 8407 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back +system.cpu.iew.WB:consumers 5878 # num instructions consuming a value +system.cpu.iew.WB:count 8512 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4386 # num instructions producing a value -system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle -system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4396 # num instructions producing a value +system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle +system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6020 66.28% # Type of FU issued + IntAlu 6072 66.72% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1973 21.72% # Type of FU issued - MemWrite 1085 11.95% # Type of FU issued + MemRead 1928 21.18% # Type of FU issued + MemWrite 1096 12.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.93% # attempts to use FU when none available + IntAlu 2 2.15% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 72 67.29% # attempts to use FU when none available - MemWrite 34 31.78% # attempts to use FU when none available + MemRead 56 60.22% # attempts to use FU when none available + MemWrite 35 37.63% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10556 +system.cpu.iq.ISSUE:issued_per_cycle.samples 12970 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6842 6481.62% - 1 1288 1220.16% - 2 888 841.23% - 3 723 684.92% - 4 456 431.98% - 5 198 187.57% - 6 106 100.42% - 7 40 37.89% - 8 15 14.21% + 0 8890 6854.28% + 1 1667 1285.27% + 2 1037 799.54% + 3 696 536.62% + 4 340 262.14% + 5 189 145.72% + 6 103 79.41% + 7 35 26.99% + 8 13 10.02% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate -system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1700 # ITB accesses +system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate +system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1737 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1670 # ITB hits -system.cpu.itb.misses 30 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles +system.cpu.itb.hits 1704 # ITB hits +system.cpu.itb.misses 33 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 480 # number of overall misses +system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 479 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,29 +415,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 11014 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking +system.cpu.numCycles 24784 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 5992f7131..337694eda 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 2c5a26de6..d863a4704 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:48:39 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:49 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5506500 because target called exit() +Exiting @ tick 12391500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 43431aef9..1ee191af5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 22e685732..7935839f7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 65172 # Simulator instruction rate (inst/s) -host_mem_usage 209040 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 208535003 # Simulator tick rate (ticks/s) +host_inst_rate 496189 # Simulator instruction rate (inst/s) +host_mem_usage 197472 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2580329636 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6315 # Number of instructions simulated -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20250000 # Number of ticks simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33503000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1851 # number of overall hits -system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses system.cpu.dcache.overall_misses 179 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6047 # number of overall hits -system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 6326 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -196,29 +196,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses system.cpu.l2cache.overall_misses 443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 40500 # number of cpu cycles simulated +system.cpu.numCycles 67006 # number of cpu cycles simulated system.cpu.num_insts 6315 # Number of instructions executed system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 5992f7131..598fc86c0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a4ec269db..90b25945e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:50:09 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:10:34 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 20250000 because target called exit() +Exiting @ tick 33503000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 2971dacfa..a04865714 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index b9f64c44d..110788930 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 155 # Number of BTB hits -global.BPredUnit.BTBLookups 639 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +global.BPredUnit.BTBHits 198 # Number of BTB hits +global.BPredUnit.BTBLookups 684 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 405 # Number of conditional branches predicted -global.BPredUnit.lookups 821 # Number of BP lookups -global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. -host_inst_rate 39438 # Simulator instruction rate (inst/s) -host_mem_usage 151264 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 44410086 # Simulator tick rate (ticks/s) +global.BPredUnit.condPredicted 447 # Number of conditional branches predicted +global.BPredUnit.lookups 859 # Number of BP lookups +global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +host_inst_rate 67408 # Simulator instruction rate (inst/s) +host_mem_usage 197188 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 201701674 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2700000 # Number of ticks simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7183000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 4866 +system.cpu.commit.COM:committed_per_cycle.samples 6196 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3922 8060.01% - 1 255 524.04% - 2 327 672.01% - 3 133 273.33% - 4 67 137.69% - 5 70 143.86% - 6 33 67.82% - 7 20 41.10% - 8 39 80.15% + 0 5239 8455.46% + 1 263 424.47% + 2 334 539.06% + 3 134 216.27% + 4 73 117.82% + 5 63 101.68% + 6 32 51.65% + 7 20 32.28% + 8 38 61.33% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency -system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses +system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 663 # number of overall hits -system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 674 # number of overall hits +system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses +system.cpu.dcache.overall_misses 193 # number of overall misses +system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use -system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use +system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 936 # DTB accesses +system.cpu.dtb.accesses 971 # DTB accesses system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 911 # DTB hits +system.cpu.dtb.hits 946 # DTB hits system.cpu.dtb.misses 25 # DTB misses -system.cpu.dtb.read_accesses 578 # DTB read accesses +system.cpu.dtb.read_accesses 611 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 567 # DTB read hits +system.cpu.dtb.read_hits 600 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 358 # DTB write accesses +system.cpu.dtb.write_accesses 360 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 344 # DTB write hits +system.cpu.dtb.write_hits 346 # DTB write hits system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 821 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 705 # Number of cache lines fetched -system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle +system.cpu.fetch.Branches 859 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 747 # Number of cache lines fetched +system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 5157 +system.cpu.fetch.rateDist.samples 6528 system.cpu.fetch.rateDist.min_value 0 - 0 4266 8272.25% - 1 34 65.93% - 2 85 164.82% - 3 67 129.92% - 4 115 223.00% - 5 55 106.65% - 6 41 79.50% - 7 48 93.08% - 8 446 864.84% + 0 5595 8570.77% + 1 36 55.15% + 2 100 153.19% + 3 69 105.70% + 4 130 199.14% + 5 72 110.29% + 6 45 68.93% + 7 48 73.53% + 8 433 663.30% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency -system.cpu.icache.demand_hits 500 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses -system.cpu.icache.demand_misses 205 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.demand_hits 512 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses +system.cpu.icache.demand_misses 235 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency +system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 500 # number of overall hits -system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses -system.cpu.icache.overall_misses 205 # number of overall misses -system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.icache.overall_hits 512 # number of overall hits +system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses +system.cpu.icache.overall_misses 235 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use -system.cpu.icache.total_refs 500 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use +system.cpu.icache.total_refs 512 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 542 # Number of branches executed -system.cpu.iew.EXEC:nop 277 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate -system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 358 # Number of stores executed +system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 584 # Number of branches executed +system.cpu.iew.EXEC:nop 286 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate +system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 360 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1788 # num instructions consuming a value -system.cpu.iew.WB:count 3104 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1896 # num instructions consuming a value +system.cpu.iew.WB:count 3311 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1414 # num instructions producing a value -system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle -system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1509 # num instructions producing a value +system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle +system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2327 70.71% # Type of FU issued + IntAlu 2506 71.31% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 599 18.20% # Type of FU issued - MemWrite 364 11.06% # Type of FU issued + MemRead 639 18.18% # Type of FU issued + MemWrite 368 10.47% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.86% # attempts to use FU when none available + IntAlu 1 2.94% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,63 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 34.29% # attempts to use FU when none available - MemWrite 22 62.86% # attempts to use FU when none available + MemRead 11 32.35% # attempts to use FU when none available + MemWrite 22 64.71% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 5157 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3776 7322.09% - 1 540 1047.12% - 2 304 589.49% - 3 226 438.24% - 4 166 321.89% - 5 89 172.58% - 6 40 77.56% - 7 12 23.27% - 8 4 7.76% + 0 5051 7737.44% + 1 569 871.63% + 2 331 507.05% + 3 253 387.56% + 4 172 263.48% + 5 97 148.59% + 6 39 59.74% + 7 11 16.85% + 8 5 7.66% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate -system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate +system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 734 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 776 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 705 # ITB hits +system.cpu.itb.hits 747 # ITB hits system.cpu.itb.misses 29 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -376,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 267 # number of overall misses +system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -414,28 +414,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 5401 # number of cpu cycles simulated +system.cpu.numCycles 14367 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index 298b6fba0..19df33f11 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index abedce50c..c1c2d8a89 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:50 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 2700000 because target called exit() +Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 7d543f47c..d146bb3c1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index c93b1f19c..ae6876b28 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 99969 # Simulator instruction rate (inst/s) -host_mem_usage 193012 # Number of bytes of host memory used +host_inst_rate 96492 # Simulator instruction rate (inst/s) +host_mem_usage 196528 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 383001655 # Simulator tick rate (ticks/s) +host_tick_rate 644436202 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9950000 # Number of ticks simulated +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17374000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses system.cpu.dcache.overall_misses 93 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2586 # ITB hits system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 19900 # number of cpu cycles simulated +system.cpu.numCycles 34748 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index f26dcb93f..bc68d7b07 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d1bbc80b8..97ac18bed 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:24:22 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:25 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 9950000 because target called exit() +Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index e5f76a0a8..fa2de5431 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -226,6 +226,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 @@ -251,7 +252,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index d3bab9d0b..c07fb7a13 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11117 # Simulator instruction rate (inst/s) -host_mem_usage 195308 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host -host_tick_rate 38035865 # Simulator tick rate (ticks/s) +host_inst_rate 142745 # Simulator instruction rate (inst/s) +host_mem_usage 198836 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 810420480 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19359000 # Number of ticks simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32322000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -90,13 +90,13 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -108,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -147,7 +147,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use +system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -162,31 +162,31 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38718 # number of cpu cycles simulated +system.cpu.numCycles 64644 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.tlb.accesses 0 # DTB accesses diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr index 5992f7131..1ad466eb8 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 37be8fb0c..4c9c838f5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:31:07 -M5 started Mon Jul 21 20:31:09 2008 +M5 compiled Aug 2 2008 17:07:38 +M5 started Sat Aug 2 17:07:42 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello World! -Exiting @ tick 19359000 because target called exit() +Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 834e9fbf3..1194cf323 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 132891c92..39cffe2aa 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 56962 # Simulator instruction rate (inst/s) -host_mem_usage 210220 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 184294275 # Simulator tick rate (ticks/s) +host_inst_rate 288337 # Simulator instruction rate (inst/s) +host_mem_usage 198672 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1546587822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17315000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,37 +138,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -180,29 +180,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.numCycles 58062 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr index 2a6ac4135..320065be7 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 9fab97574..85eaa5038 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:56 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:40 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 17315000 because target called exit() +Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index fc5cea346..6c266b8a4 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -413,7 +413,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 28f9f7577..1ece980d2 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 817 # Number of BTB hits -global.BPredUnit.BTBLookups 4239 # Number of BTB lookups -global.BPredUnit.RASInCorrect 150 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1415 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2870 # Number of conditional branches predicted -global.BPredUnit.lookups 4960 # Number of BP lookups -global.BPredUnit.usedRAS 590 # Number of times the RAS was used to get a target. -host_inst_rate 59476 # Simulator instruction rate (inst/s) -host_mem_usage 210328 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 33433367 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 46 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2257 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2354 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1267 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1298 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 849 # Number of BTB hits +global.BPredUnit.BTBLookups 4531 # Number of BTB lookups +global.BPredUnit.RASInCorrect 176 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1493 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2930 # Number of conditional branches predicted +global.BPredUnit.lookups 5203 # Number of BP lookups +global.BPredUnit.usedRAS 663 # Number of times the RAS was used to get a target. +host_inst_rate 79876 # Simulator instruction rate (inst/s) +host_mem_usage 198844 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 88938501 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 48 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2378 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2381 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1292 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1235 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12595 # Number of instructions simulated -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7085500 # Number of ticks simulated +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14042500 # Number of ticks simulated system.cpu.commit.COM:branches 2024 # Number of branches committed system.cpu.commit.COM:branches_0 1012 # Number of branches committed system.cpu.commit.COM:branches_1 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 152 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 138 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 14074 +system.cpu.commit.COM:committed_per_cycle.samples 22161 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 8763 6226.37% - 1 2528 1796.22% - 2 1133 805.03% - 3 504 358.11% - 4 369 262.19% - 5 263 186.87% - 6 218 154.90% - 7 144 102.32% - 8 152 108.00% + 0 16399 7399.94% + 1 2912 1314.02% + 2 1246 562.25% + 3 587 264.88% + 4 387 174.63% + 5 231 104.24% + 6 170 76.71% + 7 91 41.06% + 8 138 62.27% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 12629 # Number of instructions committed -system.cpu.commit.COM:count_0 6314 # Number of instructions committed -system.cpu.commit.COM:count_1 6315 # Number of instructions committed +system.cpu.commit.COM:count_0 6315 # Number of instructions committed +system.cpu.commit.COM:count_1 6314 # Number of instructions committed system.cpu.commit.COM:loads 2336 # Number of loads committed system.cpu.commit.COM:loads_0 1168 # Number of loads committed system.cpu.commit.COM:loads_1 1168 # Number of loads committed @@ -61,133 +61,133 @@ system.cpu.commit.COM:refs_1 2030 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1036 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1089 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9674 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6297 # Number of Instructions Simulated -system.cpu.committedInsts_1 6298 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 10184 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6298 # Number of Instructions Simulated +system.cpu.committedInsts_1 6297 # Number of Instructions Simulated system.cpu.committedInsts_total 12595 # Number of Instructions Simulated -system.cpu.cpi_0 2.250596 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.250238 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.125208 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3671 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3671 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12250.889680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10641.025641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3390 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3390 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3442500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3442500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.076546 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 281 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 281 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 86 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 86 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2075000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2075000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.053119 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 195 # number of ReadReq MSHR misses +system.cpu.cpi_0 4.459511 # CPI: Cycles Per Instruction +system.cpu.cpi_1 4.460219 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.229933 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 35747.734139 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 37101.010101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3422 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3422 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11832500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 11832500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.088196 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 331 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 133 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 7346000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 7346000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052758 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 9093.800979 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8701.149425 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1111 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1111 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5574500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 5574500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.355568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 613 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 613 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 439 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 439 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency_0 33945.394737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36212.643678 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 964 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 964 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25798500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 25798500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.440835 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6301000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 6301000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.379412 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.933140 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5395 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5477 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5477 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 10086.129754 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 34492.208983 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4501 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4501 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4386 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9017000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 37631000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 37631000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.165709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.199197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 894 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1091 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1091 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 525 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 719 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 719 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3589000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3589000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 13647000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 13647000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.068397 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.067920 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 369 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 372 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5395 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5477 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5477 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 10086.129754 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 34492.208983 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4501 # number of overall hits -system.cpu.dcache.overall_hits_0 4501 # number of overall hits +system.cpu.dcache.overall_hits 4386 # number of overall hits +system.cpu.dcache.overall_hits_0 4386 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9017000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 37631000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 37631000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.165709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.199197 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 894 # number of overall misses -system.cpu.dcache.overall_misses_0 894 # number of overall misses +system.cpu.dcache.overall_misses 1091 # number of overall misses +system.cpu.dcache.overall_misses_0 1091 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 525 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 719 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 719 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3589000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3589000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 13647000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 13647000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.068397 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.067920 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 369 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.357154 # Cycle average of tags in use -system.cpu.dcache.total_refs 4549 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 220.225325 # Cycle average of tags in use +system.cpu.dcache.total_refs 4449 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2189 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 393 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 537 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 25750 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 19285 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4519 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1860 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 5942 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 4888 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 421 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 556 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 26407 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32471 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4675 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2005 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 667 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 168 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 6113 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5817 # DTB hits -system.cpu.dtb.misses 125 # DTB misses -system.cpu.dtb.read_accesses 3857 # DTB read accesses +system.cpu.dtb.hits 5960 # DTB hits +system.cpu.dtb.misses 153 # DTB misses +system.cpu.dtb.read_accesses 3958 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3775 # DTB read hits -system.cpu.dtb.read_misses 82 # DTB read misses -system.cpu.dtb.write_accesses 2085 # DTB write accesses +system.cpu.dtb.read_hits 3865 # DTB read hits +system.cpu.dtb.read_misses 93 # DTB read misses +system.cpu.dtb.write_accesses 2155 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2042 # DTB write hits -system.cpu.dtb.write_misses 43 # DTB write misses -system.cpu.fetch.Branches 4960 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3670 # Number of cache lines fetched -system.cpu.fetch.Cycles 8581 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 538 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 28943 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1537 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.349986 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1407 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.042266 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 2095 # DTB write hits +system.cpu.dtb.write_misses 60 # DTB write misses +system.cpu.fetch.Branches 5203 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3861 # Number of cache lines fetched +system.cpu.fetch.Cycles 8930 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 591 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 29621 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.185252 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3861 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1512 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.054654 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 14126 +system.cpu.fetch.rateDist.samples 22207 system.cpu.fetch.rateDist.min_value 0 - 0 9265 6558.83% - 1 397 281.04% - 2 297 210.25% - 3 373 264.05% - 4 393 278.21% - 5 288 203.88% - 6 408 288.83% - 7 267 189.01% - 8 2438 1725.90% + 0 17188 7739.90% + 1 414 186.43% + 2 327 147.25% + 3 389 175.17% + 4 409 184.18% + 5 315 141.85% + 6 447 201.29% + 7 251 113.03% + 8 2467 1110.91% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 10197.443182 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7726.171244 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2966 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7179000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7179000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.191826 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 85 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.168665 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 3861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 36045.289855 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35597.896440 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3033 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 3033 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29845500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 29845500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.214452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 828 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 828 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 210 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 21999500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 21999500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.160062 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 618 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.791599 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.907767 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3670 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3861 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 10197.443182 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 36045.289855 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2966 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2966 # number of demand (read+write) hits +system.cpu.icache.demand_hits 3033 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 3033 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7179000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7179000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 29845500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 29845500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.191826 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.214452 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 704 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses +system.cpu.icache.demand_misses 828 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 828 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 85 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 85 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 210 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21999500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 21999500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.168665 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.160062 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 618 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 618 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3670 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3861 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 10197.443182 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 36045.289855 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2966 # number of overall hits -system.cpu.icache.overall_hits_0 2966 # number of overall hits +system.cpu.icache.overall_hits 3033 # number of overall hits +system.cpu.icache.overall_hits_0 3033 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7179000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7179000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 29845500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 29845500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.191826 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.214452 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 704 # number of overall misses -system.cpu.icache.overall_misses_0 704 # number of overall misses +system.cpu.icache.overall_misses 828 # number of overall misses +system.cpu.icache.overall_misses_0 828 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 85 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 85 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 210 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4782500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4782500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21999500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 21999500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.168665 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.160062 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 618 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.replacements_0 7 # number of replacements +system.cpu.icache.replacements 6 # number of replacements +system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 335.078862 # Cycle average of tags in use -system.cpu.icache.total_refs 2966 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.695837 # Cycle average of tags in use +system.cpu.icache.total_refs 3033 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 46 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2896 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1452 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1444 # Number of branches executed -system.cpu.iew.EXEC:nop 125 # number of nop insts executed +system.cpu.idleCycles 5879 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2965 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1479 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1486 # Number of branches executed +system.cpu.iew.EXEC:nop 135 # number of nop insts executed system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 59 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.282811 # Inst execution rate -system.cpu.iew.EXEC:refs 5961 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2937 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3024 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2102 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1047 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1055 # Number of stores executed +system.cpu.iew.EXEC:nop_1 69 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.661860 # Inst execution rate +system.cpu.iew.EXEC:refs 6137 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 3077 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3060 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2176 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1094 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1082 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11655 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5835 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5820 # num instructions consuming a value -system.cpu.iew.WB:count 17454 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8729 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8725 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.541828 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.770865 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.770962 # average fanout of values written-back +system.cpu.iew.WB:consumers 11623 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5794 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5829 # num instructions consuming a value +system.cpu.iew.WB:count 17865 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8901 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8964 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.541951 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.772351 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.769600 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8985 # num instructions producing a value -system.cpu.iew.WB:producers_0 4498 # num instructions producing a value -system.cpu.iew.WB:producers_1 4487 # num instructions producing a value -system.cpu.iew.WB:rate 1.231583 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.615933 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.615651 # insts written-back per cycle -system.cpu.iew.WB:sent 17676 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 8819 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 8857 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1177 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4611 # Number of dispatched load instructions +system.cpu.iew.WB:producers 8961 # num instructions producing a value +system.cpu.iew.WB:producers_0 4475 # num instructions producing a value +system.cpu.iew.WB:producers_1 4486 # num instructions producing a value +system.cpu.iew.WB:rate 0.636082 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.316919 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.319163 # insts written-back per cycle +system.cpu.iew.WB:sent 18110 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 9029 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 9081 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1169 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4759 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 648 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2565 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 22432 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3859 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1890 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1969 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1127 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18180 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 18 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 598 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2527 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22890 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3961 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1983 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18589 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1860 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2005 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1089 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 405 # Number of stores squashed +system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1210 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 430 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1186 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 436 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 137 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.444327 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.444397 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.888724 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9630 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1213 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 373 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 139 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 999 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 250 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.224240 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.224204 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.448444 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9805 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6491 67.40% # Type of FU issued + IntAlu 6546 66.76% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2024 21.02% # Type of FU issued - MemWrite 1110 11.53% # Type of FU issued + MemRead 2114 21.56% # Type of FU issued + MemWrite 1140 11.63% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 9677 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 9829 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6446 66.61% # Type of FU issued + IntAlu 6612 67.27% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2105 21.75% # Type of FU issued - MemWrite 1121 11.58% # Type of FU issued + MemRead 2096 21.32% # Type of FU issued + MemWrite 1116 11.35% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 19307 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 19634 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 12937 67.01% # Type of FU issued + IntAlu 13158 67.02% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4129 21.39% # Type of FU issued - MemWrite 2231 11.56% # Type of FU issued + MemRead 4210 21.44% # Type of FU issued + MemWrite 2256 11.49% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 191 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009893 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004558 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005335 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 163 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 81 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 82 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008302 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004125 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004176 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 10 5.24% # attempts to use FU when none available + IntAlu 10 6.13% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,163 +543,163 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 116 60.73% # attempts to use FU when none available - MemWrite 65 34.03% # attempts to use FU when none available + MemRead 92 56.44% # attempts to use FU when none available + MemWrite 61 37.42% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 14126 +system.cpu.iq.ISSUE:issued_per_cycle.samples 22207 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6647 4705.51% - 1 2379 1684.13% - 2 1804 1277.08% - 3 1327 939.40% - 4 983 695.88% - 5 624 441.74% - 6 265 187.60% - 7 79 55.93% - 8 18 12.74% + 0 13725 6180.48% + 1 3247 1462.15% + 2 2190 986.18% + 3 1374 618.72% + 4 899 404.83% + 5 454 204.44% + 6 231 104.02% + 7 63 28.37% + 8 24 10.81% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.362334 # Inst issue rate -system.cpu.iq.iqInstsAdded 22262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19307 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.699067 # Inst issue rate +system.cpu.iq.iqInstsAdded 22710 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19634 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8627 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3720 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 5121 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3911 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3670 # ITB hits +system.cpu.itb.hits 3861 # ITB hits system.cpu.itb.misses 50 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6824.137931 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3824.137931 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 989500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 989500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34636.986301 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31585.616438 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 5057000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 554500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 554500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4611500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4611500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6515.413070 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3515.413070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5284000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 5284000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.996314 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2851000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2851000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6344.827586 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3344.827586 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 184000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 184000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 816 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 816 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 34609.950860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31482.800983 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 28172500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 28172500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 814 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 814 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25627000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 814 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34303.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 960500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 960500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 97000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 873000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 873000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6200 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003836 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 5 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 31000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 959 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6562.238494 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 34614.062500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6273500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6273500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 33229500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 33229500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.996872 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 960 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 960 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3405500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3405500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 30238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 30238500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.996872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 960 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 959 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 959 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6562.238494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 34614.062500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_hits_0 3 # number of overall hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_hits_0 2 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6273500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6273500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 33229500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 33229500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.996872 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 956 # number of overall misses -system.cpu.l2cache.overall_misses_0 956 # number of overall misses +system.cpu.l2cache.overall_misses 960 # number of overall misses +system.cpu.l2cache.overall_misses_0 960 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3405500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3405500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 30238500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 30238500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.996872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 960 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -719,34 +719,34 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 786 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 444.416250 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 433.129952 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 14172 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 760 # Number of cycles rename is blocking +system.cpu.numCycles 28086 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2865 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 19739 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 868 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 30813 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 24390 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 18197 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4242 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1860 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 926 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9123 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2524 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 15 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 32955 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1341 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 31504 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 25059 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18781 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4307 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2005 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1387 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9707 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 688 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3332 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 252 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 0ce82a0be..792313cca 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,5 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 1c27475d4..35ba3f4fd 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:49:40 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:13:24 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 7085500 because target called exit() +Exiting @ tick 14042500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 13cb0931f..6ee9f16a8 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index d4ce934cb..f90003dbb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4364 # Number of BTB hits -global.BPredUnit.BTBLookups 10024 # Number of BTB lookups +global.BPredUnit.BTBHits 4398 # Number of BTB hits +global.BPredUnit.BTBLookups 9844 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2911 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 11601 # Number of conditional branches predicted -global.BPredUnit.lookups 11601 # Number of BP lookups +global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted +global.BPredUnit.lookups 11413 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 6832 # Simulator instruction rate (inst/s) -host_mem_usage 210732 # Number of bytes of host memory used -host_seconds 2.11 # Real time elapsed on the host -host_tick_rate 10370738 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads. +host_inst_rate 50656 # Simulator instruction rate (inst/s) +host_mem_usage 199212 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host +host_tick_rate 97240761 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 4977 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3503 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21933500 # Number of ticks simulated +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27756500 # Number of ticks simulated system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 39346 +system.cpu.commit.COM:committed_per_cycle.samples 42766 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 31195 7928.38% - 1 4789 1217.15% - 2 1729 439.43% - 3 717 182.23% - 4 416 105.73% - 5 147 37.36% - 6 198 50.32% - 7 50 12.71% - 8 105 26.69% + 0 34594 8089.14% + 1 4804 1123.32% + 2 1741 407.10% + 3 720 168.36% + 4 413 96.57% + 5 144 33.67% + 6 196 45.83% + 7 51 11.93% + 8 103 24.08% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 2226 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2911 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 20100 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 3.036058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.036058 # CPI: Total CPI of All Threads +system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9408.602151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7113.636364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3751 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 875000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.024194 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.017170 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9957.589286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1218 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2230500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.155340 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 224 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 714000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 33.590604 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9796.529968 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4969 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3105500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.059970 # miss rate for demand accesses -system.cpu.dcache.demand_misses 317 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 149 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1183500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.031782 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses +system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9796.529968 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4969 # number of overall hits -system.cpu.dcache.overall_miss_latency 3105500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.059970 # miss rate for overall accesses -system.cpu.dcache.overall_misses 317 # number of overall misses -system.cpu.dcache.overall_mshr_hits 149 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1183500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.031782 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses +system.cpu.dcache.overall_hits 4728 # number of overall hits +system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses +system.cpu.dcache.overall_misses 558 # number of overall misses +system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 114.768529 # Cycle average of tags in use -system.cpu.dcache.total_refs 5005 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use +system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5414 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 52959 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 18733 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 15067 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4338 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 11601 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 7392 # Number of cache lines fetched -system.cpu.fetch.Cycles 24155 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 764 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 59501 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.264452 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 7392 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 4364 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.356365 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched +system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 43684 +system.cpu.fetch.rateDist.samples 47090 system.cpu.fetch.rateDist.min_value 0 - 0 26944 6167.93% - 1 7490 1714.59% - 2 1209 276.76% - 3 1044 238.99% - 4 1055 241.51% - 5 1191 272.64% - 6 698 159.78% - 7 326 74.63% - 8 3727 853.17% + 0 30448 6465.92% + 1 7532 1599.49% + 2 1217 258.44% + 3 1059 224.89% + 4 1060 225.10% + 5 1193 253.34% + 6 711 150.99% + 7 327 69.44% + 8 3543 752.39% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 7392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8917.690418 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6472.527473 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6985 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3629500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.055060 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 364 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.189560 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7392 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8917.690418 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency -system.cpu.icache.demand_hits 6985 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3629500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.055060 # miss rate for demand accesses -system.cpu.icache.demand_misses 407 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 364 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses +system.cpu.icache.demand_misses 535 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 7392 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8917.690418 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency +system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6985 # number of overall hits -system.cpu.icache.overall_miss_latency 3629500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.055060 # miss rate for overall accesses -system.cpu.icache.overall_misses 407 # number of overall misses -system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2356000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 364 # number of overall MSHR misses +system.cpu.icache.overall_hits 6821 # number of overall hits +system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses +system.cpu.icache.overall_misses 535 # number of overall misses +system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 247.187481 # Cycle average of tags in use -system.cpu.icache.total_refs 6985 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use +system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 184 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4855 # Number of branches executed -system.cpu.iew.EXEC:nop 2093 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.570211 # Inst execution rate -system.cpu.iew.EXEC:refs 6456 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2482 # Number of stores executed +system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4842 # Number of branches executed +system.cpu.iew.EXEC:nop 2091 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate +system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2454 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 13185 # num instructions consuming a value -system.cpu.iew.WB:count 24031 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.826773 # average fanout of values written-back +system.cpu.iew.WB:consumers 13039 # num instructions consuming a value +system.cpu.iew.WB:count 23891 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10901 # num instructions producing a value -system.cpu.iew.WB:rate 0.547802 # insts written-back per cycle -system.cpu.iew.WB:sent 24254 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3206 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4977 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 772 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3503 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 35402 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3974 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4417 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 25014 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 10787 # num instructions producing a value +system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle +system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4338 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 58 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2751 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2055 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 58 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 769 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2437 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.329374 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.329374 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 29431 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 21547 73.21% # Type of FU issued + IntAlu 21395 73.22% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4739 16.10% # Type of FU issued - MemWrite 3145 10.69% # Type of FU issued + MemRead 4720 16.15% # Type of FU issued + MemWrite 3105 10.63% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006388 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 49 26.06% # attempts to use FU when none available + IntAlu 40 23.12% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,96 +296,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 25 13.30% # attempts to use FU when none available - MemWrite 114 60.64% # attempts to use FU when none available + MemRead 20 11.56% # attempts to use FU when none available + MemWrite 113 65.32% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 43684 +system.cpu.iq.ISSUE:issued_per_cycle.samples 47090 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 30754 7040.11% - 1 5431 1243.25% - 2 3052 698.65% - 3 2131 487.82% - 4 1026 234.87% - 5 660 151.09% - 6 361 82.64% - 7 219 50.13% - 8 50 11.45% + 0 34112 7244.00% + 1 5516 1171.37% + 2 3070 651.94% + 3 2146 455.72% + 4 997 211.72% + 5 653 138.67% + 6 342 72.63% + 7 211 44.81% + 8 43 9.13% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.670899 # Inst issue rate -system.cpu.iq.iqInstsAdded 32537 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 29431 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 772 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 16058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 297 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 12535 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate +system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5795.180723 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2795.180723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 481000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 232000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5433.098592 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2433.098592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2314500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990698 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1036500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5578.947368 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2578.947368 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 106000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 49000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009828 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5492.141454 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992203 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 509 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 509 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5492.141454 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2795500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992203 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 509 # number of overall misses +system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 503 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1268500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 509 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,27 +398,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 273.898723 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 43868 # number of cpu cycles simulated +system.cpu.numCycles 55514 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 20565 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 76206 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 43436 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 36362 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13390 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4338 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 306 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 22530 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5085 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 899 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5188 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 833 # count of temporary serializing insts renamed -system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed +system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index eb1796ead..320065be7 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 502cab72d..6ac99b20a 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:53 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:40 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 21933500 because target called exit() +Exiting @ tick 27756500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index d0972f695..1df0c476d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 27bd0c98d..42336245f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 26211 # Simulator instruction rate (inst/s) -host_mem_usage 210104 # Number of bytes of host memory used -host_seconds 0.58 # Real time elapsed on the host -host_tick_rate 52105150 # Simulator tick rate (ticks/s) +host_inst_rate 494493 # Simulator instruction rate (inst/s) +host_mem_usage 198556 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 1381087807 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30178000 # Number of ticks simulated +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 42735000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1431000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2754000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2448000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4185000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3720000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 3513 # number of overall hits -system.cpu.dcache.overall_miss_latency 4185000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses system.cpu.dcache.overall_misses 155 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3720000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.837167 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26907.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6694000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26907.142857 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses system.cpu.icache.demand_misses 280 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6694000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26907.142857 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 14941 # number of overall hits -system.cpu.icache.overall_miss_latency 7534000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses system.cpu.icache.overall_misses 280 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6694000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,37 +140,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 165.376172 # Cycle average of tags in use +system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 935000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7613000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3641000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -182,29 +182,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4576000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses system.cpu.l2cache.overall_misses 416 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4576000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -221,12 +221,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.735043 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 60356 # number of cpu cycles simulated +system.cpu.numCycles 85470 # number of cpu cycles simulated system.cpu.num_insts 15175 # Number of instructions executed system.cpu.num_refs 3684 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr index eb1796ead..320065be7 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index 2511a0e62..8c9e71e76 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:03:20 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:41 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 30178000 because target called exit() +Exiting @ tick 42735000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ecab1a9a6..e57480396 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -411,7 +411,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index df1b8566f..af3c5730d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1110947 # Simulator instruction rate (inst/s) -host_mem_usage 261416 # Number of bytes of host memory used -host_seconds 56.81 # Real time elapsed on the host -host_tick_rate 32921847339 # Simulator tick rate (ticks/s) +host_inst_rate 4441196 # Simulator instruction rate (inst/s) +host_mem_usage 289900 # Number of bytes of host memory used +host_seconds 14.21 # Real time elapsed on the host +host_tick_rate 131610473505 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63114046 # Number of instructions simulated -sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335151500 # Number of ticks simulated +sim_insts 63113507 # Number of instructions simulated +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335522500 # Number of ticks simulated system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits +system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits +system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664339 # number of overall hits +system.cpu0.dcache.overall_hits 12664298 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057379 # number of overall misses +system.cpu0.dcache.overall_misses 2057375 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978971 # number of replacements -system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978967 # number of replacements +system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082956 # DTB hits +system.cpu0.dtb.hits 15082911 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148379 # DTB read hits +system.cpu0.dtb.read_hits 9148351 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934577 # DTB write hits +system.cpu0.dtb.write_hits 5934560 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56305276 # number of overall hits +system.cpu0.icache.overall_hits 56304737 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884863 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884868 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884267 # number of replacements -system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884272 # number of replacements +system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858846 # ITB accesses +system.cpu0.itb.accesses 3858857 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855361 # ITB hits +system.cpu0.itb.hits 3855372 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183273 # number of callpals executed +system.cpu0.kern.callpal 183274 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed @@ -158,7 +158,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # nu system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,43 +168,43 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl +system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1156 -system.cpu0.kern.mode_good_user 1157 +system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1157 +system.cpu0.kern.mode_good_user 1158 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed @@ -239,9 +239,9 @@ system.cpu0.kern.syscall_132 2 0.88% 98.23% # nu system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 3740670191 # number of cpu cycles simulated -system.cpu0.num_insts 57182083 # Number of instructions executed -system.cpu0.num_refs 15322406 # Number of memory references +system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.num_insts 57181549 # Number of instructions executed +system.cpu0.num_refs 15322361 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -255,12 +255,12 @@ system.cpu1.dcache.StoreCondReq_hits 13438 # nu system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -269,10 +269,10 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -284,10 +284,10 @@ system.cpu1.dcache.overall_accesses 1884270 # nu system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812115 # number of overall hits +system.cpu1.dcache.overall_hits 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72155 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 72152 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -303,13 +303,13 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 62341 # number of replacements -system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 62338 # number of replacements +system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30850 # number of writebacks +system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 30848 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations system.cpu1.dtb.hits 1914885 # DTB hits @@ -322,25 +322,25 @@ system.cpu1.dtb.write_accesses 103280 # DT system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -348,14 +348,14 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_hits 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103630 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -371,12 +371,12 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 103097 # number of replacements -system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 103091 # number of replacements +system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.itb.accesses 1469938 # ITB accesses @@ -403,7 +403,7 @@ system.cpu1.kern.callpal_imb 38 0.12% 100.00% # nu system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl @@ -414,8 +414,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl @@ -433,9 +433,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed @@ -456,8 +456,8 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 3740248139 # number of cpu cycles simulated -system.cpu1.num_insts 5931963 # Number of instructions executed +system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.num_insts 5931958 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -525,37 +525,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.435434 # Cycle average of tags in use +system.iocache.tagsinuse 0.435437 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759614 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses +system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759609 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 964534 # number of ReadReq misses system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427643 # number of Writeback hits +system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427641 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.789371 # Average number of references to valid blocks. +system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1759614 # number of demand (read+write) hits +system.l2c.demand_hits 1759609 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270780 # number of demand (read+write) misses +system.l2c.demand_misses 1270778 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1759614 # number of overall hits +system.l2c.overall_hits 1759609 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270780 # number of overall misses +system.l2c.overall_misses 1270778 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056801 # number of replacements -system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks. +system.l2c.replacements 1056800 # number of replacements +system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use -system.l2c.total_refs 1953009 # Total number of references to valid blocks. +system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use +system.l2c.total_refs 1952731 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123879 # number of writebacks +system.l2c.writebacks 123878 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 4e60f8a9d..7d514c2b6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,6 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +Listening for system connection on port 3459 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index a5a0972a1..601a2c3c3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:28:09 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:14 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1870335151500 because m5_exit instruction encountered +Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 4ce652819..e739f3815 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -300,7 +300,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 082e17724..5018c7d30 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1474278 # Simulator instruction rate (inst/s) -host_mem_usage 260680 # Number of bytes of host memory used -host_seconds 40.70 # Real time elapsed on the host -host_tick_rate 44928072322 # Simulator tick rate (ticks/s) +host_inst_rate 3096300 # Simulator instruction rate (inst/s) +host_mem_usage 288712 # Number of bytes of host memory used +host_seconds 19.38 # Real time elapsed on the host +host_tick_rate 94358252114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995479 # Number of instructions simulated -sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355496000 # Number of ticks simulated +sim_insts 59995351 # Number of instructions simulated +sim_seconds 1.828356 # Number of seconds simulated +sim_ticks 1828355695500 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801378 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721676 # number of ReadReq misses +system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552150 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121093 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552150 # number of overall hits +system.cpu.dcache.overall_hits 13552138 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121093 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121104 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042665 # number of replacements -system.cpu.dcache.sampled_refs 2043177 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042676 # number of replacements +system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029602 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428885 # number of writebacks +system.cpu.dcache.writebacks 428892 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053818 # DTB hits +system.cpu.dtb.hits 16053817 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703850 # DTB read hits +system.cpu.dtb.read_hits 9703849 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087262 # number of ReadReq hits +system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920055 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229474 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_hits 59087262 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920055 # number of demand (read+write) misses +system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087262 # number of overall hits +system.cpu.icache.overall_hits 59087131 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920055 # number of overall misses +system.cpu.icache.overall_misses 920058 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919428 # number of replacements -system.cpu.icache.sampled_refs 919940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919431 # number of replacements +system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087262 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use +system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979217 # ITB accesses +system.cpu.itb.accesses 4979228 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974211 # ITB hits +system.cpu.itb.hits 4974222 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192139 # number of callpals executed +system.cpu.kern.callpal 192140 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -157,7 +157,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -167,40 +167,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355288500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087557500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1908 -system.cpu.kern.mode_good_user 1737 +system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1909 +system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1737 # number of protection mode switches +system.cpu.kern.mode_switch_user 1738 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056192000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -234,9 +234,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656710883 # number of cpu cycles simulated -system.cpu.num_insts 59995479 # Number of instructions executed -system.cpu.num_refs 16302129 # Number of memory references +system.cpu.numCycles 3656711283 # number of cpu cycles simulated +system.cpu.num_insts 59995351 # Number of instructions executed +system.cpu.num_refs 16302128 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226223 # Cycle average of tags in use +system.iocache.tagsinuse 1.226225 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696454 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361965 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962420 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696464 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428892 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.726821 # Average number of references to valid blocks. +system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963216 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1696454 # number of demand (read+write) hits +system.l2c.demand_hits 1696464 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427496 # miss rate for demand accesses -system.l2c.demand_misses 1266762 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses +system.l2c.demand_misses 1266766 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963216 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1696454 # number of overall hits +system.l2c.overall_hits 1696464 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427496 # miss rate for overall accesses -system.l2c.overall_misses 1266762 # number of overall misses +system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses +system.l2c.overall_misses 1266766 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050727 # number of replacements -system.l2c.sampled_refs 1081066 # Sample count of references to valid blocks. +system.l2c.replacements 1050731 # number of replacements +system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.986648 # Cycle average of tags in use -system.l2c.total_refs 1866807 # Total number of references to valid blocks. +system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use +system.l2c.total_refs 1866797 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119145 # number of writebacks +system.l2c.writebacks 119150 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 7e35fafed..438bf9f24 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +Listening for system connection on port 3459 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index ac8785088..8a31735d4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:27:46 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:29 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1828355496000 because m5_exit instruction encountered +Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 459187376..2985b82ee 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -405,7 +405,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 85a08a7e2..3478349a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 647923 # Simulator instruction rate (inst/s) -host_mem_usage 252928 # Number of bytes of host memory used -host_seconds 97.63 # Real time elapsed on the host -host_tick_rate 20205445341 # Simulator tick rate (ticks/s) +host_inst_rate 1987058 # Simulator instruction rate (inst/s) +host_mem_usage 287224 # Number of bytes of host memory used +host_seconds 29.88 # Real time elapsed on the host +host_tick_rate 65994111033 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63257216 # Number of instructions simulated -sim_seconds 1.972680 # Number of seconds simulated -sim_ticks 1972679592000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192278 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175522 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 234006000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.087145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16756 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 183738000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.087145 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16756 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 9119152 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941 # average ReadReq mshr miss latency +sim_insts 59379829 # Number of instructions simulated +sim_seconds 1.972135 # Number of seconds simulated +sim_ticks 1972135479000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7426037 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 35981081500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.185666 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1693115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 30901697000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.185666 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1693115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 857399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191314 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 162861 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 759304000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.148724 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28453 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 673945000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.148724 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28453 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5834436 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5455075 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 10223632000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.065021 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379361 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 9085549000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379361 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1211657000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.692591 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14953588 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12881112 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 46204713500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.138594 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2072476 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 39987246000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.138594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 2072476 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14953588 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12881112 # number of overall hits -system.cpu0.dcache.overall_miss_latency 46204713500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.138594 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2072476 # number of overall misses +system.cpu0.dcache.overall_hits 12909668 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417993 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 39987246000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.138594 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 2072476 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2069056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1992967 # number of replacements -system.cpu0.dcache.sampled_refs 1993479 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1338626 # number of replacements +system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.888732 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13341539 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 66395000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403713 # number of writebacks -system.cpu0.dtb.accesses 719861 # DTB accesses +system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 403562 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 15321442 # DTB hits -system.cpu0.dtb.misses 8487 # DTB misses -system.cpu0.dtb.read_accesses 524202 # DTB read accesses +system.cpu0.dtb.hits 14696400 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 9294921 # DTB read hits -system.cpu0.dtb.read_misses 7689 # DTB read misses +system.cpu0.dtb.read_hits 8658591 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6026521 # DTB write hits +system.cpu0.dtb.write_hits 6037809 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57943269 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14213.482115 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11212.730813 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 57028190 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13006459000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.015793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 915079 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10260534500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.015793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 915079 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 62.327526 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57943269 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency -system.cpu0.icache.demand_hits 57028190 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13006459000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015793 # miss rate for demand accesses -system.cpu0.icache.demand_misses 915079 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10260534500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.015793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 915079 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57943269 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 57028190 # number of overall hits -system.cpu0.icache.overall_miss_latency 13006459000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015793 # miss rate for overall accesses -system.cpu0.icache.overall_misses 915079 # number of overall misses +system.cpu0.icache.overall_hits 53208030 # number of overall hits +system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916222 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10260534500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.015793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 915079 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,76 +171,76 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 914464 # number of replacements -system.cpu0.icache.sampled_refs 914976 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 915582 # number of replacements +system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 507.411447 # Cycle average of tags in use -system.cpu0.icache.total_refs 57028190 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 49269353000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use +system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.932800 # Percentage of idle cycles -system.cpu0.itb.accesses 3949472 # ITB accesses +system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles +system.cpu0.itb.accesses 3953623 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3945631 # ITB hits +system.cpu0.itb.hits 3949782 # ITB hits system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187580 # number of callpals executed +system.cpu0.kern.callpal 187998 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 94 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3867 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 171680 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal_rdps 6661 3.55% 97.22% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4704 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202457 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178500 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72488 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1977 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 7 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 103897 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144346 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71119 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1977 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 7 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71112 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972678821000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1900126420500 96.32% 96.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 86973000 0.00% 96.33% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 568583000 0.03% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5546500 0.00% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 71891298000 3.64% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684447 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1228 -system.cpu0.kern.mode_good_user 1229 +system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1232 +system.cpu0.kern.mode_good_user 1233 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7227 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1229 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.169918 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1969223377000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3455442000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3868 # number of times the context was actually changed +system.cpu0.kern.swap_context 3869 # number of times the context was actually changed system.cpu0.kern.syscall 224 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed @@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.067200 # Percentage of non-idle cycles -system.cpu0.numCycles 3945359184 # number of cpu cycles simulated -system.cpu0.num_insts 57934492 # Number of instructions executed -system.cpu0.num_refs 15562811 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12625 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9190.944882 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11609 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 12386000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.080475 # miss rate for LoadLockedReq accesses +system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270958 # number of cpu cycles simulated +system.cpu0.num_insts 54115477 # Number of instructions executed +system.cpu0.num_refs 14937789 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 9338000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.080475 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1030298 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 994091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 505024500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035142 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 36207 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 396399000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035142 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 36207 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 13393500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12560 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 10118 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 55860000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.194427 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2442 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48534000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.194427 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2442 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 657926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 631072 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 708377500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040816 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26854 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 627815500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040816 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26854 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 305665000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.077708 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1688224 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1625163 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 1213402000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037353 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 63061 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1024214500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037353 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 63061 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1688224 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1625163 # number of overall hits -system.cpu1.dcache.overall_miss_latency 1213402000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037353 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 63061 # number of overall misses +system.cpu1.dcache.overall_hits 1608374 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62122 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1024214500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037353 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 63061 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 319058500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 54390 # number of replacements -system.cpu1.dcache.sampled_refs 54808 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 53749 # number of replacements +system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 387.947804 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1648499 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1956976796000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 27227 # number of writebacks +system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26833 # number of writebacks system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1712100 # DTB hits +system.cpu1.dtb.hits 1693796 # DTB hits system.cpu1.dtb.misses 3106 # DTB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1039743 # DTB read hits +system.cpu1.dtb.read_hits 1029675 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 672357 # DTB write hits +system.cpu1.dtb.write_hits 664121 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5325914 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5236056 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1284961500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016872 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 89858 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015347000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016872 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 89858 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 58.288501 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5325914 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5236056 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1284961500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016872 # miss rate for demand accesses -system.cpu1.icache.demand_misses 89858 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015347000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016872 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 89858 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5325914 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5236056 # number of overall hits -system.cpu1.icache.overall_miss_latency 1284961500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016872 # miss rate for overall accesses -system.cpu1.icache.overall_misses 89858 # number of overall misses +system.cpu1.icache.overall_hits 5180112 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87430 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015347000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016872 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 89858 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -439,72 +439,72 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 89318 # number of replacements -system.cpu1.icache.sampled_refs 89830 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 86890 # number of replacements +system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.412997 # Cycle average of tags in use -system.cpu1.icache.total_refs 5236056 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1957297672000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.995045 # Percentage of idle cycles -system.cpu1.itb.accesses 1398451 # ITB accesses +system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.itb.accesses 1397499 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1397205 # ITB hits +system.cpu1.itb.hits 1396253 # ITB hits system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29654 # number of callpals executed +system.cpu1.kern.callpal 29501 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 7 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 369 1.24% 1.28% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24277 81.87% 83.20% # number of callpals executed -system.cpu1.kern.callpal_rdps 2191 7.39% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.62% # number of callpals executed -system.cpu1.kern.callpal_rti 2588 8.73% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed +system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed +system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36198 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2401 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28931 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9254 31.99% 31.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1971 6.81% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 94 0.32% 39.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17612 60.88% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20463 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9246 45.18% 45.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1971 9.63% 54.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 94 0.46% 55.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9152 44.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1972666579000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1919200833000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 508731500 0.03% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 56757500 0.00% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 52900257000 2.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.519646 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 533 -system.cpu1.kern.mode_good_user 515 -system.cpu1.kern.mode_good_idle 18 -system.cpu1.kern.mode_switch_kernel 882 # number of protection mode switches -system.cpu1.kern.mode_switch_user 515 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2077 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.612975 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.604308 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 532 +system.cpu1.kern.mode_good_user 516 +system.cpu1.kern.mode_good_idle 16 +system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches +system.cpu1.kern.mode_switch_user 516 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.008666 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3978131000 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1616488000 0.08% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1966135435000 99.72% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 370 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed @@ -527,10 +527,10 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.004955 # Percentage of non-idle cycles -system.cpu1.numCycles 3945333218 # number of cpu cycles simulated -system.cpu1.num_insts 5322724 # Number of instructions executed -system.cpu1.num_refs 1722033 # Number of memory references +system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles +system.cpu1.numCycles 3943367734 # number of cpu cycles simulated +system.cpu1.num_insts 5264352 # Number of instructions executed +system.cpu1.num_refs 1703685 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -543,58 +543,58 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113562.488636 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61562.488636 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19986998 # number of ReadReq miss cycles +system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 176 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10834998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115053.879621 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63053.711494 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4780718806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2620007820 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4173.944424 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2771 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11566000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41728 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.demand_accesses 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4800705804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41728 # number of demand (read+write) misses +system.iocache.demand_misses 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2630842818 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41728 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.overall_accesses 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4800705804 # number of overall miss cycles +system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41728 # number of overall misses +system.iocache.overall_misses 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2630842818 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -606,83 +606,83 @@ system.iocache.prefetcher.num_hwpf_issued 0 # n system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41696 # number of replacements -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.replacements 41698 # number of replacements +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.554980 # Cycle average of tags in use +system.iocache.tagsinuse 0.582076 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766170681000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 307159 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23004.538366 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11004.538366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7066051000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 307159 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3380143000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 307159 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2746067 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.790348 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782997 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22162928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.350709 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 963070 # number of ReadReq misses +system.l2c.ReadReq_hits 1782800 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307447 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 10605988000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.350705 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 963059 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 779852500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127459 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 22445.817871 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11007.104245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2860921500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127459 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1402954500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127459 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1370781000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430940 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430940 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430395 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.813929 # Average number of references to valid blocks. +system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3053226 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency -system.l2c.demand_hits 1782997 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29228979000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.416028 # miss rate for demand accesses -system.l2c.demand_misses 1270229 # number of demand (read+write) misses +system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.demand_hits 1782800 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses +system.l2c.demand_misses 614243 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13986131000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.416025 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1270218 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3053226 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency +system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782997 # number of overall hits -system.l2c.overall_miss_latency 29228979000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.416028 # miss rate for overall accesses -system.l2c.overall_misses 1270229 # number of overall misses +system.l2c.overall_hits 1782800 # number of overall hits +system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses +system.l2c.overall_misses 614243 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13986131000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.416025 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1270218 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2150633500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1055829 # number of replacements -system.l2c.sampled_refs 1087019 # Sample count of references to valid blocks. +system.l2c.replacements 399043 # number of replacements +system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30866.493853 # Cycle average of tags in use -system.l2c.total_refs 1971775 # Total number of references to valid blocks. -system.l2c.warmup_cycle 7281125000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123132 # number of writebacks +system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use +system.l2c.total_refs 1963771 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123178 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index b0bbb3d67..98c38c0d8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +Listening for system connection on port 3458 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... -warn: 478619000: Trying to launch CPU number 1! +warn: 591544000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 18467c41b..dff43c48d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:27:23 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:07:43 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1972679592000 because m5_exit instruction encountered +Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index c2aeea3f1..6974143c8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -27,6 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memcluster 1, usage 0, start 392, end 16384 freeing pages 1069:16384 reserving pages 1069:1070 + 4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles SMP: 2 CPUs probed -- cpu_present_mask = 3 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 66d96d325..05eb9b89c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -297,7 +297,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index fcddfbde2..7b835d1b3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827411 # Simulator instruction rate (inst/s) -host_mem_usage 316168 # Number of bytes of host memory used -host_seconds 72.58 # Real time elapsed on the host -host_tick_rate 26612603617 # Simulator tick rate (ticks/s) +host_inst_rate 1555255 # Simulator instruction rate (inst/s) +host_mem_usage 285892 # Number of bytes of host memory used +host_seconds 36.11 # Real time elapsed on the host +host_tick_rate 53447376481 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60056349 # Number of instructions simulated -sim_seconds 1.931640 # Number of seconds simulated -sim_ticks 1931639667000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200273 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183016 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 243431000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17257 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191660000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17257 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9530772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712 # average ReadReq mshr miss latency +sim_insts 56165112 # Number of instructions simulated +sim_seconds 1.930166 # Number of seconds simulated +sim_ticks 1930165791000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7805869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36469798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.180983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1724903 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31295044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.180983 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1724903 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 837553000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169292 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 809028000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150362 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29960 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 719148000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150362 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29960 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6154055 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5753421 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10819509500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400634 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9617607500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400634 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1174669000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.859082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15684827 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13559290 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 47289308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135515 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2125537 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 40912651500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.135515 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2125537 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15684827 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13559290 # number of overall hits -system.cpu.dcache.overall_miss_latency 47289308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135515 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2125537 # number of overall misses +system.cpu.dcache.overall_hits 13569826 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471004 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 40912651500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.135515 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2125537 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2012222000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2046082 # number of replacements -system.cpu.dcache.sampled_refs 2046594 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1391586 # number of replacements +system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.986722 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037756 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66420000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430195 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses +system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430461 # number of writebacks +system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16064922 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.hits 15421361 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9711464 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.read_hits 9063577 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6353458 # DTB write hits +system.cpu.dtb.write_hits 6357784 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60068188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 929129 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency -system.cpu.icache.demand_hits 59139059 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accesses -system.cpu.icache.demand_misses 929129 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses +system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency +system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59139059 # number of overall hits -system.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accesses -system.cpu.icache.overall_misses 929129 # number of overall misses +system.cpu.icache.overall_hits 55246023 # number of overall hits +system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses +system.cpu.icache.overall_misses 930923 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 928458 # number of replacements -system.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930251 # number of replacements +system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in use -system.cpu.icache.total_refs 59139059 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use +system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929252 # Percentage of idle cycles -system.cpu.itb.accesses 4979997 # ITB accesses +system.cpu.idle_fraction 0.929251 # Percentage of idle cycles +system.cpu.itb.accesses 4982832 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974991 # ITB hits -system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192947 # number of callpals executed +system.cpu.itb.hits 4977822 # ITB hits +system.cpu.itb.misses 5010 # ITB misses +system.cpu.kern.callpal 193204 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed +system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183224 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1905 -system.cpu.kern.mode_good_user 1736 -system.cpu.kern.mode_good_idle 169 -system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2093 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1743 +system.cpu.kern.mode_good_idle 167 +system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches +system.cpu.kern.mode_switch_user 1743 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4172 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070748 # Percentage of non-idle cycles -system.cpu.numCycles 3863279334 # number of cpu cycles simulated -system.cpu.num_insts 60056349 # Number of instructions executed -system.cpu.num_refs 16313052 # Number of memory references +system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles +system.cpu.numCycles 3860331582 # number of cpu cycles simulated +system.cpu.num_insts 56165112 # Number of instructions executed +system.cpu.num_refs 15669461 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -284,55 +284,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113566.462428 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61566.462428 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19646998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10650998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115104.611234 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63104.539180 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4782826806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2622119812 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4196.454414 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2764 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11599000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4802473804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2632770810 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4802473804 # number of overall miss cycles +system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2632770810 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.333347 # Cycle average of tags in use +system.iocache.tagsinuse 1.353410 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766149259000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23005.373872 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7003664000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304436 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3350432000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304436 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2671270 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.722595 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1708534 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22155176500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.360404 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962736 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 10602344500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.360404 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 962736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126158 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 23005.275131 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2902299500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1710772 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307605 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126158 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1388610500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126158 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1061281000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430195 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430195 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430461 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.743066 # Average number of references to valid blocks. +system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2975706 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency -system.l2c.demand_hits 1708534 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29158840500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.425839 # miss rate for demand accesses -system.l2c.demand_misses 1267172 # number of demand (read+write) misses +system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.demand_hits 1710772 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses +system.l2c.demand_misses 612230 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13952776500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.425839 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1267172 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2975706 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency +system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1708534 # number of overall hits -system.l2c.overall_miss_latency 29158840500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.425839 # miss rate for overall accesses -system.l2c.overall_misses 1267172 # number of overall misses +system.l2c.overall_hits 1710772 # number of overall hits +system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses +system.l2c.overall_misses 612230 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13952776500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.425839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1267172 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1811383000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050085 # number of replacements -system.l2c.sampled_refs 1081030 # Sample count of references to valid blocks. +system.l2c.replacements 394925 # number of replacements +system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30869.828292 # Cycle average of tags in use -system.l2c.total_refs 1884307 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5029142000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 118653 # number of writebacks +system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use +system.l2c.total_refs 1889516 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119047 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 408213e67..3aab2bec2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +Listening for system connection on port 3458 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index a429ac712..4d30d3925 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:28:11 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:13 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1931639667000 because m5_exit instruction encountered +Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 7930e9e46..3efa225a8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,6 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memcluster 1, usage 0, start 392, end 16384 freeing pages 1069:16384 reserving pages 1069:1070 + 4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles SMP: 1 CPUs probed -- cpu_present_mask = 1 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index ddf7f50b2..3d8212f3f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -163,6 +163,7 @@ type=ExeTracer [system.cpu.workload] type=EioProcess chkpt= +errout=cerr file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 @@ -182,7 +183,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index f4cb30fc4..e8282d216 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 922979 # Simulator instruction rate (inst/s) -host_mem_usage 193036 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host -host_tick_rate 1305530646 # Simulator tick rate (ticks/s) +host_inst_rate 1672362 # Simulator instruction rate (inst/s) +host_mem_usage 196544 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 2464131877 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000708 # Number of seconds simulated -sim_ticks 707548000 # Number of ticks simulated +sim_seconds 0.000737 # Number of seconds simulated +sim_ticks 737389000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 8505000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 7560000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7464000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16902000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 15024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180149 # number of overall hits -system.cpu.dcache.overall_miss_latency 16902000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses system.cpu.dcache.overall_misses 626 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 15024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 289.353429 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 56340 # DTB write hits system.cpu.dtb.write_misses 10 # DTB write misses system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10881000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 9672000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10881000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9672000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499617 # number of overall hits -system.cpu.icache.overall_miss_latency 10881000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9672000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 266.476324 # Cycle average of tags in use +system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 500020 # ITB hits system.cpu.itb.misses 13 # ITB misses system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3197000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1529000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 16514000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7898000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3956000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 373.323140 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1415096 # number of cpu cycles simulated +system.cpu.numCycles 1474778 # number of cpu cycles simulated system.cpu.num_insts 500001 # Number of instructions executed system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr index 9e24842c0..cc0a07c09 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 3f3a9bccf..46fb8222f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:18:02 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:10:34 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second main dictionary has 1245 entries 49508 bytes wasted ->Exiting @ tick 707548000 because a thread reached the max instruction count +>Exiting @ tick 737389000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 1a7e3807d..ce3301742 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -428,7 +428,7 @@ mem_side=system.toL2Bus.port[8] [system.funcmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 @@ -484,7 +484,7 @@ port=system.l2c.mem_side system.physmem.port[0] [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index f7b90230a..c4e841ee5 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 323140 # Number of bytes of host memory used -host_seconds 197.60 # Real time elapsed on the host -host_tick_rate 574221 # Simulator tick rate (ticks/s) +host_mem_usage 323512 # Number of bytes of host memory used +host_seconds 193.82 # Real time elapsed on the host +host_tick_rate 1387453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113467820 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 16813.519915 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15809.702810 # average ReadReq mshr miss latency +sim_seconds 0.000269 # Number of seconds simulated +sim_ticks 268915439 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7364 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 627699139 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.835246 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37333 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 590223635 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835246 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37333 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 316695188 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24294 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 20338.524830 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19334.650285 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 955 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 474680831 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.960690 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23339 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 451251403 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.960690 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23339 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 201005657 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1600.079607 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.402132 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 70069 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 112115978 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 68991 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 18169.501088 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8319 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 1102379970 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.879419 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60672 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 1041475038 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.879419 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60672 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 68991 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 18169.501088 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8319 # number of overall hits -system.cpu0.l1c.overall_miss_latency 1102379970 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.879419 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60672 # number of overall misses +system.cpu0.l1c.overall_hits 8674 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60767 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 1041475038 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.879419 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60672 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 517700845 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 27892 # number of replacements -system.cpu0.l1c.sampled_refs 28232 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 28158 # number of replacements +system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 346.353469 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11353 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11056 # number of writebacks +system.cpu0.l1c.writebacks 11054 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99413 # number of read accesses completed -system.cpu0.num_writes 54273 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44637 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 16885.597031 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15881.726361 # average ReadReq mshr miss latency +system.cpu0.num_reads 99578 # number of read accesses completed +system.cpu0.num_writes 53795 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7453 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 627874040 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.833031 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37184 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 590546113 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833031 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37184 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 318748024 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24256 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 20197.502675 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19193.799580 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 895 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 471833860 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.963102 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23361 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 448386352 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.963102 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23361 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 199243328 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1599.721775 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.408930 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69990 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 111964527 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68893 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 18163.480056 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8348 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 1099707900 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.878827 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60545 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 1038932465 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.878827 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60545 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68893 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 18163.480056 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8348 # number of overall hits -system.cpu1.l1c.overall_miss_latency 1099707900 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.878827 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60545 # number of overall misses +system.cpu1.l1c.overall_hits 8551 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60450 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 1038932465 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.878827 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60545 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 517991352 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27678 # number of replacements -system.cpu1.l1c.sampled_refs 28017 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27563 # number of replacements +system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 343.577416 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11457 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10919 # number of writebacks +system.cpu1.l1c.writebacks 10923 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99570 # number of read accesses completed -system.cpu1.num_writes 53662 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44913 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 16880.348216 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15876.450165 # average ReadReq mshr miss latency +system.cpu1.num_reads 99680 # number of read accesses completed +system.cpu1.num_writes 54175 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7600 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 629856433 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.830784 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37313 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 592397985 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830784 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37313 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 314233420 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24350 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 20273.649648 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19269.817033 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 925 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 474910243 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.962012 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23425 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 451395464 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.962012 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23425 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 201676231 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1601.319797 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.408037 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 70035 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 112148432 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69263 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 18189.052587 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8525 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 1104766676 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.876918 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60738 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 1043793449 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.876918 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60738 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69263 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 18189.052587 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8525 # number of overall hits -system.cpu2.l1c.overall_miss_latency 1104766676 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.876918 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60738 # number of overall misses +system.cpu2.l1c.overall_hits 8437 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60562 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 1043793449 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.876918 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60738 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 515909651 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27950 # number of replacements -system.cpu2.l1c.sampled_refs 28294 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27725 # number of replacements +system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.355959 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11545 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10956 # number of writebacks +system.cpu2.l1c.writebacks 10868 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99987 # number of read accesses completed -system.cpu2.num_writes 53946 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44879 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 16871.980218 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 15868.081622 # average ReadReq mshr miss latency +system.cpu2.num_reads 99153 # number of read accesses completed +system.cpu2.num_writes 52976 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7573 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 629426094 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.831257 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37306 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 591974653 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.831257 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37306 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 315451568 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24230 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 20326.119616 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 19322.374206 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 922 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 473761196 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.961948 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23308 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 450365898 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961948 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23308 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 202979355 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1601.528078 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.416658 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69967 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 112054115 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69109 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 18200.206058 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8495 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 1103187290 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.877078 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60614 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 1042340551 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.877078 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60614 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69109 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 18200.206058 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8495 # number of overall hits -system.cpu3.l1c.overall_miss_latency 1103187290 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.877078 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60614 # number of overall misses +system.cpu3.l1c.overall_hits 8535 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60533 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 1042340551 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.877078 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60614 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 518430923 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 27588 # number of replacements +system.cpu3.l1c.replacements 27562 # number of replacements system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 346.019907 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11631 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10783 # number of writebacks +system.cpu3.l1c.writebacks 10850 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99559 # number of read accesses completed -system.cpu3.num_writes 53870 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44804 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 16848.729876 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 15844.831650 # average ReadReq mshr miss latency +system.cpu3.num_reads 99282 # number of read accesses completed +system.cpu3.num_writes 53764 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7584 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 627109726 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.830729 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37220 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 589744634 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.830729 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37220 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 313232793 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24193 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 20495.832426 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 19492.129507 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 866 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 478106283 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.964205 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23327 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 454692905 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.964205 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23327 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 192427965 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1603.347065 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.413043 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69889 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 112056323 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68997 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 18253.852528 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8450 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 1105216009 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877531 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60547 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 1044437539 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877531 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60547 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68997 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 18253.852528 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8450 # number of overall hits -system.cpu4.l1c.overall_miss_latency 1105216009 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877531 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60547 # number of overall misses +system.cpu4.l1c.overall_hits 8435 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60418 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 1044437539 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877531 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60547 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 505660758 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 27638 # number of replacements -system.cpu4.l1c.sampled_refs 27985 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27721 # number of replacements +system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 346.668579 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11559 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10780 # number of writebacks +system.cpu4.l1c.writebacks 10846 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99517 # number of read accesses completed -system.cpu4.num_writes 53554 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 45330 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 16742.272952 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15738.453990 # average ReadReq mshr miss latency +system.cpu4.num_reads 99301 # number of read accesses completed +system.cpu4.num_writes 53586 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7653 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 630798618 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.831171 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37677 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 592977731 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831171 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37677 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 317163872 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24208 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 20252.552363 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19248.677491 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 928 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 471479419 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.961666 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23280 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 448109212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961666 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23280 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 202581548 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1592.994331 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413221 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 70383 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 112119720 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69538 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 18082.878701 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8581 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 1102278037 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.876600 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60957 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 1041086943 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.876600 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60957 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 69538 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 18082.878701 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8581 # number of overall hits -system.cpu5.l1c.overall_miss_latency 1102278037 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.876600 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60957 # number of overall misses +system.cpu5.l1c.overall_hits 8362 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60470 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 1041086943 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.876600 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60957 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 519745420 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 28012 # number of replacements -system.cpu5.l1c.sampled_refs 28365 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27632 # number of replacements +system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 347.429877 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11721 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10901 # number of writebacks +system.cpu5.l1c.writebacks 10950 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53842 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45124 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 16852.177623 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15848.333619 # average ReadReq mshr miss latency +system.cpu5.num_reads 99024 # number of read accesses completed +system.cpu5.num_writes 53903 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7719 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 630355704 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.828938 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 592806919 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.828938 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 313955648 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24360 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 20279.291722 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19275.372628 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 913 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 475488553 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962521 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23447 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 451949662 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962521 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23447 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 198611435 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1598.405866 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.418615 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 70240 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 112272028 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69484 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 18172.685483 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8632 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 1105844257 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.875770 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60852 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 1044756581 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.875770 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60852 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 69484 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 18172.685483 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8632 # number of overall hits -system.cpu6.l1c.overall_miss_latency 1105844257 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.875770 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60852 # number of overall misses +system.cpu6.l1c.overall_hits 8396 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60973 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 1044756581 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.875770 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60852 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 512567083 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 27959 # number of replacements -system.cpu6.l1c.sampled_refs 28310 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 28139 # number of replacements +system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 344.892132 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11851 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11044 # number of writebacks +system.cpu6.l1c.writebacks 11130 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99626 # number of read accesses completed -system.cpu6.num_writes 53905 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44909 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 16826.619219 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15822.802503 # average ReadReq mshr miss latency +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 54239 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7759 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 625108904 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.827228 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37150 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 587817113 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.827228 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37150 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 317908383 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24427 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 20228.908213 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 19225.075071 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 916 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 475601861 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.962501 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23511 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 452000740 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962501 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23511 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 197920310 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1598.930420 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.421584 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 70034 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 111979493 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69336 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 18145.278927 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8675 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 1100710765 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.874885 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60661 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 1039817853 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.874885 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60661 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 69336 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 18145.278927 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8675 # number of overall hits -system.cpu7.l1c.overall_miss_latency 1100710765 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.874885 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60661 # number of overall misses +system.cpu7.l1c.overall_hits 8481 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60440 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 1039817853 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.874885 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60661 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 515828693 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -628,88 +628,88 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27690 # number of replacements -system.cpu7.l1c.sampled_refs 28049 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27627 # number of replacements +system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 343.299146 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11825 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10985 # number of writebacks +system.cpu7.l1c.writebacks 10984 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99331 # number of read accesses completed -system.cpu7.num_writes 53962 # number of write accesses completed -system.l2c.ReadExReq_accesses 75034 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 19990.930951 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10006.831093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 1499999513 # number of ReadExReq miss cycles +system.cpu7.num_reads 99634 # number of read accesses completed +system.cpu7.num_writes 53744 # number of write accesses completed +system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 75034 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 354 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 747310146 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.995282 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74680 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 139261 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 19959.179983 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10007.689712 # average ReadReq mshr miss latency +system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 91062 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 962012516 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.346106 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 48199 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 611 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 476245938 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.341718 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 47588 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 793404880 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18516 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11019.424390 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 10007.005085 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 204035662 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 89906 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 48016 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18516 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 184989496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 0.998380 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18486 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 430707040 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86799 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 86799 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs 2909.833333 # average number of cycles each access was blocked +system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 86929 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.988478 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked +system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 17459 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 214295 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 19978.512484 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency -system.l2c.demand_hits 91062 # number of demand (read+write) hits -system.l2c.demand_miss_latency 2462012029 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.575062 # miss rate for demand accesses -system.l2c.demand_misses 123233 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 965 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 1223556084 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.570559 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 122268 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 213064 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.demand_hits 89906 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses +system.l2c.demand_misses 123158 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 214295 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 19978.512484 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency +system.l2c.overall_accesses 213064 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 91062 # number of overall hits -system.l2c.overall_miss_latency 2462012029 # number of overall miss cycles -system.l2c.overall_miss_rate 0.575062 # miss rate for overall accesses -system.l2c.overall_misses 123233 # number of overall misses -system.l2c.overall_mshr_hits 965 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 1223556084 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.570559 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 122268 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1224111920 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 89906 # number of overall hits +system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles +system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses +system.l2c.overall_misses 123158 # number of overall misses +system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -720,12 +720,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 74376 # number of replacements -system.l2c.sampled_refs 74986 # Sample count of references to valid blocks. +system.l2c.replacements 73303 # number of replacements +system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.319008 # Cycle average of tags in use -system.l2c.total_refs 149108 # Total number of references to valid blocks. +system.l2c.tagsinuse 633.737828 # Cycle average of tags in use +system.l2c.total_refs 148204 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 47583 # number of writebacks +system.l2c.writebacks 47216 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index f89b5d5ce..a93b081cc 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @10889862 -system.cpu6: completed 10000 read accesses @10965571 -system.cpu0: completed 10000 read accesses @10999807 -system.cpu1: completed 10000 read accesses @11061066 -system.cpu3: completed 10000 read accesses @11070068 -system.cpu5: completed 10000 read accesses @11143240 -system.cpu7: completed 10000 read accesses @11205415 -system.cpu4: completed 10000 read accesses @11436114 -system.cpu5: completed 20000 read accesses @22318031 -system.cpu2: completed 20000 read accesses @22337080 -system.cpu0: completed 20000 read accesses @22381736 -system.cpu6: completed 20000 read accesses @22509672 -system.cpu1: completed 20000 read accesses @22762640 -system.cpu7: completed 20000 read accesses @22874302 -system.cpu3: completed 20000 read accesses @22934916 -system.cpu4: completed 20000 read accesses @22955693 -system.cpu2: completed 30000 read accesses @33671766 -system.cpu5: completed 30000 read accesses @33722420 -system.cpu0: completed 30000 read accesses @33817843 -system.cpu1: completed 30000 read accesses @34138032 -system.cpu3: completed 30000 read accesses @34173736 -system.cpu6: completed 30000 read accesses @34210820 -system.cpu7: completed 30000 read accesses @34282426 -system.cpu4: completed 30000 read accesses @34509982 -system.cpu2: completed 40000 read accesses @45029426 -system.cpu5: completed 40000 read accesses @45134036 -system.cpu0: completed 40000 read accesses @45316016 -system.cpu3: completed 40000 read accesses @45518533 -system.cpu6: completed 40000 read accesses @45639311 -system.cpu1: completed 40000 read accesses @45681507 -system.cpu7: completed 40000 read accesses @45794833 -system.cpu4: completed 40000 read accesses @46027115 -system.cpu2: completed 50000 read accesses @56302892 -system.cpu5: completed 50000 read accesses @56333031 -system.cpu3: completed 50000 read accesses @56769550 -system.cpu0: completed 50000 read accesses @56860279 -system.cpu1: completed 50000 read accesses @56989965 -system.cpu7: completed 50000 read accesses @57056302 -system.cpu6: completed 50000 read accesses @57079409 -system.cpu4: completed 50000 read accesses @57116196 -system.cpu2: completed 60000 read accesses @67583365 -system.cpu5: completed 60000 read accesses @67785565 -system.cpu3: completed 60000 read accesses @68057386 -system.cpu0: completed 60000 read accesses @68158806 -system.cpu4: completed 60000 read accesses @68296537 -system.cpu6: completed 60000 read accesses @68386914 -system.cpu7: completed 60000 read accesses @68429516 -system.cpu1: completed 60000 read accesses @68460666 -system.cpu2: completed 70000 read accesses @79111322 -system.cpu5: completed 70000 read accesses @79209430 -system.cpu4: completed 70000 read accesses @79635720 -system.cpu0: completed 70000 read accesses @79745526 -system.cpu3: completed 70000 read accesses @79788385 -system.cpu1: completed 70000 read accesses @79799686 -system.cpu7: completed 70000 read accesses @79866566 -system.cpu6: completed 70000 read accesses @79989630 -system.cpu5: completed 80000 read accesses @90523593 -system.cpu2: completed 80000 read accesses @90753657 -system.cpu4: completed 80000 read accesses @91052610 -system.cpu6: completed 80000 read accesses @91127936 -system.cpu0: completed 80000 read accesses @91167181 -system.cpu1: completed 80000 read accesses @91235432 -system.cpu3: completed 80000 read accesses @91277914 -system.cpu7: completed 80000 read accesses @91382669 -system.cpu2: completed 90000 read accesses @101882254 -system.cpu5: completed 90000 read accesses @101888287 -system.cpu1: completed 90000 read accesses @102242250 -system.cpu4: completed 90000 read accesses @102331682 -system.cpu6: completed 90000 read accesses @102446126 -system.cpu3: completed 90000 read accesses @102480895 -system.cpu0: completed 90000 read accesses @102517256 -system.cpu7: completed 90000 read accesses @102831150 -system.cpu5: completed 100000 read accesses @113467820 +system.cpu3: completed 10000 read accesses @26226880 +system.cpu6: completed 10000 read accesses @26416342 +system.cpu2: completed 10000 read accesses @26427251 +system.cpu5: completed 10000 read accesses @26798889 +system.cpu0: completed 10000 read accesses @26886521 +system.cpu7: completed 10000 read accesses @27109446 +system.cpu1: completed 10000 read accesses @27197408 +system.cpu4: completed 10000 read accesses @27318359 +system.cpu3: completed 20000 read accesses @53279230 +system.cpu6: completed 20000 read accesses @53417084 +system.cpu2: completed 20000 read accesses @53757092 +system.cpu0: completed 20000 read accesses @53888320 +system.cpu5: completed 20000 read accesses @53947132 +system.cpu4: completed 20000 read accesses @54390092 +system.cpu1: completed 20000 read accesses @54397720 +system.cpu7: completed 20000 read accesses @54632966 +system.cpu6: completed 30000 read accesses @80144176 +system.cpu3: completed 30000 read accesses @80518264 +system.cpu0: completed 30000 read accesses @80638600 +system.cpu5: completed 30000 read accesses @80869702 +system.cpu1: completed 30000 read accesses @81289158 +system.cpu2: completed 30000 read accesses @81358716 +system.cpu7: completed 30000 read accesses @81981296 +system.cpu4: completed 30000 read accesses @82043104 +system.cpu6: completed 40000 read accesses @107087547 +system.cpu0: completed 40000 read accesses @107662142 +system.cpu3: completed 40000 read accesses @107722516 +system.cpu5: completed 40000 read accesses @107884124 +system.cpu1: completed 40000 read accesses @107981413 +system.cpu7: completed 40000 read accesses @108415286 +system.cpu2: completed 40000 read accesses @108655120 +system.cpu4: completed 40000 read accesses @109427858 +system.cpu6: completed 50000 read accesses @133583246 +system.cpu0: completed 50000 read accesses @133832383 +system.cpu5: completed 50000 read accesses @134755386 +system.cpu1: completed 50000 read accesses @134792594 +system.cpu7: completed 50000 read accesses @134914312 +system.cpu3: completed 50000 read accesses @134993978 +system.cpu2: completed 50000 read accesses @135362549 +system.cpu4: completed 50000 read accesses @135394370 +system.cpu0: completed 60000 read accesses @160410176 +system.cpu6: completed 60000 read accesses @160667590 +system.cpu7: completed 60000 read accesses @161466346 +system.cpu1: completed 60000 read accesses @161592434 +system.cpu5: completed 60000 read accesses @161656374 +system.cpu4: completed 60000 read accesses @161882626 +system.cpu2: completed 60000 read accesses @162062631 +system.cpu3: completed 60000 read accesses @162154299 +system.cpu6: completed 70000 read accesses @187592265 +system.cpu1: completed 70000 read accesses @188138542 +system.cpu7: completed 70000 read accesses @188373105 +system.cpu0: completed 70000 read accesses @188690782 +system.cpu3: completed 70000 read accesses @189309687 +system.cpu2: completed 70000 read accesses @189360790 +system.cpu4: completed 70000 read accesses @189391126 +system.cpu5: completed 70000 read accesses @189902895 +system.cpu6: completed 80000 read accesses @214739574 +system.cpu1: completed 80000 read accesses @215665444 +system.cpu0: completed 80000 read accesses @216021457 +system.cpu7: completed 80000 read accesses @216394344 +system.cpu3: completed 80000 read accesses @216537382 +system.cpu4: completed 80000 read accesses @216775798 +system.cpu2: completed 80000 read accesses @216868662 +system.cpu5: completed 80000 read accesses @217401619 +system.cpu6: completed 90000 read accesses @241415090 +system.cpu1: completed 90000 read accesses @242558992 +system.cpu0: completed 90000 read accesses @242897388 +system.cpu7: completed 90000 read accesses @243372191 +system.cpu3: completed 90000 read accesses @243630762 +system.cpu5: completed 90000 read accesses @243633950 +system.cpu4: completed 90000 read accesses @243710816 +system.cpu2: completed 90000 read accesses @243974160 +system.cpu6: completed 100000 read accesses @268915439 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index d0d9bd67d..7382eca3b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:18:03 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:20 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second -Exiting @ tick 113467820 because maximum number of loads reached +Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 5ae2e325d..4a385ded6 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/binkertn/regress/m5/configs/boot/netperf-server.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -156,7 +156,7 @@ pio=drivesys.membus.default [drivesys.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 @@ -698,7 +698,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/binkertn/regress/m5/configs/boot/netperf-stream-client.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -840,7 +840,7 @@ pio=testsys.membus.default [testsys.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 03c1ec15e..6315d7b3d 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -39,8 +39,8 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl @@ -59,8 +59,8 @@ drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # f drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -76,7 +76,7 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 199572412849 # number of cpu cycles simulated +drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -139,76 +139,76 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 222632706 # Simulator instruction rate (inst/s) -host_mem_usage 479796 # Number of bytes of host memory used -host_seconds 1.23 # Real time elapsed on the host -host_tick_rate 162907421274 # Simulator tick rate (ticks/s) +host_inst_rate 162488534 # Simulator instruction rate (inst/s) +host_mem_usage 477336 # Number of bytes of host memory used +host_seconds 1.68 # Real time elapsed on the host +host_tick_rate 118897556170 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294782 # Number of instructions simulated +sim_insts 273294177 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163322 # DTB hits +testsys.cpu.dtb.hits 1163288 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658456 # DTB read hits +testsys.cpu.dtb.read_hits 658435 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504866 # DTB write hits +testsys.cpu.dtb.write_hits 504853 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249851 # ITB accesses +testsys.cpu.itb.accesses 1249822 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248354 # ITB hits +testsys.cpu.itb.hits 1248325 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13125 # number of callpals executed +testsys.cpu.kern.callpal 13122 # number of callpals executed testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed -testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed +testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 655 -testsys.cpu.kern.mode_good_user 650 +testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 654 +testsys.cpu.kern.mode_good_user 649 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -233,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 199570420361 # number of cpu cycles simulated -testsys.cpu.num_insts 3560518 # Number of instructions executed -testsys.cpu.num_refs 1173605 # Number of memory references +testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated +testsys.cpu.num_insts 3560411 # Number of instructions executed +testsys.cpu.num_refs 1173571 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 225676946325 # Simulator instruction rate (inst/s) -host_mem_usage 479796 # Number of bytes of host memory used +host_inst_rate 147646773096 # Simulator instruction rate (inst/s) +host_mem_usage 477336 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 612132399 # Simulator tick rate (ticks/s) +host_tick_rate 399988804 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294782 # Number of instructions simulated +sim_insts 273294177 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 66e5a984c..e7a8e93ac 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,8 +1,8 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for testsys connection on port 3457 +Listening for testsys connection on port 3456 warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for drivesys connection on port 3461 -0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7006 -0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7007 +Listening for drivesys connection on port 3457 +0: testsys.remote_gdb.listener: listening for remote gdb on port 7005 +0: drivesys.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... -warn: Obsolete M5 instruction ivlb encountered. +warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index c137b03cf..d355bed12 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:27:45 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:07:37 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4300235844056 because checkpoint +Exiting @ tick 4300236804024 because checkpoint -- cgit v1.2.3 From 50ef39af82413ef463609f24173b22af13fad268 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 3 Aug 2008 18:19:55 -0700 Subject: sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. --- tests/run.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/run.py b/tests/run.py index 9b77ff9d2..aadc16b93 100644 --- a/tests/run.py +++ b/tests/run.py @@ -26,7 +26,12 @@ # # Authors: Steve Reinhardt -import os, sys +import os +import sys +import m5 + +# Since we're in batch mode, dont allow tcp socket connections +m5.disableAllListeners() # single "path" arg encodes everything we need to know about test (category, name, isa, opsys, config) = sys.argv[1].split('/') @@ -57,8 +62,7 @@ execfile(os.path.join(tests_root, 'configs', config + '.py')) # set default maxtick... script can override # -1 means run forever -from m5 import MaxTick -maxtick = MaxTick +maxtick = m5.MaxTick # tweak configuration for specific test -- cgit v1.2.3 From 6f92e9b8d4c1aa366a7570faa57ac8120037c9c4 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 4 Aug 2008 00:48:11 -0400 Subject: Make test/SConscript use new redirection options. --- tests/SConscript | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 62c4d0508..af11195cc 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -178,23 +178,18 @@ def test_builder(env, ref_dir): # referring to files via SOURCES and TARGETS so that scons can # mess with paths all it wants to and we still get the right # files. - base_cmd = '${SOURCES[0]} -d $TARGET.dir ${SOURCES[1]} %s' % tgt_dir - # stdout and stderr files - cmd_stdout = '${TARGETS[0]}' - cmd_stderr = '${TARGETS[1]}' + cmd = '${SOURCES[0]} -d $TARGET.dir' + cmd += ' -re --stdout-file ${TARGETS[0]} --stderr-file ${TARGETS[1]}' + cmd += ' ${SOURCES[1]} %s' % tgt_dir # Prefix test run with batch job submission command if appropriate. - # Output redirection is also different for batch runs. # Batch command also supports timeout arg (in seconds, not minutes). - timeout = 15 # used to be a param, probably should be again + timeout = 15 * 60 # used to be a param, probably should be again if env['BATCH']: - cmd = [env['BATCH_CMD'], '-t', str(timeout * 60), - '-o', cmd_stdout, '-e', cmd_stderr, base_cmd] - else: - cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr] + cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) env.Command([tgt('stdout'), tgt('stderr'), new_stats], - [env.M5Binary, 'run.py'], ' '.join(cmd)) + [env.M5Binary, 'run.py'], cmd) # order of targets is important... see check_test env.Command([tgt('outdiff'), tgt('statsdiff'), status_file], -- cgit v1.2.3 From ab6e522032a752402af6be6f06862faee00a3018 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 4 Aug 2008 01:01:35 -0400 Subject: Minor fix for test/SConscript... forgot to 'qref' before 'qdel', argh. --- tests/SConscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index af11195cc..984eaa97c 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -179,7 +179,7 @@ def test_builder(env, ref_dir): # mess with paths all it wants to and we still get the right # files. cmd = '${SOURCES[0]} -d $TARGET.dir' - cmd += ' -re --stdout-file ${TARGETS[0]} --stderr-file ${TARGETS[1]}' + cmd += ' -re --stdout-file stdout --stderr-file stderr' cmd += ' ${SOURCES[1]} %s' % tgt_dir # Prefix test run with batch job submission command if appropriate. -- cgit v1.2.3 From 30bc897613a1ee36ed887eb9da1579bd9828186e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 3 Sep 2008 00:52:54 -0400 Subject: X86: Fix the microcode for sign/zero extending moves that use high byte registers. --- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../00.gzip/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- .../long/10.mcf/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- .../20.parser/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../20.parser/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- .../long/20.parser/ref/x86/linux/simple-atomic/stderr | 2 +- .../long/20.parser/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- .../60.bzip2/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- .../70.twolf/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../70.twolf/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr | 2 +- tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- .../00.hello/ref/x86/linux/simple-atomic/config.ini | 3 ++- .../00.hello/ref/x86/linux/simple-atomic/m5stats.txt | 14 +++++++------- .../quick/00.hello/ref/x86/linux/simple-atomic/stderr | 2 +- .../quick/00.hello/ref/x86/linux/simple-atomic/stdout | 14 +++++++------- 24 files changed, 112 insertions(+), 106 deletions(-) mode change 100644 => 100755 tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/20.parser/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/20.parser/ref/x86/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout mode change 100644 => 100755 tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr mode change 100644 => 100755 tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 7cc249f17..fb96ff412 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index 9e6571b45..ccee129c6 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2111657 # Simulator instruction rate (inst/s) -host_mem_usage 206000 # Number of bytes of host memory used -host_seconds 759.59 # Real time elapsed on the host -host_tick_rate 1257375756 # Simulator tick rate (ticks/s) +host_inst_rate 1695420 # Simulator instruction rate (inst/s) +host_mem_usage 194768 # Number of bytes of host memory used +host_seconds 955.72 # Real time elapsed on the host +host_tick_rate 1007896114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1603986018 # Number of instructions simulated -sim_seconds 0.955086 # Number of seconds simulated -sim_ticks 955086010500 # Number of ticks simulated +sim_insts 1620345246 # Number of instructions simulated +sim_seconds 0.963266 # Number of seconds simulated +sim_ticks 963265624500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1910172022 # number of cpu cycles simulated -system.cpu.num_insts 1603986018 # Number of instructions executed +system.cpu.numCycles 1926531250 # number of cpu cycles simulated +system.cpu.num_insts 1620345246 # Number of instructions executed system.cpu.num_refs 607160103 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 4cf848bfa..bd8016039 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index cca1d58a5..700bd8c8c --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:08:42 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:04 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 955086010500 because target called exit() +Exiting @ tick 963265624500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index e2db98cec..7f2a4c792 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:268435455 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index e2d716404..0b2ce70f9 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2310204 # Simulator instruction rate (inst/s) -host_mem_usage 340492 # Number of bytes of host memory used -host_seconds 116.72 # Real time elapsed on the host -host_tick_rate 1419682765 # Simulator tick rate (ticks/s) +host_inst_rate 1382425 # Simulator instruction rate (inst/s) +host_mem_usage 329284 # Number of bytes of host memory used +host_seconds 195.09 # Real time elapsed on the host +host_tick_rate 849513127 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269654744 # Number of instructions simulated -sim_seconds 0.165710 # Number of seconds simulated -sim_ticks 165710415000 # Number of ticks simulated +sim_insts 269697420 # Number of instructions simulated +sim_seconds 0.165732 # Number of seconds simulated +sim_ticks 165731753000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331420831 # number of cpu cycles simulated -system.cpu.num_insts 269654744 # Number of instructions executed +system.cpu.numCycles 331463507 # number of cpu cycles simulated +system.cpu.num_insts 269697420 # Number of instructions executed system.cpu.num_refs 124054658 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index d81394784..88df04dd8 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index ac908f417..2116bb4ba --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:09:15 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:01 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165710415000 because target called exit() +Exiting @ tick 165731753000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 3a3046603..300a3a0b4 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index 9ef50e95e..ee6f3d5dc 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2071310 # Simulator instruction rate (inst/s) -host_mem_usage 209664 # Number of bytes of host memory used -host_seconds 716.88 # Real time elapsed on the host -host_tick_rate 1204360345 # Simulator tick rate (ticks/s) +host_inst_rate 1780328 # Simulator instruction rate (inst/s) +host_mem_usage 198432 # Number of bytes of host memory used +host_seconds 840.01 # Real time elapsed on the host +host_tick_rate 1034139857 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484872746 # Number of instructions simulated -sim_seconds 0.863378 # Number of seconds simulated -sim_ticks 863377516000 # Number of ticks simulated +sim_insts 1495492819 # Number of instructions simulated +sim_seconds 0.868688 # Number of seconds simulated +sim_ticks 868687552500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726755033 # number of cpu cycles simulated -system.cpu.num_insts 1484872746 # Number of instructions executed +system.cpu.numCycles 1737375106 # number of cpu cycles simulated +system.cpu.num_insts 1495492819 # Number of instructions executed system.cpu.num_refs 533549003 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index e75f35ba1..4a54d0384 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index ea6ac1298..fcf87de75 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:09:17 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:02 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Reading the dictionary files: ************************************************* @@ -71,4 +71,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 863377516000 because target called exit() +Exiting @ tick 868687552500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3ebce331c..3a2c48ff2 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index 9b7f29b45..2e5af9606 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2222828 # Simulator instruction rate (inst/s) -host_mem_usage 206012 # Number of bytes of host memory used -host_seconds 2067.49 # Real time elapsed on the host -host_tick_rate 1357412596 # Simulator tick rate (ticks/s) +host_inst_rate 2125831 # Simulator instruction rate (inst/s) +host_mem_usage 194800 # Number of bytes of host memory used +host_seconds 2188.89 # Real time elapsed on the host +host_tick_rate 1295270570 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4595681265 # Number of instructions simulated -sim_seconds 2.806442 # Number of seconds simulated -sim_ticks 2806441694500 # Number of ticks simulated +sim_insts 4653219908 # Number of instructions simulated +sim_seconds 2.835211 # Number of seconds simulated +sim_ticks 2835211016000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5612883390 # number of cpu cycles simulated -system.cpu.num_insts 4595681265 # Number of instructions executed +system.cpu.numCycles 5670422033 # number of cpu cycles simulated +system.cpu.num_insts 4653219908 # Number of instructions executed system.cpu.num_refs 1686313784 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 64c88a35a..4a54d0384 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 32d78ce58..df51001f3 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:11:12 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:01 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2806441694500 because target called exit() +Exiting @ tick 2835211016000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index bdad08432..a50589b32 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index 3c3b5e445..df2f6c498 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1772433 # Simulator instruction rate (inst/s) -host_mem_usage 213128 # Number of bytes of host memory used -host_seconds 123.23 # Real time elapsed on the host -host_tick_rate 1054286984 # Simulator tick rate (ticks/s) +host_inst_rate 1393641 # Simulator instruction rate (inst/s) +host_mem_usage 201900 # Number of bytes of host memory used +host_seconds 156.85 # Real time elapsed on the host +host_tick_rate 828865190 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218419088 # Number of instructions simulated -sim_seconds 0.129921 # Number of seconds simulated -sim_ticks 129921260000 # Number of ticks simulated +sim_insts 218595439 # Number of instructions simulated +sim_seconds 0.130009 # Number of seconds simulated +sim_ticks 130009435500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259842521 # number of cpu cycles simulated -system.cpu.num_insts 218419088 # Number of instructions executed +system.cpu.numCycles 260018872 # number of cpu cycles simulated +system.cpu.num_insts 218595439 # Number of instructions executed system.cpu.num_refs 77165367 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 8adaf60da..c336b1cb3 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 793e5c943..48714ece9 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:12:24 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:03 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 129921260000 because target called exit() +122 123 124 Exiting @ tick 130009435500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 40d1ca238..140ac8ef9 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index ef5ccc7e6..296fe27ac 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 69477 # Simulator instruction rate (inst/s) -host_mem_usage 201612 # Number of bytes of host memory used +host_inst_rate 67755 # Simulator instruction rate (inst/s) +host_mem_usage 190344 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 40336760 # Simulator tick rate (ticks/s) +host_tick_rate 39312509 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9511 # Number of instructions simulated +sim_insts 9551 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5529000 # Number of ticks simulated +sim_ticks 5549000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11059 # number of cpu cycles simulated -system.cpu.num_insts 9511 # Number of instructions executed +system.cpu.numCycles 11099 # number of cpu cycles simulated +system.cpu.num_insts 9551 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr old mode 100644 new mode 100755 index e29ceab39..88df04dd8 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout old mode 100644 new mode 100755 index ada9a56fb..49a567e66 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:08:41 -M5 started Wed Jul 23 16:14:28 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic +M5 compiled Aug 31 2008 22:55:36 +M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 +M5 commit date Sun Aug 31 22:51:39 2008 -0400 +M5 started Aug 31 2008 22:56:02 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5529000 because target called exit() +Exiting @ tick 5549000 because target called exit() -- cgit v1.2.3 From bb3ab0f474c046a6be53640873f70c71c19a70ce Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 28 Sep 2008 14:15:37 -0700 Subject: tests: Kevin fixed how writebacks are handled in SMT and that changed stats. --- .../ref/alpha/linux/o3-timing/m5stats.txt | 746 ++++++++++----------- .../ref/alpha/linux/o3-timing/stderr | 3 +- .../ref/alpha/linux/o3-timing/stdout | 14 +- 3 files changed, 381 insertions(+), 382 deletions(-) mode change 100644 => 100755 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr mode change 100644 => 100755 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout (limited to 'tests') diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 1ece980d2..14012208f 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 849 # Number of BTB hits -global.BPredUnit.BTBLookups 4531 # Number of BTB lookups -global.BPredUnit.RASInCorrect 176 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1493 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2930 # Number of conditional branches predicted -global.BPredUnit.lookups 5203 # Number of BP lookups -global.BPredUnit.usedRAS 663 # Number of times the RAS was used to get a target. -host_inst_rate 79876 # Simulator instruction rate (inst/s) -host_mem_usage 198844 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 88938501 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 48 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2378 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2381 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1292 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1235 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 854 # Number of BTB hits +global.BPredUnit.BTBLookups 4386 # Number of BTB lookups +global.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1443 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2855 # Number of conditional branches predicted +global.BPredUnit.lookups 5041 # Number of BP lookups +global.BPredUnit.usedRAS 646 # Number of times the RAS was used to get a target. +host_inst_rate 37318 # Simulator instruction rate (inst/s) +host_mem_usage 199092 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host +host_tick_rate 41547100 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 42 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 25 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2333 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1249 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12595 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14042500 # Number of ticks simulated +sim_ticks 14029500 # Number of ticks simulated system.cpu.commit.COM:branches 2024 # Number of branches committed system.cpu.commit.COM:branches_0 1012 # Number of branches committed system.cpu.commit.COM:branches_1 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 138 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 158 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 22161 +system.cpu.commit.COM:committed_per_cycle.samples 21929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16399 7399.94% - 1 2912 1314.02% - 2 1246 562.25% - 3 587 264.88% - 4 387 174.63% - 5 231 104.24% - 6 170 76.71% - 7 91 41.06% - 8 138 62.27% + 0 16145 7362.40% + 1 3000 1368.05% + 2 1194 544.48% + 3 576 262.67% + 4 357 162.80% + 5 253 115.37% + 6 166 75.70% + 7 80 36.48% + 8 158 72.05% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 12629 # Number of instructions committed -system.cpu.commit.COM:count_0 6315 # Number of instructions committed -system.cpu.commit.COM:count_1 6314 # Number of instructions committed +system.cpu.commit.COM:count_0 6314 # Number of instructions committed +system.cpu.commit.COM:count_1 6315 # Number of instructions committed system.cpu.commit.COM:loads 2336 # Number of loads committed system.cpu.commit.COM:loads_0 1168 # Number of loads committed system.cpu.commit.COM:loads_1 1168 # Number of loads committed @@ -61,89 +61,89 @@ system.cpu.commit.COM:refs_1 2030 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1089 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1061 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10184 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6298 # Number of Instructions Simulated -system.cpu.committedInsts_1 6297 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 9861 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6297 # Number of Instructions Simulated +system.cpu.committedInsts_1 6298 # Number of Instructions Simulated system.cpu.committedInsts_total 12595 # Number of Instructions Simulated -system.cpu.cpi_0 4.459511 # CPI: Cycles Per Instruction -system.cpu.cpi_1 4.460219 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.229933 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 35747.734139 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 37101.010101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3422 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3422 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11832500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 11832500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.088196 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 331 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 331 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 133 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 7346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052758 # mshr miss rate for ReadReq accesses +system.cpu.cpi_0 4.456090 # CPI: Cycles Per Instruction +system.cpu.cpi_1 4.455383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.227868 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 35521.212121 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36972.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3416 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3416 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11722000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 11722000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.088094 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 330 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 132 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 7320500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 7320500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052856 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 33945.394737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36212.643678 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 33638.157895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 35974.137931 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 964 # number of WriteReq hits system.cpu.dcache.WriteReq_hits_0 964 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25798500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 25798500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25565000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 25565000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate_0 0.440835 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6301000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 6301000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6259500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 6259500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.933140 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.915698 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5477 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5477 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5470 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5470 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 34492.208983 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 34208.256881 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4380 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 37631000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 37631000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 37287000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 37287000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.199197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.199269 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1091 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1091 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1090 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 719 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 719 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 718 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 718 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13647000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 13647000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 13580000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 13580000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.067920 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.068007 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_0 372 # number of demand (read+write) MSHR misses @@ -153,38 +153,38 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5477 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5477 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5470 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5470 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 34492.208983 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 34208.256881 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4386 # number of overall hits -system.cpu.dcache.overall_hits_0 4386 # number of overall hits +system.cpu.dcache.overall_hits 4380 # number of overall hits +system.cpu.dcache.overall_hits_0 4380 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 37631000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 37631000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 37287000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 37287000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.199197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.199269 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1091 # number of overall misses -system.cpu.dcache.overall_misses_0 1091 # number of overall misses +system.cpu.dcache.overall_misses 1090 # number of overall misses +system.cpu.dcache.overall_misses_0 1090 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 719 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 719 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 718 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 718 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13647000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 13647000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 13580000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 13580000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.067920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.068007 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_0 372 # number of overall MSHR misses @@ -211,157 +211,157 @@ system.cpu.dcache.sampled_refs 344 # Sa system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 220.225325 # Cycle average of tags in use -system.cpu.dcache.total_refs 4449 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 218.241072 # Cycle average of tags in use +system.cpu.dcache.total_refs 4443 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4888 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 421 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 556 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 26407 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32471 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4675 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2005 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 667 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 168 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 6113 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 5036 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 400 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 534 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 25996 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32008 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4597 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1938 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 558 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 173 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 6094 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5960 # DTB hits -system.cpu.dtb.misses 153 # DTB misses -system.cpu.dtb.read_accesses 3958 # DTB read accesses +system.cpu.dtb.hits 5949 # DTB hits +system.cpu.dtb.misses 145 # DTB misses +system.cpu.dtb.read_accesses 3938 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3865 # DTB read hits -system.cpu.dtb.read_misses 93 # DTB read misses -system.cpu.dtb.write_accesses 2155 # DTB write accesses +system.cpu.dtb.read_hits 3853 # DTB read hits +system.cpu.dtb.read_misses 85 # DTB read misses +system.cpu.dtb.write_accesses 2156 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2095 # DTB write hits +system.cpu.dtb.write_hits 2096 # DTB write hits system.cpu.dtb.write_misses 60 # DTB write misses -system.cpu.fetch.Branches 5203 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3861 # Number of cache lines fetched -system.cpu.fetch.Cycles 8930 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 591 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 29621 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.185252 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3861 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1512 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.054654 # Number of inst fetches per cycle +system.cpu.fetch.Branches 5041 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3820 # Number of cache lines fetched +system.cpu.fetch.Cycles 8809 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 28977 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1559 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179651 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1500 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.032680 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 22207 +system.cpu.fetch.rateDist.samples 21971 system.cpu.fetch.rateDist.min_value 0 - 0 17188 7739.90% - 1 414 186.43% - 2 327 147.25% - 3 389 175.17% - 4 409 184.18% - 5 315 141.85% - 6 447 201.29% - 7 251 113.03% - 8 2467 1110.91% + 0 17033 7752.49% + 1 423 192.53% + 2 326 148.38% + 3 380 172.96% + 4 411 187.06% + 5 313 142.46% + 6 429 195.26% + 7 269 122.43% + 8 2387 1086.43% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 36045.289855 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35597.896440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3033 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 3033 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29845500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 29845500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.214452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 828 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 828 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21999500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 21999500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.160062 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 3820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 35987.893462 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35566.129032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2994 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2994 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 29726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.216230 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 826 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 826 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 206 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 206 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 22051000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 22051000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.162304 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.907767 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.829032 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3861 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3820 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3820 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 36045.289855 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 35987.893462 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 3033 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 3033 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2994 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2994 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29845500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 29845500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 29726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 29726000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.214452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.216230 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 828 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 828 # number of demand (read+write) misses +system.cpu.icache.demand_misses 826 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 826 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 210 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 206 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 206 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21999500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 21999500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 22051000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 22051000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.160062 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.162304 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 618 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3861 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3820 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3820 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 36045.289855 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 35987.893462 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3033 # number of overall hits -system.cpu.icache.overall_hits_0 3033 # number of overall hits +system.cpu.icache.overall_hits 2994 # number of overall hits +system.cpu.icache.overall_hits_0 2994 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 29845500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 29845500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 29726000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 29726000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.214452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.216230 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 828 # number of overall misses -system.cpu.icache.overall_misses_0 828 # number of overall misses +system.cpu.icache.overall_misses 826 # number of overall misses +system.cpu.icache.overall_misses_0 826 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 210 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 206 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 206 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21999500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 21999500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 22051000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 22051000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.160062 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.162304 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 618 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +381,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6 # number of replacements system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 322.695837 # Cycle average of tags in use -system.cpu.icache.total_refs 3033 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.256979 # Cycle average of tags in use +system.cpu.icache.total_refs 2994 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 5879 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2965 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1479 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1486 # Number of branches executed -system.cpu.iew.EXEC:nop 135 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 69 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.661860 # Inst execution rate -system.cpu.iew.EXEC:refs 6137 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 3077 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3060 # number of memory reference insts executed +system.cpu.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2958 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1488 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1470 # Number of branches executed +system.cpu.iew.EXEC:nop 133 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 63 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.660299 # Inst execution rate +system.cpu.iew.EXEC:refs 6116 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 3062 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3054 # number of memory reference insts executed system.cpu.iew.EXEC:stores 2176 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1094 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1082 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1102 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1074 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11623 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5794 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5829 # num instructions consuming a value -system.cpu.iew.WB:count 17865 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8901 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8964 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.541951 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.772351 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.769600 # average fanout of values written-back +system.cpu.iew.WB:consumers 11542 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5820 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5722 # num instructions consuming a value +system.cpu.iew.WB:count 17828 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8981 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8847 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.545155 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.771649 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.773506 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8961 # num instructions producing a value -system.cpu.iew.WB:producers_0 4475 # num instructions producing a value -system.cpu.iew.WB:producers_1 4486 # num instructions producing a value -system.cpu.iew.WB:rate 0.636082 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.316919 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.319163 # insts written-back per cycle -system.cpu.iew.WB:sent 18110 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 9029 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 9081 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1169 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4759 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 598 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2527 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 22890 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3961 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1983 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1978 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18589 # Number of executed instructions +system.cpu.iew.WB:producers 8917 # num instructions producing a value +system.cpu.iew.WB:producers_0 4491 # num instructions producing a value +system.cpu.iew.WB:producers_1 4426 # num instructions producing a value +system.cpu.iew.WB:rate 0.635353 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.320064 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.315289 # insts written-back per cycle +system.cpu.iew.WB:sent 18058 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 9082 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 8976 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1215 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1067 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4660 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 801 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2511 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22574 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3940 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1960 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1980 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1001 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18528 # Number of executed instructions system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2005 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1938 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1210 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 430 # Number of stores squashed +system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1159 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1213 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 373 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 139 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 999 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 250 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.224240 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.224204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.448444 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9805 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1165 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 387 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 127 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 964 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 251 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.224412 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.224448 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.448860 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9816 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6546 66.76% # Type of FU issued + IntAlu 6598 67.22% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2114 21.56% # Type of FU issued - MemWrite 1140 11.63% # Type of FU issued + MemRead 2077 21.16% # Type of FU issued + MemWrite 1136 11.57% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 9829 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 9713 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6612 67.27% # Type of FU issued + IntAlu 6508 67.00% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2096 21.32% # Type of FU issued - MemWrite 1116 11.35% # Type of FU issued + MemRead 2085 21.47% # Type of FU issued + MemWrite 1115 11.48% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 19634 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 19529 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 13158 67.02% # Type of FU issued + IntAlu 13106 67.11% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4210 21.44% # Type of FU issued - MemWrite 2256 11.49% # Type of FU issued + MemRead 4162 21.31% # Type of FU issued + MemWrite 2251 11.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 163 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 81 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 82 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008302 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004125 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004176 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 165 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 86 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 79 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004404 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004045 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 10 6.13% # attempts to use FU when none available + IntAlu 5 3.03% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,136 +543,136 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 92 56.44% # attempts to use FU when none available - MemWrite 61 37.42% # attempts to use FU when none available + MemRead 94 56.97% # attempts to use FU when none available + MemWrite 66 40.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 22207 +system.cpu.iq.ISSUE:issued_per_cycle.samples 21971 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 13725 6180.48% - 1 3247 1462.15% - 2 2190 986.18% - 3 1374 618.72% - 4 899 404.83% - 5 454 204.44% - 6 231 104.02% - 7 63 28.37% - 8 24 10.81% + 0 13541 6163.12% + 1 3190 1451.91% + 2 2253 1025.44% + 3 1351 614.90% + 4 834 379.59% + 5 490 223.02% + 6 205 93.30% + 7 92 41.87% + 8 15 6.83% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.699067 # Inst issue rate -system.cpu.iq.iqInstsAdded 22710 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19634 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5121 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3911 # ITB accesses +system.cpu.iq.ISSUE:rate 0.695973 # Inst issue rate +system.cpu.iq.iqInstsAdded 22397 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19529 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8499 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4789 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3871 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3861 # ITB hits -system.cpu.itb.misses 50 # ITB misses +system.cpu.itb.hits 3820 # ITB hits +system.cpu.itb.misses 51 # ITB misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34636.986301 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31585.616438 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5057000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 5057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34517.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31445.205479 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5039500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 5039500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4611500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4611500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4591000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4591000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 34609.950860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31482.800983 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 34572.916667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31431.372549 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 28172500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 28172500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 814 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 814 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25627000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 814 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 28211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 28211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.997555 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 816 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 816 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 25648000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25648000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 816 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 816 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34303.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 960500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 960500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34410.714286 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31232.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 963500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 963500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 873000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 873000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 874500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 874500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6200 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 5 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.002538 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 31000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 964 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 964 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 34614.062500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 34564.449064 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33229500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 33229500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 33251000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 33251000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997925 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 960 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 960 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 30238500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 30238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 30239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 30239000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997925 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 960 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 964 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 964 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 34614.062500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 34564.449064 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency @@ -680,26 +680,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_hits_0 2 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33229500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 33229500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 33251000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 33251000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 960 # number of overall misses -system.cpu.l2cache.overall_misses_0 960 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 30238500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 30238500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 30239000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 30239000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 960 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -719,34 +719,34 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 786 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 788 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 433.129952 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 431.449507 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 28086 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2865 # Number of cycles rename is blocking +system.cpu.numCycles 28060 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2889 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 32955 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1341 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 31504 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 25059 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 18781 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4307 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2005 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1387 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9707 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 688 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3332 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 32446 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 31166 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 24765 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18538 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4270 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1938 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1355 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9464 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 854 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3364 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed +system.cpu.timesIdled 254 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr old mode 100644 new mode 100755 index 792313cca..8867143dd --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -0: system.remote_gdb.listener: listening for remote gdb on port 7008 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout old mode 100644 new mode 100755 index 35ba3f4fd..57e2874c3 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:13:24 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:23 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 14042500 because target called exit() +Exiting @ tick 14029500 because target called exit() -- cgit v1.2.3 From f2f40bcb77f7b356543883da07bb97f2ebe9ed3a Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 28 Sep 2008 14:15:50 -0700 Subject: tests: perlbmk now works. Commit stats and assume the're right. Kevin fixed how O3 handles syscalls that change NextPC (longjump). --- .../ref/alpha/tru64/o3-timing/config.ini | 403 ++++++ .../ref/alpha/tru64/o3-timing/m5stats.txt | 449 +++++++ .../40.perlbmk/ref/alpha/tru64/o3-timing/stderr | 5 + .../40.perlbmk/ref/alpha/tru64/o3-timing/stdout | 1390 ++++++++++++++++++++ 4 files changed, 2247 insertions(+) create mode 100644 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini create mode 100644 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt create mode 100755 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr create mode 100755 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout (limited to 'tests') diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini new file mode 100644 index 000000000..bc6eef39f --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -0,0 +1,403 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList5.opList + +[system.cpu.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList7.opList + +[system.cpu.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt new file mode 100644 index 000000000..655aa8500 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 240462096 # Number of BTB hits +global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups +global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted +global.BPredUnit.lookups 349424732 # Number of BP lookups +global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target. +host_inst_rate 256177 # Simulator instruction rate (inst/s) +host_mem_usage 209160 # Number of bytes of host memory used +host_seconds 7116.35 # Real time elapsed on the host +host_tick_rate 99090030 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1823043370 # Number of instructions simulated +sim_seconds 0.705159 # Number of seconds simulated +sim_ticks 705159454500 # Number of ticks simulated +system.cpu.commit.COM:branches 266706457 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1310002800 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 603585598 4607.51% + 1 273587002 2088.45% + 2 174037133 1328.52% + 3 65399709 499.23% + 4 48333002 368.95% + 5 34003109 259.57% + 6 18481317 141.08% + 7 23715686 181.04% + 8 68860244 525.65% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 2008987604 # Number of instructions committed +system.cpu.commit.COM:loads 511595302 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 722390433 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 696013928 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1823043370 # Number of Instructions Simulated +system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated +system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 465737270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37550.777258 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 463802713 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72644119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 440.284638 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 676532166 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674038254 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94226058985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2493912 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959838 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 676532166 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 674038254 # number of overall hits +system.cpu.dcache.overall_miss_latency 94226058985 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2493912 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959838 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1526847 # number of replacements +system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use +system.cpu.dcache.total_refs 674050685 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2936172394 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 716337475 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561391035 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 775959989 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 775335045 # DTB hits +system.cpu.dtb.misses 624944 # DTB misses +system.cpu.dtb.read_accesses 516992086 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 516404964 # DTB read hits +system.cpu.dtb.read_misses 587122 # DTB read misses +system.cpu.dtb.write_accesses 258967903 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 258930081 # DTB write hits +system.cpu.dtb.write_misses 37822 # DTB write misses +system.cpu.fetch.Branches 349424732 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched +system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3030218621 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 290350353 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 1410161885 +system.cpu.fetch.rateDist.min_value 0 + 0 830588040 5890.02% + 1 53463106 379.13% + 2 39766072 282.00% + 3 63538024 450.57% + 4 121390718 860.83% + 5 35256321 250.02% + 6 38761683 274.87% + 7 6988644 49.56% + 8 220409277 1563.01% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses +system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 348437250 # number of overall hits +system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses +system.cpu.icache.overall_misses 10649 # number of overall misses +system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 8097 # number of replacements +system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use +system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 274534146 # Number of branches executed +system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate +system.cpu.iew.EXEC:refs 776495505 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258968901 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1631503181 # num instructions consuming a value +system.cpu.iew.WB:count 2002130592 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1136229271 # num instructions producing a value +system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle +system.cpu.iew.WB:sent 2003425038 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 31680134 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 655954744 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 62125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2715209776 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 517526604 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85279851 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2004227959 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 144359442 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30863144 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2089507810 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 2752 0.00% # Type of FU issued + IntAlu 1204412682 57.64% # Type of FU issued + IntMult 17591 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 27851349 1.33% # Type of FU issued + FloatCmp 8254694 0.40% # Type of FU issued + FloatCvt 7204646 0.34% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 557993260 26.70% # Type of FU issued + MemWrite 283770832 13.58% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 37093549 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 8291 0.02% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 28032979 75.57% # attempts to use FU when none available + MemWrite 9052279 24.40% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 537278440 3810.05% + 1 285217725 2022.59% + 2 273546794 1939.83% + 3 154810622 1097.82% + 4 63341839 449.18% + 5 51438518 364.77% + 6 32491112 230.41% + 7 9036667 64.08% + 8 3000168 21.28% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate +system.cpu.iq.iqInstsAdded 2386031658 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2089507810 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 562621265 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 516017441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 348448092 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 348447899 # ITB hits +system.cpu.itb.misses 193 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 28934 # number of overall hits +system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511777 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 1474251 # number of replacements +system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.numCycles 1410318910 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed +system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr new file mode 100755 index 000000000..70f4beb45 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout new file mode 100755 index 000000000..157f726f1 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout @@ -0,0 +1,1390 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 28 2008 07:36:20 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +1375000: 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3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 -- cgit v1.2.3 From 602faeb47ce74624087a84d78ead0ba84386a97f Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 28 Sep 2008 14:16:24 -0700 Subject: tests: rename the terminal files for solaris. I forgot to do this when I renamed everything else. --HG-- rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm --- .../console.system.t1000.hconsole | 0 .../console.system.t1000.pconsole | 48 ---------------------- .../solaris/t1000-simple-atomic/system.t1000.hterm | 0 .../solaris/t1000-simple-atomic/system.t1000.pterm | 48 ++++++++++++++++++++++ 4 files changed, 48 insertions(+), 48 deletions(-) delete mode 100644 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole delete mode 100644 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole create mode 100644 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm create mode 100644 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm (limited to 'tests') diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole deleted file mode 100644 index e69de29bb..000000000 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole deleted file mode 100644 index f90a96e24..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole +++ /dev/null @@ -1,48 +0,0 @@ -cpu - -Sun Fire T2000, No Keyboard -Copyright 2006 Sun Microsystems, Inc. All rights reserved. -OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. -[saidi obp #30] -Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. - - - -Boot device: /virtual-devices/disk@0 File and args: -vV -Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. -FCode UFS Reader 1.12 00/07/17 15:48:16. -Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot -Loading: /platform/sun4v/ufsboot -device path '/virtual-devices@100/disk@0:a' -The boot filesystem is logging. -The ufs log is empty and will not be used. -standalone = `kernel/sparcv9/unix', args = `-v' -|Elf64 client -Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes -modpath: /platform/sun4v/kernel /kernel /usr/kernel -|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000 -module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 -module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 -module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 -module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 -\ SunOS Release 5.10 Version Generic_118822-23 64-bit -Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. -Use is subject to license terms. -|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3 -\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000) -avail mem = 237879296 -root nexus = Sun Fire T2000 -pseudo0 at root -pseudo0 is /pseudo -scsi_vhci0 at root -scsi_vhci0 is /scsi_vhci -virtual-device: hsimd0 -hsimd0 is /virtual-devices@100/disk@0 -root on /virtual-devices@100/disk@0:a fstype ufs -pseudo-device: dld0 -dld0 is /pseudo/dld@0 -cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) -iscsi0 at root -iscsi0 is /iscsi -Hostname: unknown -Loading M5 readfile script... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm new file mode 100644 index 000000000..e69de29bb diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm new file mode 100644 index 000000000..f90a96e24 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm @@ -0,0 +1,48 @@ +cpu + +Sun Fire T2000, No Keyboard +Copyright 2006 Sun Microsystems, Inc. All rights reserved. +OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. +[saidi obp #30] +Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. + + + +Boot device: /virtual-devices/disk@0 File and args: -vV +Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. +FCode UFS Reader 1.12 00/07/17 15:48:16. +Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot +Loading: /platform/sun4v/ufsboot +device path '/virtual-devices@100/disk@0:a' +The boot filesystem is logging. +The ufs log is empty and will not be used. +standalone = `kernel/sparcv9/unix', args = `-v' +|Elf64 client +Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes +modpath: /platform/sun4v/kernel /kernel /usr/kernel +|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000 +module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 +module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 +module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 +module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 +\ SunOS Release 5.10 Version Generic_118822-23 64-bit +Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. +Use is subject to license terms. +|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3 +\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000) +avail mem = 237879296 +root nexus = Sun Fire T2000 +pseudo0 at root +pseudo0 is /pseudo +scsi_vhci0 at root +scsi_vhci0 is /scsi_vhci +virtual-device: hsimd0 +hsimd0 is /virtual-devices@100/disk@0 +root on /virtual-devices@100/disk@0:a fstype ufs +pseudo-device: dld0 +dld0 is /pseudo/dld@0 +cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) +iscsi0 at root +iscsi0 is /iscsi +Hostname: unknown +Loading M5 readfile script... -- cgit v1.2.3 From d2fae026a84c732ecd0dc898655f487f2e45bd35 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 28 Sep 2008 14:16:26 -0700 Subject: tests: Update all tests for small outstanding changes. Little differences have accumulated over time and it's worth getting things back in sync for the stable release. --- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 12 ++++++------ .../long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ .../long/00.gzip/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr | 2 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout | 12 ++++++------ .../long/00.gzip/ref/sparc/linux/simple-atomic/config.ini | 3 ++- tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr | 2 +- tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout | 12 ++++++------ .../long/00.gzip/ref/sparc/linux/simple-timing/config.ini | 1 + tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr | 2 +- tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout | 12 ++++++------ tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini | 3 ++- tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr | 2 +- tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout | 12 ++++++------ tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini | 1 + tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr | 2 +- tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout | 12 ++++++------ tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/long/20.parser/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 12 ++++++------ tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ .../40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ .../40.perlbmk/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout | 12 ++++++------ .../50.vortex/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ .../50.vortex/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ .../50.vortex/ref/sparc/linux/simple-atomic/config.ini | 4 +++- tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr | 2 +- tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout | 12 ++++++------ .../50.vortex/ref/sparc/linux/simple-timing/config.ini | 1 + tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr | 2 +- tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout | 12 ++++++------ tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 12 ++++++------ .../long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ .../long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 14 ++++++-------- .../long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout | 14 ++++++-------- .../long/70.twolf/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout | 14 ++++++-------- .../long/70.twolf/ref/sparc/linux/simple-atomic/config.ini | 3 ++- tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr | 2 +- tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout | 14 ++++++-------- .../long/70.twolf/ref/sparc/linux/simple-timing/config.ini | 1 + tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr | 2 +- tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout | 14 ++++++-------- tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout | 12 +++++------- .../ref/sparc/solaris/t1000-simple-atomic/config.ini | 13 +++++++------ .../ref/sparc/solaris/t1000-simple-atomic/stderr | 5 ++--- .../ref/sparc/solaris/t1000-simple-atomic/stdout | 12 ++++++------ tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr | 2 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout | 12 ++++++------ .../00.hello/ref/alpha/linux/simple-atomic/config.ini | 3 ++- tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr | 1 + tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout | 12 ++++++------ .../00.hello/ref/alpha/linux/simple-timing/config.ini | 1 + tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr | 2 +- tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout | 12 ++++++------ tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr | 2 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout | 12 ++++++------ .../00.hello/ref/alpha/tru64/simple-atomic/config.ini | 4 +++- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr | 1 + tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout | 12 ++++++------ .../00.hello/ref/alpha/tru64/simple-timing/config.ini | 1 + tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout | 12 ++++++------ .../quick/00.hello/ref/mips/linux/simple-atomic/config.ini | 4 +++- tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr | 1 + tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout | 12 ++++++------ .../quick/00.hello/ref/mips/linux/simple-timing/config.ini | 1 + tests/quick/00.hello/ref/mips/linux/simple-timing/stderr | 2 +- tests/quick/00.hello/ref/mips/linux/simple-timing/stdout | 12 ++++++------ .../00.hello/ref/sparc/linux/simple-atomic/config.ini | 3 ++- tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr | 2 +- tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout | 12 ++++++------ .../00.hello/ref/sparc/linux/simple-timing/config.ini | 1 + tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr | 2 +- tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout | 12 ++++++------ tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout | 10 +++++----- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr | 2 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout | 12 ++++++------ .../02.insttest/ref/sparc/linux/simple-atomic/config.ini | 3 ++- .../quick/02.insttest/ref/sparc/linux/simple-atomic/stderr | 2 +- .../quick/02.insttest/ref/sparc/linux/simple-atomic/stdout | 12 ++++++------ .../02.insttest/ref/sparc/linux/simple-timing/config.ini | 1 + .../quick/02.insttest/ref/sparc/linux/simple-timing/stderr | 2 +- .../quick/02.insttest/ref/sparc/linux/simple-timing/stdout | 12 ++++++------ .../ref/alpha/linux/tsunami-simple-atomic-dual/config.ini | 2 ++ .../ref/alpha/linux/tsunami-simple-atomic-dual/stderr | 5 ++--- .../ref/alpha/linux/tsunami-simple-atomic-dual/stdout | 12 ++++++------ .../ref/alpha/linux/tsunami-simple-atomic/config.ini | 1 + .../ref/alpha/linux/tsunami-simple-atomic/stderr | 4 ++-- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 12 ++++++------ .../ref/alpha/linux/tsunami-simple-timing-dual/config.ini | 2 ++ .../ref/alpha/linux/tsunami-simple-timing-dual/stderr | 5 ++--- .../ref/alpha/linux/tsunami-simple-timing-dual/stdout | 12 ++++++------ .../ref/alpha/linux/tsunami-simple-timing/config.ini | 1 + .../ref/alpha/linux/tsunami-simple-timing/stderr | 4 ++-- .../ref/alpha/linux/tsunami-simple-timing/stdout | 12 ++++++------ .../20.eio-short/ref/alpha/eio/simple-atomic/config.ini | 4 +++- .../quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr | 1 + .../quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout | 12 ++++++------ .../20.eio-short/ref/alpha/eio/simple-timing/config.ini | 1 + .../20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt | 8 ++++---- .../quick/20.eio-short/ref/alpha/eio/simple-timing/stderr | 2 +- .../quick/20.eio-short/ref/alpha/eio/simple-timing/stdout | 12 ++++++------ tests/quick/50.memtest/ref/alpha/linux/memtest/stderr | 0 tests/quick/50.memtest/ref/alpha/linux/memtest/stdout | 12 ++++++------ .../alpha/linux/twosys-tsunami-simple-atomic/config.ini | 6 ++++-- .../ref/alpha/linux/twosys-tsunami-simple-atomic/stderr | 6 ++---- .../ref/alpha/linux/twosys-tsunami-simple-atomic/stdout | 12 ++++++------ 141 files changed, 450 insertions(+), 406 deletions(-) mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr mode change 100644 => 100755 tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout mode change 100644 => 100755 tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout mode change 100644 => 100755 tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr mode change 100644 => 100755 tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr mode change 100644 => 100755 tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout mode change 100644 => 100755 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr mode change 100644 => 100755 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout mode change 100644 => 100755 tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr mode change 100644 => 100755 tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr mode change 100644 => 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout mode change 100644 => 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr mode change 100644 => 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout mode change 100644 => 100755 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tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr mode change 100644 => 100755 tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout mode change 100644 => 100755 tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr mode change 100644 => 100755 tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout mode change 100644 => 100755 tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr mode change 100644 => 100755 tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout mode change 100644 => 100755 tests/quick/50.memtest/ref/alpha/linux/memtest/stderr mode change 100644 => 100755 tests/quick/50.memtest/ref/alpha/linux/memtest/stdout mode change 100644 => 100755 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr mode change 100644 => 100755 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index 337694eda..7edb64427 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index 069608705..e18bd34ec --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:11:39 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:09:41 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 471b28d35..a002dafb3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index f33d007a7..7edb64427 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index 26bc81b05..5da808ef6 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic tests/run.py long/00.gzip/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:12:32 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 2080bc2a7..cbfde3c7a 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index 26249ed90..7edb64427 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 1e55b6a1c..ccbbe4b14 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:24 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:14:02 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr old mode 100644 new mode 100755 index 22ad4f8ac..0598945b4 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout old mode 100644 new mode 100755 index 331ed166e..168a468b1 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:21:17 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:21:26 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index ea30aeebe..94bc4dfcb 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 802ce964e..0598945b4 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index f085a464a..9aba34a0b --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:03:21 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:22:26 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 2047c5ea9..550c53eb7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index cdd59eda7..0598945b4 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index 78d24c8c9..fbc427ffb --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:23:47 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:25:17 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 700bd8c8c..4b2b46a54 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:04 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:33:06 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index b08c16b82..064c9f4af 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:268435455 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 2a6ac4135..0598945b4 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 772308160..9799173e4 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:56 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:28:02 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 0493cbfab..91c1b4f58 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index 320065be7..0598945b4 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index 1d6b63175..81c01b3d2 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:25:03 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:28:38 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second MCF SPEC version 1.6.I diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index 2116bb4ba..bfeaf8ac6 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:01 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:33:22 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index fcf87de75..01ec1845d 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:02 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:35:20 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index 982c0e2fd..b72d69553 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index bdcee079b..ce9f5b7a4 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:19 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:14:55 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index f1d9f437d..db2c600ee 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index 4bb0d9bbe..b72d69553 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index 285c8d750..0c68e7560 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:02 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic tests/run.py long/30.eon/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:59 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 77ba42098..a0f5ff1cc 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index 292df496c..b72d69553 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 0958fd3e9..6317641d5 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:16:23 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:19:23 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Eon, Version 1.1 OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 68b00e416..b01978881 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=perlbmk -I. -I lib lgred.makerand.pl cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index a6133a5ee..70f4beb45 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index e78146575..ff0b6f94d --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:58 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:15:46 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second 1375000: 2038431008 1374000: 3487365506 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index edda67681..d888b1d3a 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index ef87f0bcb..70f4beb45 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index f85223189..bb638ab73 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:20 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:24 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second 1375000: 2038431008 1374000: 3487365506 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index d6124e8ba..7edb64427 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index 103f04999..3c7b7f584 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:08:52 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:23 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 337e5e366..3d82ef611 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index f33d007a7..7edb64427 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index f99b33e5f..4f6e61da0 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:04 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic tests/run.py long/50.vortex/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:32 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 8d7054aba..65c1a4eef 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index 598fc86c0..7edb64427 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 82f9f1165..04c3255fb --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:10:35 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:24 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index b8eed166b..ce467d491 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=vortex bendian.raw cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index bc4f4d822..942c388e0 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7013 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index b230e2c83..068a01d62 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:38:08 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:29:09 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index b127e5d20..685fc165c 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index fc5baf4b1..942c388e0 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index dd1bc90df..5a2b5220b --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:28:00 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:30:05 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index 11628a59e..8867143dd --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index b38f0f385..d0f2d73e9 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:08:50 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:54 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 0768661a6..28bab6a3a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index d0a887867..8867143dd --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index 469f3b36a..cab37301e --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:16:25 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic tests/run.py long/60.bzip2/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:46 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 95f20bb49..811d5b2e6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index 660aa118b..8867143dd --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 7e1135f7a..aa4d0233f --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:11:35 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:57 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second spec_init Loading Input Data diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index df51001f3..0939c6481 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:01 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:36:52 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index 8053728f7..7edb64427 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index d1a734653..1669451f7 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:15:05 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:10:53 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index f0ed922b1..035d4db65 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index f33d007a7..7edb64427 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index 0fc73d0d9..f2321006a --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic tests/run.py long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:38 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 0a4a7ae02..fdbe4055f 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index 337694eda..7edb64427 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 77554b01e..2f63f8309 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:25 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:14:06 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 217cd2719..0da6124a8 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 598fc86c0..7edb64427 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 0ed160885..5631e050f --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:04:15 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:31:36 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index cf8698574..05096323e 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index 047da0c93..7edb64427 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index 88fe50099..f7be3ede4 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:29:26 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:31:45 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index 48714ece9..bb2f68a97 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:03 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:41:47 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 2616832f0..96250b233 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -62,6 +62,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -109,7 +110,7 @@ read_only=true [system.hypervisor_desc] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=133446500352:133446508543 @@ -179,7 +180,7 @@ pio=system.membus.default [system.nvram] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=133429198848:133429207039 @@ -189,7 +190,7 @@ port=system.membus.port[6] [system.partition_desc] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=133445976064:133445984255 @@ -199,7 +200,7 @@ port=system.membus.port[8] [system.physmem] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=1048576:68157439 @@ -209,7 +210,7 @@ port=system.membus.port[3] [system.physmem2] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=2147483648:2415919103 @@ -219,7 +220,7 @@ port=system.membus.port[4] [system.rom] type=PhysicalMemory file= -latency=1 +latency=60 latency_var=0 null=false range=1099243192320:1099251580927 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr old mode 100644 new mode 100755 index 4c0b4aee0..5c083e687 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -5,11 +5,10 @@ Warning: rounding error > tolerance warn: No kernel set for full system simulation. Assuming you know what you're doing... Warning: rounding error > tolerance 0.002000 rounded to 0 -Listening for t1000 connection on port 3456 -Listening for t1000 connection on port 3457 +warn: Sockets disabled, not accepting terminal connections Warning: rounding error > tolerance 0.002000 rounded to 0 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout old mode 100644 new mode 100755 index 78a121c17..18ed44091 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:41:45 -M5 started Mon Jul 21 20:41:46 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +M5 compiled Sep 27 2008 21:21:09 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:21:11 +M5 executing on piton +command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr old mode 100644 new mode 100755 index 337694eda..7edb64427 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout old mode 100644 new mode 100755 index d863a4704..55062a489 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:08:49 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:38 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 12391500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 5214649cb..f3b922bb8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr old mode 100644 new mode 100755 index f33d007a7..7edb64427 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1,2 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 7e1e7de26..34663e210 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:50:09 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:32 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 3170500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 1ee191af5..1f66e65a5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr old mode 100644 new mode 100755 index 598fc86c0..7edb64427 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout old mode 100644 new mode 100755 index 90b25945e..ac2c65392 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:10:34 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:24 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 33503000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr old mode 100644 new mode 100755 index 19df33f11..8c3c8342e --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout old mode 100644 new mode 100755 index c1c2d8a89..9f9b0550a --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:08:50 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:12:32 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 74656d464..bbdfaa101 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -51,6 +52,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -76,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr old mode 100644 new mode 100755 index 9f8e7c2e9..8c3c8342e --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout old mode 100644 new mode 100755 index 0f1a816dd..5ed36f668 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:58 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index d146bb3c1..bfcd95204 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr old mode 100644 new mode 100755 index bc68d7b07..8c3c8342e --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout old mode 100644 new mode 100755 index 97ac18bed..1cedfe45b --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:25 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:24 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 11bedc8c7..83f026450 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -78,6 +78,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -111,6 +112,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 @@ -136,7 +138,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr old mode 100644 new mode 100755 index f33d007a7..7edb64427 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr @@ -1,2 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 43b61af39..d2ef70029 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:31:07 -M5 started Mon Jul 21 20:31:10 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +M5 compiled Sep 27 2008 21:20:59 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:21:01 +M5 executing on piton +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello World! Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index fa2de5431..53b4a0368 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -78,6 +78,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr old mode 100644 new mode 100755 index 1ad466eb8..7edb64427 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout old mode 100644 new mode 100755 index 4c9c838f5..289b969c4 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:38 -M5 started Sat Aug 2 17:07:42 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +M5 compiled Sep 27 2008 21:20:59 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:21:02 +M5 executing on piton +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello World! Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index a80c5cabd..7ebff17bf 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 41aec2f86..0598945b4 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7012 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index c0e107ab6..11bda0e5c --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:55 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:32:52 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 1194cf323..9cdba6f24 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index 320065be7..0598945b4 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index 85eaa5038..134f2661f --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:29:40 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:32:53 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 49a567e66..e89d3c49f 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 31 2008 22:55:36 -M5 revision 5540:e8dde121a24fbf62092085d7d996cb8c965c3fe6 -M5 commit date Sun Aug 31 22:51:39 2008 -0400 -M5 started Aug 31 2008 22:56:02 -M5 executing on zizzer +M5 compiled Sep 27 2008 21:33:04 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:41:59 +M5 executing on piton command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr old mode 100644 new mode 100755 index 320065be7..0598945b4 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout old mode 100644 new mode 100755 index 6ac99b20a..ba74f1637 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:29:40 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:32:53 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index fe774ce88..bd75b6dd2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -77,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr old mode 100644 new mode 100755 index 320065be7..0598945b4 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout old mode 100644 new mode 100755 index 91b36f948..777898779 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:02:07 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:32:54 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 1df0c476d..7773c920e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr old mode 100644 new mode 100755 index 320065be7..0598945b4 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout old mode 100644 new mode 100755 index 8c9e71e76..1426e329d --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:21:13 -M5 started Sat Aug 2 17:29:41 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing +M5 compiled Sep 27 2008 21:21:24 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:32:54 +M5 executing on piton +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... LDSTUB: Passed diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index e57480396..a3b119b60 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -50,6 +50,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -161,6 +162,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr old mode 100644 new mode 100755 index 7d514c2b6..9825eea69 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,6 +1,5 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3459 -0: system.remote_gdb.listener: listening for remote gdb on port 7004 -0: system.remote_gdb.listener: listening for remote gdb on port 7008 +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout old mode 100644 new mode 100755 index 601a2c3c3..69f528e17 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:34 -M5 started Sat Aug 2 17:08:14 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Sep 27 2008 21:08:15 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:17 +M5 executing on piton +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index e739f3815..f63d2144d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -50,6 +50,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr old mode 100644 new mode 100755 index 438bf9f24..45392f539 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3459 -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout old mode 100644 new mode 100755 index 8a31735d4..4d9c075f2 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:34 -M5 started Sat Aug 2 17:08:29 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Sep 27 2008 21:08:15 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:17 +M5 executing on piton +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 2985b82ee..29f87c7e0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -50,6 +50,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -158,6 +159,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr old mode 100644 new mode 100755 index 98c38c0d8..c03c0154e --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,5 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -0: system.remote_gdb.listener: listening for remote gdb on port 7008 +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: 591544000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout old mode 100644 new mode 100755 index dff43c48d..02b572ec9 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:34 -M5 started Sat Aug 2 17:07:43 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Sep 27 2008 21:08:15 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:17 +M5 executing on piton +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 05eb9b89c..c6c4209f5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -50,6 +50,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr old mode 100644 new mode 100755 index 3aab2bec2..45392f539 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout old mode 100644 new mode 100755 index 4d30d3925..6ec325f9b --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:34 -M5 started Sat Aug 2 17:08:13 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Sep 27 2008 21:08:15 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:17 +M5 executing on piton +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index a0555b3f3..836233457 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 simulate_data_stalls=false @@ -48,6 +49,7 @@ type=ExeTracer [system.cpu.workload] type=EioProcess chkpt= +errout=cerr file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 @@ -67,7 +69,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr old mode 100644 new mode 100755 index 4e444fa6b..ea818e9b8 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout old mode 100644 new mode 100755 index 54f73c06e..e002b4982 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:16:25 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:14:06 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second main dictionary has 1245 entries 49508 bytes wasted diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 3d8212f3f..8c926f583 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -23,6 +23,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index e8282d216..fdebad7d8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1672362 # Simulator instruction rate (inst/s) -host_mem_usage 196544 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 2464131877 # Simulator tick rate (ticks/s) +host_inst_rate 1585966 # Simulator instruction rate (inst/s) +host_mem_usage 196712 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host +host_tick_rate 2336933545 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr old mode 100644 new mode 100755 index cc0a07c09..ea818e9b8 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout old mode 100644 new mode 100755 index 46fb8222f..fec2f14b8 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:10:34 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:23 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second main dictionary has 1245 entries 49508 bytes wasted diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr old mode 100644 new mode 100755 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout old mode 100644 new mode 100755 index 7382eca3b..0fc21b2ef --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:15 -M5 started Sat Aug 2 17:07:20 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest +M5 compiled Sep 27 2008 21:08:21 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:09:08 +M5 executing on piton +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 4a385ded6..2dc579fd2 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS +readfile=/n/iceaxe/Users/nate/work/m5/work/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -50,6 +50,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -698,7 +699,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS +readfile=/n/iceaxe/Users/nate/work/m5/work/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -734,6 +735,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr old mode 100644 new mode 100755 index e7a8e93ac..c0d2c6cc2 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,8 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for testsys connection on port 3456 +warn: Sockets disabled, not accepting terminal connections warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for drivesys connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb on port 7005 -0: drivesys.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout old mode 100644 new mode 100755 index d355bed12..3d3f5d1b8 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 2 2008 17:07:34 -M5 started Sat Aug 2 17:07:37 2008 -M5 executing on zizzer -M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 -M5 commit date Thu Jul 31 08:01:38 2008 -0700 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Sep 27 2008 21:08:15 +M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 +M5 commit date Sat Sep 27 21:03:50 2008 -0700 +M5 started Sep 27 2008 21:08:17 +M5 executing on piton +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 4300236804024 because checkpoint -- cgit v1.2.3 From 8384ff7d6c4460a966aec3b65a0af13e71bd76a2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 15:31:37 -0700 Subject: X86: Update the stats for cpuid's new implementation --- .../00.gzip/ref/x86/linux/simple-atomic/m5stats.txt | 20 ++++++++++---------- .../long/00.gzip/ref/x86/linux/simple-atomic/stderr | 4 ++++ .../long/00.gzip/ref/x86/linux/simple-atomic/stdout | 12 ++++++------ .../10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout | 12 ++++++------ .../ref/x86/linux/simple-atomic/m5stats.txt | 20 ++++++++++---------- .../20.parser/ref/x86/linux/simple-atomic/stdout | 12 ++++++------ .../60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- .../long/60.bzip2/ref/x86/linux/simple-atomic/stdout | 12 ++++++------ .../70.twolf/ref/x86/linux/simple-atomic/m5stats.txt | 18 +++++++++--------- .../long/70.twolf/ref/x86/linux/simple-atomic/stdout | 14 ++++++++------ .../00.hello/ref/x86/linux/simple-atomic/m5stats.txt | 16 ++++++++-------- .../00.hello/ref/x86/linux/simple-atomic/stdout | 12 ++++++------ 13 files changed, 97 insertions(+), 91 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index ccee129c6..e1904a94f 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1695420 # Simulator instruction rate (inst/s) -host_mem_usage 194768 # Number of bytes of host memory used -host_seconds 955.72 # Real time elapsed on the host -host_tick_rate 1007896114 # Simulator tick rate (ticks/s) +host_inst_rate 1864345 # Simulator instruction rate (inst/s) +host_mem_usage 194404 # Number of bytes of host memory used +host_seconds 868.62 # Real time elapsed on the host +host_tick_rate 1108605034 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1620345246 # Number of instructions simulated -sim_seconds 0.963266 # Number of seconds simulated -sim_ticks 963265624500 # Number of ticks simulated +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 0.962952 # Number of seconds simulated +sim_ticks 962951801000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1926531250 # number of cpu cycles simulated -system.cpu.num_insts 1620345246 # Number of instructions executed -system.cpu.num_refs 607160103 # Number of memory references +system.cpu.numCycles 1925903603 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr index bd8016039..c07fe7d68 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting gdb connections warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 4b2b46a54..92309e31c 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:33:06 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:20:39 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 963265624500 because target called exit() +Exiting @ tick 962951801000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index 0b2ce70f9..5d9da19d3 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1382425 # Simulator instruction rate (inst/s) -host_mem_usage 329284 # Number of bytes of host memory used -host_seconds 195.09 # Real time elapsed on the host -host_tick_rate 849513127 # Simulator tick rate (ticks/s) +host_inst_rate 1324719 # Simulator instruction rate (inst/s) +host_mem_usage 328816 # Number of bytes of host memory used +host_seconds 203.59 # Real time elapsed on the host +host_tick_rate 814052041 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697420 # Number of instructions simulated +sim_insts 269697303 # Number of instructions simulated sim_seconds 0.165732 # Number of seconds simulated -sim_ticks 165731753000 # Number of ticks simulated +sim_ticks 165731691000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331463507 # number of cpu cycles simulated -system.cpu.num_insts 269697420 # Number of instructions executed -system.cpu.num_refs 124054658 # Number of memory references +system.cpu.numCycles 331463383 # number of cpu cycles simulated +system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index bfeaf8ac6..00ec2119c 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:33:22 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:20:39 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165731753000 because target called exit() +Exiting @ tick 165731691000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index ee6f3d5dc..f1fef537b 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1780328 # Simulator instruction rate (inst/s) -host_mem_usage 198432 # Number of bytes of host memory used -host_seconds 840.01 # Real time elapsed on the host -host_tick_rate 1034139857 # Simulator tick rate (ticks/s) +host_inst_rate 1855549 # Simulator instruction rate (inst/s) +host_mem_usage 197988 # Number of bytes of host memory used +host_seconds 805.96 # Real time elapsed on the host +host_tick_rate 1077833305 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492819 # Number of instructions simulated -sim_seconds 0.868688 # Number of seconds simulated -sim_ticks 868687552500 # Number of ticks simulated +sim_insts 1495492697 # Number of instructions simulated +sim_seconds 0.868687 # Number of seconds simulated +sim_ticks 868687488000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737375106 # number of cpu cycles simulated -system.cpu.num_insts 1495492819 # Number of instructions executed -system.cpu.num_refs 533549003 # Number of memory references +system.cpu.numCycles 1737374977 # number of cpu cycles simulated +system.cpu.num_insts 1495492697 # Number of instructions executed +system.cpu.num_refs 533549000 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index 01ec1845d..03a15d3cc 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:35:20 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:20:39 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868687552500 because target called exit() +Exiting @ tick 868687488000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index 2e5af9606..891b17a00 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2125831 # Simulator instruction rate (inst/s) -host_mem_usage 194800 # Number of bytes of host memory used -host_seconds 2188.89 # Real time elapsed on the host -host_tick_rate 1295270570 # Simulator tick rate (ticks/s) +host_inst_rate 1763085 # Simulator instruction rate (inst/s) +host_mem_usage 194072 # Number of bytes of host memory used +host_seconds 2639.25 # Real time elapsed on the host +host_tick_rate 1074249302 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219908 # Number of instructions simulated +sim_insts 4653219791 # Number of instructions simulated sim_seconds 2.835211 # Number of seconds simulated -sim_ticks 2835211016000 # Number of ticks simulated +sim_ticks 2835210954000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5670422033 # number of cpu cycles simulated -system.cpu.num_insts 4653219908 # Number of instructions executed -system.cpu.num_refs 1686313784 # Number of memory references +system.cpu.numCycles 5670421909 # number of cpu cycles simulated +system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index 0939c6481..196cf8f42 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:36:52 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:55:01 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second spec_init @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2835211016000 because target called exit() +Exiting @ tick 2835210954000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index df2f6c498..c4fe4712d 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1393641 # Simulator instruction rate (inst/s) -host_mem_usage 201900 # Number of bytes of host memory used -host_seconds 156.85 # Real time elapsed on the host -host_tick_rate 828865190 # Simulator tick rate (ticks/s) +host_inst_rate 1300052 # Simulator instruction rate (inst/s) +host_mem_usage 201460 # Number of bytes of host memory used +host_seconds 168.14 # Real time elapsed on the host +host_tick_rate 773204086 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595439 # Number of instructions simulated +sim_insts 218595322 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009435500 # Number of ticks simulated +sim_ticks 130009373500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018872 # number of cpu cycles simulated -system.cpu.num_insts 218595439 # Number of instructions executed -system.cpu.num_refs 77165367 # Number of memory references +system.cpu.numCycles 260018748 # number of cpu cycles simulated +system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.num_refs 77165364 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index bb2f68a97..fcbdb82ed 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:41:47 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:20:39 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -25,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009435500 because target called exit() +122 123 124 Exiting @ tick 130009373500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index 296fe27ac..bacf33c33 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 67755 # Simulator instruction rate (inst/s) -host_mem_usage 190344 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 39312509 # Simulator tick rate (ticks/s) +host_inst_rate 8984 # Simulator instruction rate (inst/s) +host_mem_usage 189888 # Number of bytes of host memory used +host_seconds 1.06 # Real time elapsed on the host +host_tick_rate 5221453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9551 # Number of instructions simulated +sim_insts 9493 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5549000 # Number of ticks simulated +sim_ticks 5518000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11099 # number of cpu cycles simulated -system.cpu.num_insts 9551 # Number of instructions executed +system.cpu.numCycles 11037 # number of cpu cycles simulated +system.cpu.num_insts 9493 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index e89d3c49f..e87534cec 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:33:04 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:41:59 -M5 executing on piton +M5 compiled Oct 8 2008 20:20:37 +M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 +M5 commit date Wed Oct 08 20:18:02 2008 -0700 +M5 started Oct 8 2008 20:20:39 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5549000 because target called exit() +Exiting @ tick 5518000 because target called exit() -- cgit v1.2.3 From aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 20 Oct 2008 19:00:07 -0400 Subject: Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete. --- tests/SConscript | 3 +- tests/configs/tsunami-o3-dual.py | 99 ++ tests/configs/tsunami-o3.py | 98 ++ .../ref/alpha/linux/tsunami-o3-dual/config.ini | 1363 ++++++++++++++++++++ .../ref/alpha/linux/tsunami-o3-dual/m5stats.txt | 1123 ++++++++++++++++ .../ref/alpha/linux/tsunami-o3-dual/stderr | 5 + .../ref/alpha/linux/tsunami-o3-dual/stdout | 16 + .../alpha/linux/tsunami-o3-dual/system.terminal | 111 ++ .../ref/alpha/linux/tsunami-o3/config.ini | 1049 +++++++++++++++ .../ref/alpha/linux/tsunami-o3/m5stats.txt | 674 ++++++++++ .../ref/alpha/linux/tsunami-o3/stderr | 4 + .../ref/alpha/linux/tsunami-o3/stdout | 16 + .../ref/alpha/linux/tsunami-o3/system.terminal | 106 ++ tests/long/10.linux-boot/test.py | 29 + 14 files changed, 4695 insertions(+), 1 deletion(-) create mode 100644 tests/configs/tsunami-o3-dual.py create mode 100644 tests/configs/tsunami-o3.py create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt create mode 100755 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr create mode 100755 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt create mode 100755 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr create mode 100755 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout create mode 100644 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal create mode 100644 tests/long/10.linux-boot/test.py (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 984eaa97c..762262dfa 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -216,7 +216,8 @@ if env['FULL_SYSTEM']: 'tsunami-simple-timing', 'tsunami-simple-atomic-dual', 'tsunami-simple-timing-dual', - 'twosys-tsunami-simple-atomic'] + 'twosys-tsunami-simple-atomic', + 'tsunami-o3', 'tsunami-o3-dual'] if env['TARGET_ISA'] == 'sparc': configs += ['t1000-simple-atomic', 't1000-simple-timing'] diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py new file mode 100644 index 000000000..5dbfa5a8b --- /dev/null +++ b/tests/configs/tsunami-o3-dual.py @@ -0,0 +1,99 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +import FSConfig + + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + mem_side_filter_ranges=[AddrRange(0, Addr.max)] + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + +#cpu +cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] +#the system +system = FSConfig.makeLinuxAlphaSystem('timing') + +system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +for c in cpus: + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py new file mode 100644 index 000000000..ee60ea8ae --- /dev/null +++ b/tests/configs/tsunami-o3.py @@ -0,0 +1,98 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +import FSConfig + + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + mem_side_filter_ranges=[AddrRange(0, Addr.max)] + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + +#cpu +cpu = DerivO3CPU(cpu_id=0) +#the system +system = FSConfig.makeLinuxAlphaSystem('timing') + +system.cpu = cpu +#create the l1/l2 bus +system.toL2Bus = Bus() +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini new file mode 100644 index 000000000..dca62b55f --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -0,0 +1,1363 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxAlphaSystem +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +boot_cpu_frequency=500 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=timing +pal=/dist/m5/system/binaries/ts_osfpal +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +system_rev=1024 +system_type=34 + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:8589934591 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu0] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu0.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu0.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList4.opList + +[system.cpu0.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList5.opList + +[system.cpu0.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 + +[system.cpu0.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu0.fuPool.FUList7.opList + +[system.cpu0.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.interrupts] +type=AlphaInterrupts + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=1 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu1.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu1.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu1.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 + +[system.cpu1.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu1.fuPool.FUList0.opList + +[system.cpu1.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu1.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 + +[system.cpu1.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu1.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu1.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 + +[system.cpu1.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu1.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu1.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu1.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 + +[system.cpu1.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu1.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu1.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu1.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu1.fuPool.FUList4.opList + +[system.cpu1.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu1.fuPool.FUList5.opList + +[system.cpu1.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 + +[system.cpu1.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu1.fuPool.FUList7.opList + +[system.cpu1.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.interrupts] +type=AlphaInterrupts + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk0.image + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk2.image + +[system.disk2.image] +type=CowDiskImage +children=child +child=system.disk2.image.child +read_only=false +table_size=65536 + +[system.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=true +width=64 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges=549755813888:18446744073709551615 +hash_delay=1 +latency=50000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges=0:18446744073709551615 +mshrs=20 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[28] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.membus.responder.pio +port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.simple_disk] +type=SimpleDisk +children=disk +disk=system.simple_disk.disk +system=system + +[system.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + +[system.tsunami] +type=Tsunami +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=system.intrctrl +system=system + +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + +[system.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[1] + +[system.tsunami.ethernet] +type=NSGigE +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] + +[system.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[9] + +[system.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[20] + +[system.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[21] + +[system.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[10] + +[system.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[13] + +[system.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[18] + +[system.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[19] + +[system.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848891 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[8] + +[system.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[3] + +[system.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[4] + +[system.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[5] + +[system.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[6] + +[system.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[7] + +[system.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=system.tsunami +system=system +pio=system.iobus.port[22] + +[system.tsunami.ide] +type=IdeController +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] + +[system.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=system.tsunami +system=system +time=Thu Jan 1 00:00:00 2009 +tsunami=system.tsunami +year_is_bcd=false +pio=system.iobus.port[23] + +[system.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[2] + +[system.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.tsunami +size=16777216 +system=system +pio=system.iobus.default + +[system.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[24] + diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt new file mode 100644 index 000000000..39d149122 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt @@ -0,0 +1,1123 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 4974822 # Number of BTB hits +global.BPredUnit.BTBHits 2263931 # Number of BTB hits +global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups +global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups +global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions. +global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect +global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted +global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted +global.BPredUnit.lookups 10092697 # Number of BP lookups +global.BPredUnit.lookups 5530798 # Number of BP lookups +global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. +global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. +host_inst_rate 132625 # Simulator instruction rate (inst/s) +host_mem_usage 292844 # Number of bytes of host memory used +host_seconds 423.41 # Real time elapsed on the host +host_tick_rate 4505618304 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 56154063 # Number of instructions simulated +sim_seconds 1.907705 # Number of seconds simulated +sim_ticks 1907705350500 # Number of ticks simulated +system.cpu0.commit.COM:branches 5979955 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle.samples 69429521 +system.cpu0.commit.COM:committed_per_cycle.min_value 0 + 0 52132882 7508.75% + 1 7659816 1103.25% + 2 4444319 640.12% + 3 2023012 291.38% + 4 1474688 212.40% + 5 453462 65.31% + 6 276660 39.85% + 7 294053 42.35% + 8 670629 96.59% +system.cpu0.commit.COM:committed_per_cycle.max_value 8 +system.cpu0.commit.COM:committed_per_cycle.end_dist + +system.cpu0.commit.COM:count 39866915 # Number of instructions committed +system.cpu0.commit.COM:loads 6404567 # Number of loads committed +system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed +system.cpu0.commit.COM:refs 10831807 # Number of memory references committed +system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 37661300 # Number of Instructions Simulated +system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated +system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 8080450 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2592009 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 922698 # number of replacements +system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 297324 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking +system.cpu0.dtb.accesses 812630 # DTB accesses +system.cpu0.dtb.acv 800 # DTB access violations +system.cpu0.dtb.hits 11624529 # DTB hits +system.cpu0.dtb.misses 28502 # DTB misses +system.cpu0.dtb.read_accesses 605275 # DTB read accesses +system.cpu0.dtb.read_acv 596 # DTB read access violations +system.cpu0.dtb.read_hits 7062851 # DTB read hits +system.cpu0.dtb.read_misses 24043 # DTB read misses +system.cpu0.dtb.write_accesses 207355 # DTB write accesses +system.cpu0.dtb.write_acv 204 # DTB write access violations +system.cpu0.dtb.write_hits 4561678 # DTB write hits +system.cpu0.dtb.write_misses 4459 # DTB write misses +system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist.samples 70522996 +system.cpu0.fetch.rateDist.min_value 0 + 0 60301622 8550.63% + 1 760699 107.87% + 2 1434176 203.36% + 3 635243 90.08% + 4 2330465 330.45% + 5 474381 67.27% + 6 552250 78.31% + 7 815542 115.64% + 8 3218618 456.39% +system.cpu0.fetch.rateDist.max_value 8 +system.cpu0.fetch.rateDist.end_dist + +system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.489789 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 7526812999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses +system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 7526812999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 5806036 # number of overall hits +system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses +system.cpu0.icache.overall_misses 650298 # number of overall misses +system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 7526812999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 619824 # number of replacements +system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use +system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idleCycles 30377938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate +system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed +system.cpu0.iew.EXEC:swp 0 # number of swp insts executed +system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value +system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back +system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.iew.WB:producers 18821888 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle +system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking +system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3324 0.01% # Type of FU issued + IntAlu 28266314 68.97% # Type of FU issued + IntMult 42210 0.10% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 12073 0.03% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1656 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 7397265 18.05% # Type of FU issued + MemWrite 4611960 11.25% # Type of FU issued + IprAccess 650122 1.59% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 33477 11.53% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 185557 63.91% # attempts to use FU when none available + MemWrite 71326 24.56% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full.end_dist +system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996 +system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 + 0 49763845 7056.40% + 1 10504305 1489.49% + 2 4625788 655.93% + 3 2839071 402.57% + 4 1729907 245.30% + 5 663571 94.09% + 6 315326 44.71% + 7 67073 9.51% + 8 14110 2.00% +system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu0.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate +system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.itb.accesses 875611 # ITB accesses +system.cpu0.itb.acv 895 # ITB acv +system.cpu0.itb.hits 845707 # ITB hits +system.cpu0.itb.misses 29904 # ITB misses +system.cpu0.kern.callpal 129595 # number of callpals executed +system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed +system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed +system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed +system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed +system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871607297000 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397999500 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1284 +system.cpu0.kern.mode_good_user 1284 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2411 # number of times the context was actually changed +system.cpu0.kern.syscall 222 # number of syscalls executed +system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.numCycles 100900934 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed +system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.commit.COM:branches 2941268 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached +system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle.samples 37417437 +system.cpu1.commit.COM:committed_per_cycle.min_value 0 + 0 29372798 7850.03% + 1 3570649 954.27% + 2 1730450 462.47% + 3 1048421 280.20% + 4 705992 188.68% + 5 261184 69.80% + 6 182468 48.77% + 7 141194 37.73% + 8 404281 108.05% +system.cpu1.commit.COM:committed_per_cycle.max_value 8 +system.cpu1.commit.COM:committed_per_cycle.end_dist + +system.cpu1.commit.COM:count 19624114 # Number of instructions committed +system.cpu1.commit.COM:loads 3545101 # Number of loads committed +system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5853378 # Number of memory references committed +system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 18492763 # Number of Instructions Simulated +system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated +system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 49361.667333 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.267300 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 34265289889 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 7736833634 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33109.914913 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44248421389 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 12908645134 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33109.914913 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 4480566 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44248421389 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 1336410 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 12908645134 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 531824 # number of replacements +system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 158256 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 17763600 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14707751 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking +system.cpu1.dtb.accesses 434054 # DTB accesses +system.cpu1.dtb.acv 76 # DTB access violations +system.cpu1.dtb.hits 6272530 # DTB hits +system.cpu1.dtb.misses 17149 # DTB misses +system.cpu1.dtb.read_accesses 314239 # DTB read accesses +system.cpu1.dtb.read_acv 13 # DTB read access violations +system.cpu1.dtb.read_hits 3866975 # DTB read hits +system.cpu1.dtb.read_misses 13433 # DTB read misses +system.cpu1.dtb.write_accesses 119815 # DTB write accesses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_hits 2405555 # DTB write hits +system.cpu1.dtb.write_misses 3716 # DTB write misses +system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched +system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist.samples 38058468 +system.cpu1.fetch.rateDist.min_value 0 + 0 33027825 8678.18% + 1 336540 88.43% + 2 683303 179.54% + 3 398795 104.78% + 4 792602 208.26% + 5 252574 66.36% + 6 340311 89.42% + 7 403731 106.08% + 8 1822787 478.94% +system.cpu1.fetch.rateDist.max_value 8 +system.cpu1.fetch.rateDist.end_dist + +system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14557.233772 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.243441 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6814080999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5188832000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14557.233772 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency +system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6814080999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses +system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5188832000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14557.233772 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 2613676 # number of overall hits +system.cpu1.icache.overall_miss_latency 6814080999 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses +system.cpu1.icache.overall_misses 468089 # number of overall misses +system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5188832000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 446548 # number of replacements +system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use +system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idleCycles 4701181 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed +system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate +system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed +system.cpu1.iew.EXEC:swp 0 # number of swp insts executed +system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value +system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back +system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.iew.WB:producers 9033918 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle +system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking +system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3984 0.02% # Type of FU issued + IntAlu 13446211 65.50% # Type of FU issued + IntMult 28837 0.14% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 13702 0.07% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1986 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 4170434 20.32% # Type of FU issued + MemWrite 2440876 11.89% # Type of FU issued + IprAccess 421203 2.05% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.end_dist +system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 16051 7.28% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 131548 59.63% # attempts to use FU when none available + MemWrite 73016 33.10% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full.end_dist +system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058468 +system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 + 0 28368883 7454.03% + 1 4650018 1221.81% + 2 1988549 522.50% + 3 1356758 356.49% + 4 973103 255.69% + 5 468416 123.08% + 6 186236 48.93% + 7 54105 14.22% + 8 12400 3.26% +system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu1.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.itb.accesses 525300 # ITB accesses +system.cpu1.itb.acv 103 # ITB acv +system.cpu1.itb.hits 518475 # ITB hits +system.cpu1.itb.misses 6825 # ITB misses +system.cpu1.kern.callpal 87347 # number of callpals executed +system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed +system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed +system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed +system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed +system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed +system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 521 +system.cpu1.kern.mode_good_user 463 +system.cpu1.kern.mode_good_idle 58 +system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches +system.cpu1.kern.mode_switch_user 463 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1839 # number of times the context was actually changed +system.cpu1.kern.syscall 104 # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.numCycles 42759649 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 15176070 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12475543 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed +system.cpu1.timesIdled 480243 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 175 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41697 # number of replacements +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.387818 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41522 # number of writebacks +system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1893933 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310350 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 455580 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.836093 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.demand_hits 1893933 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses +system.l2c.demand_misses 627845 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1893933 # number of overall hits +system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles +system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses +system.l2c.overall_misses 627845 # number of overall misses +system.l2c.overall_mshr_hits 17 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 402113 # number of replacements +system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 31146.703912 # Cycle average of tags in use +system.l2c.total_refs 2097138 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124275 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr new file mode 100755 index 000000000..4cafe060d --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr @@ -0,0 +1,5 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: 125740500: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout new file mode 100755 index 000000000..974343499 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 20 2008 18:39:58 +M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6 +M5 commit date Sun Oct 19 22:50:53 2008 -0400 +M5 started Oct 20 2008 18:47:58 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1907705350500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal new file mode 100644 index 000000000..d5c08c61f --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -0,0 +1,111 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 2 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 + Bootstraping CPU 1 with sp=0xFFFFFC0000076000 + unix_boot_mem ends at FFFFFC0000078000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + 4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles + SMP: 2 CPUs probed -- cpu_present_mask = 3 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP starting up secondaries. + Slave CPU 1 console command START +SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 + Brought up 2 CPUs + SMP: Total of 2 processors activated (8000.15 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini new file mode 100644 index 000000000..808108731 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -0,0 +1,1049 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +boot_cpu_frequency=500 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=timing +pal=/dist/m5/system/binaries/ts_osfpal +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +system_rev=1024 +system_type=34 + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:8589934591 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList5.opList + +[system.cpu.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList7.opList + +[system.cpu.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=AlphaInterrupts + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk0.image + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk2.image + +[system.disk2.image] +type=CowDiskImage +children=child +child=system.disk2.image.child +read_only=false +table_size=65536 + +[system.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=true +width=64 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges=549755813888:18446744073709551615 +hash_delay=1 +latency=50000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges=0:18446744073709551615 +mshrs=20 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[28] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.membus.responder.pio +port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.simple_disk] +type=SimpleDisk +children=disk +disk=system.simple_disk.disk +system=system + +[system.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + +[system.tsunami] +type=Tsunami +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=system.intrctrl +system=system + +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + +[system.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[1] + +[system.tsunami.ethernet] +type=NSGigE +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] + +[system.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[9] + +[system.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[20] + +[system.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[21] + +[system.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[10] + +[system.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[13] + +[system.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[18] + +[system.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[19] + +[system.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848891 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[8] + +[system.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[3] + +[system.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[4] + +[system.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[5] + +[system.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[6] + +[system.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[7] + +[system.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=system.tsunami +system=system +pio=system.iobus.port[22] + +[system.tsunami.ide] +type=IdeController +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] + +[system.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=system.tsunami +system=system +time=Thu Jan 1 00:00:00 2009 +tsunami=system.tsunami +year_is_bcd=false +pio=system.iobus.port[23] + +[system.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[2] + +[system.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.tsunami +size=16777216 +system=system +pio=system.iobus.default + +[system.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[24] + diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt new file mode 100644 index 000000000..094233a29 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt @@ -0,0 +1,674 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 6932487 # Number of BTB hits +global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups +global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted +global.BPredUnit.lookups 14559443 # Number of BP lookups +global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. +host_inst_rate 211094 # Simulator instruction rate (inst/s) +host_mem_usage 290796 # Number of bytes of host memory used +host_seconds 251.32 # Real time elapsed on the host +host_tick_rate 7430116049 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 53052618 # Number of instructions simulated +sim_seconds 1.867359 # Number of seconds simulated +sim_ticks 1867358550500 # Number of ticks simulated +system.cpu.commit.COM:branches 8455188 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 100543308 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 76317924 7590.55% + 1 10743540 1068.55% + 2 5987880 595.55% + 3 2987787 297.16% + 4 2072579 206.14% + 5 671161 66.75% + 6 395328 39.32% + 7 393271 39.11% + 8 973838 96.86% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 56244351 # Number of instructions committed +system.cpu.commit.COM:loads 9302477 # Number of loads committed +system.cpu.commit.COM:membars 227741 # Number of memory barriers committed +system.cpu.commit.COM:refs 15692393 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53052618 # Number of Instructions Simulated +system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated +system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 11726365 # number of overall hits +system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3763307 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1402096 # number of replacements +system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use +system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430429 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 1229941 # DTB accesses +system.cpu.dtb.acv 828 # DTB access violations +system.cpu.dtb.hits 16757791 # DTB hits +system.cpu.dtb.misses 44378 # DTB misses +system.cpu.dtb.read_accesses 908364 # DTB read accesses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_hits 10166755 # DTB read hits +system.cpu.dtb.read_misses 36227 # DTB read misses +system.cpu.dtb.write_accesses 321577 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6591036 # DTB write hits +system.cpu.dtb.write_misses 8151 # DTB write misses +system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched +system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 102189280 +system.cpu.fetch.rateDist.min_value 0 + 0 87752503 8587.25% + 1 1049427 102.69% + 2 2020193 197.69% + 3 968502 94.78% + 4 3001129 293.68% + 5 683878 66.92% + 6 831667 81.38% + 7 1217349 119.13% + 8 4664632 456.47% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 7948798 # number of overall hits +system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047360 # number of overall misses +system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 994691 # number of replacements +system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use +system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9157080 # Number of branches executed +system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate +system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6614103 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value +system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 26369407 # num instructions producing a value +system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle +system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 7284 0.01% # Type of FU issued + IntAlu 39585322 68.15% # Type of FU issued + IntMult 61995 0.11% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 25609 0.04% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 3636 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 10781907 18.56% # Type of FU issued + MemWrite 6666291 11.48% # Type of FU issued + IprAccess 953214 1.64% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 52004 11.98% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 278726 64.23% # attempts to use FU when none available + MemWrite 103217 23.79% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 73101546 7153.54% + 1 14613738 1430.07% + 2 6411296 627.39% + 3 3930297 384.61% + 4 2526857 247.27% + 5 1033193 101.11% + 6 443511 43.40% + 7 107158 10.49% + 8 21684 2.12% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate +system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1300570 # ITB accesses +system.cpu.itb.acv 941 # ITB acv +system.cpu.itb.hits 1261136 # ITB hits +system.cpu.itb.misses 39434 # ITB misses +system.cpu.kern.callpal 192636 # number of callpals executed +system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1741 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches +system.cpu.kern.mode_switch_user 1741 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.numCycles 136890724 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed +system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41685 # number of replacements +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 1.267378 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41512 # number of writebacks +system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1786309 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311028 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430429 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.demand_hits 1786309 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses +system.l2c.demand_misses 611623 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1786309 # number of overall hits +system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses +system.l2c.overall_misses 611623 # number of overall misses +system.l2c.overall_mshr_hits 1 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 396037 # number of replacements +system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use +system.l2c.total_refs 1966986 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119087 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr new file mode 100755 index 000000000..1a557daf8 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr @@ -0,0 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout new file mode 100755 index 000000000..3c523295b --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 20 2008 18:39:58 +M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6 +M5 commit date Sun Oct 19 22:50:53 2008 -0400 +M5 started Oct 20 2008 18:47:58 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1867358550500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal new file mode 100644 index 000000000..8a13d1a5e --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -0,0 +1,106 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 2000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + 4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (4002.20 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary +mounting filesystems... +EXT2-fs warning: checktime reached, running e2fsck is recommended + loading script... diff --git a/tests/long/10.linux-boot/test.py b/tests/long/10.linux-boot/test.py new file mode 100644 index 000000000..215d63700 --- /dev/null +++ b/tests/long/10.linux-boot/test.py @@ -0,0 +1,29 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +root.system.readfile = os.path.join(tests_root, 'halt.sh') -- cgit v1.2.3 From 2435918ac28b1401fcd7bb1114e62a7a6f2310a9 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 5 Nov 2008 18:10:30 -0500 Subject: new mp eio test --- tests/SConscript | 3 +- .../ref/alpha/eio/simple-atomic-mp/config.ini | 526 +++++++++++++++ .../ref/alpha/eio/simple-atomic-mp/m5stats.txt | 627 ++++++++++++++++++ .../ref/alpha/eio/simple-atomic-mp/stderr | 13 + .../ref/alpha/eio/simple-atomic-mp/stdout | 24 + .../ref/alpha/eio/simple-timing-mp/config.ini | 514 +++++++++++++++ .../ref/alpha/eio/simple-timing-mp/m5stats.txt | 717 +++++++++++++++++++++ .../ref/alpha/eio/simple-timing-mp/stderr | 13 + .../ref/alpha/eio/simple-timing-mp/stdout | 24 + tests/quick/30.eio-mp/test.py | 33 + 10 files changed, 2493 insertions(+), 1 deletion(-) create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr create mode 100644 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout create mode 100644 tests/quick/30.eio-mp/test.py (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 762262dfa..3e0eed941 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -223,7 +223,8 @@ if env['FULL_SYSTEM']: 't1000-simple-timing'] else: - configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest'] + configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest', + 'simple-atomic-mp', 'simple-timing-mp'] cwd = os.getcwd() os.chdir(str(Dir('.').srcdir)) diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini new file mode 100644 index 000000000..78394da28 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -0,0 +1,526 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=1 +defer_registration=false +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=2 +defer_registration=false +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=3 +defer_registration=false +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt new file mode 100644 index 000000000..5a19ce746 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt @@ -0,0 +1,627 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1660926 # Simulator instruction rate (inst/s) +host_seconds 1.20 # Real time elapsed on the host +host_tick_rate 207598549 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2000004 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180793 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180775 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124435 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56340 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499556 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500032 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500019 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 182222 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180140 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180793 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180775 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124435 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56350 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56340 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499556 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500032 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 500019 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.num_insts 500001 # Number of instructions executed +system.cpu1.num_refs 182222 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499556 # number of overall hits +system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500032 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500019 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180140 # number of overall hits +system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180793 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180775 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124443 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124435 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56350 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56340 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499556 # number of overall hits +system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500032 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500019 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.num_insts 500001 # Number of instructions executed +system.cpu3.num_refs 182222 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr new file mode 100644 index 000000000..e0d5d4d73 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr @@ -0,0 +1,13 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout new file mode 100644 index 000000000..b79194a00 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 17:12:56 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 17:19:26 +M5 executing on dhcp128036150089.central.yale.edu +command line: build/ALPHA_SE/m5.fast -d simple-atomic wrapper.py +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini new file mode 100644 index 000000000..0077a0004 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -0,0 +1,514 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=1 +defer_registration=false +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=2 +defer_registration=false +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=3 +defer_registration=false +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt new file mode 100644 index 000000000..d00f39e87 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt @@ -0,0 +1,717 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 803390 # Simulator instruction rate (inst/s) +host_seconds 2.49 # Real time elapsed on the host +host_tick_rate 296594923 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1999941 # Number of instructions simulated +sim_seconds 0.000738 # Number of seconds simulated +sim_ticks 738387000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180136 # number of overall hits +system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180789 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180771 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124440 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124432 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56349 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56339 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499537 # number of overall hits +system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use +system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500013 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500000 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 1476774 # number of cpu cycles simulated +system.cpu0.num_insts 499981 # Number of instructions executed +system.cpu0.num_refs 182218 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180133 # number of overall hits +system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180786 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180768 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124437 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124429 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56349 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56339 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499531 # number of overall hits +system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use +system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500007 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 499994 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 1476774 # number of cpu cycles simulated +system.cpu1.num_insts 499975 # Number of instructions executed +system.cpu1.num_refs 182214 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499557 # number of overall hits +system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500033 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500020 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 1476774 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180137 # number of overall hits +system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180790 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180772 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124441 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124433 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56349 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56339 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499540 # number of overall hits +system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use +system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500016 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500003 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 1476774 # number of cpu cycles simulated +system.cpu3.num_insts 499984 # Number of instructions executed +system.cpu3.num_refs 182219 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 178284000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr new file mode 100644 index 000000000..e0d5d4d73 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr @@ -0,0 +1,13 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout new file mode 100644 index 000000000..2976be712 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 17:12:56 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 17:26:45 +M5 executing on dhcp128036150089.central.yale.edu +command line: build/ALPHA_SE/m5.fast -d output wrapper.py +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 738387000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/test.py b/tests/quick/30.eio-mp/test.py new file mode 100644 index 000000000..3dbb7614a --- /dev/null +++ b/tests/quick/30.eio-mp/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) + +for i in xrange(nb_cores): + root.system.cpu[i].workload = process() + root.system.cpu[i].max_insts_any_thread = 500000 -- cgit v1.2.3 From ddd179a4189d6f51f7be81567e1119aa67533dae Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 6 Nov 2008 11:11:42 -0500 Subject: Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. --- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 9 - .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 1 - .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../00.gzip/ref/alpha/tru64/simple-atomic/stderr | 1 - .../00.gzip/ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../00.gzip/ref/alpha/tru64/simple-timing/stderr | 1 - .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 11 +- .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 9 - .../00.gzip/ref/sparc/linux/o3-timing/m5stats.txt | 8 +- .../long/00.gzip/ref/sparc/linux/o3-timing/stderr | 2 +- .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 11 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../00.gzip/ref/sparc/linux/simple-atomic/stderr | 2 +- .../00.gzip/ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 8 +- .../00.gzip/ref/sparc/linux/simple-timing/stderr | 2 +- .../00.gzip/ref/sparc/linux/simple-timing/stdout | 11 +- .../ref/x86/linux/simple-atomic/m5stats.txt | 8 +- .../00.gzip/ref/x86/linux/simple-atomic/stderr | 2 +- .../00.gzip/ref/x86/linux/simple-atomic/stdout | 11 +- .../ref/alpha/linux/tsunami-o3-dual/config.ini | 18 -- .../ref/alpha/linux/tsunami-o3-dual/m5stats.txt | 102 +++---- .../ref/alpha/linux/tsunami-o3-dual/stdout | 8 +- .../ref/alpha/linux/tsunami-o3/config.ini | 12 - .../ref/alpha/linux/tsunami-o3/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-o3/stdout | 8 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../10.mcf/ref/sparc/linux/simple-atomic/stderr | 2 +- .../10.mcf/ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 8 +- .../10.mcf/ref/sparc/linux/simple-timing/stderr | 2 +- .../10.mcf/ref/sparc/linux/simple-timing/stdout | 11 +- .../10.mcf/ref/x86/linux/simple-atomic/m5stats.txt | 8 +- .../long/10.mcf/ref/x86/linux/simple-atomic/stderr | 2 +- .../long/10.mcf/ref/x86/linux/simple-atomic/stdout | 11 +- .../ref/x86/linux/simple-atomic/m5stats.txt | 16 +- .../20.parser/ref/x86/linux/simple-atomic/stderr | 2 +- .../20.parser/ref/x86/linux/simple-atomic/stdout | 13 +- .../30.eon/ref/alpha/tru64/o3-timing/config.ini | 9 - .../30.eon/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr | 1 - tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../30.eon/ref/alpha/tru64/simple-atomic/stderr | 1 - .../30.eon/ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../30.eon/ref/alpha/tru64/simple-timing/stderr | 1 - .../30.eon/ref/alpha/tru64/simple-timing/stdout | 11 +- .../ref/alpha/tru64/o3-timing/config.ini | 9 - .../ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../40.perlbmk/ref/alpha/tru64/o3-timing/stderr | 1 - .../40.perlbmk/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-atomic/stderr | 1 - .../ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/stderr | 1 - .../ref/alpha/tru64/simple-timing/stdout | 11 +- .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 9 - .../ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../50.vortex/ref/alpha/tru64/o3-timing/stderr | 1 - .../50.vortex/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../50.vortex/ref/alpha/tru64/simple-atomic/stderr | 1 - .../50.vortex/ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../50.vortex/ref/alpha/tru64/simple-timing/stderr | 1 - .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 11 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../50.vortex/ref/sparc/linux/simple-atomic/stderr | 2 +- .../50.vortex/ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 8 +- .../50.vortex/ref/sparc/linux/simple-timing/stderr | 2 +- .../50.vortex/ref/sparc/linux/simple-timing/stdout | 11 +- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 9 - .../60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt | 332 ++++++++++----------- .../long/60.bzip2/ref/alpha/tru64/o3-timing/stderr | 1 - .../long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../60.bzip2/ref/alpha/tru64/simple-atomic/stderr | 1 - .../60.bzip2/ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../60.bzip2/ref/alpha/tru64/simple-timing/stderr | 1 - .../60.bzip2/ref/alpha/tru64/simple-timing/stdout | 11 +- .../ref/x86/linux/simple-atomic/m5stats.txt | 8 +- .../60.bzip2/ref/x86/linux/simple-atomic/stderr | 2 +- .../60.bzip2/ref/x86/linux/simple-atomic/stdout | 11 +- .../70.twolf/ref/alpha/tru64/o3-timing/config.ini | 9 - .../70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../long/70.twolf/ref/alpha/tru64/o3-timing/stderr | 1 - .../long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 13 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../70.twolf/ref/alpha/tru64/simple-atomic/stderr | 1 - .../70.twolf/ref/alpha/tru64/simple-atomic/stdout | 13 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../70.twolf/ref/alpha/tru64/simple-timing/stderr | 1 - .../70.twolf/ref/alpha/tru64/simple-timing/stdout | 13 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../70.twolf/ref/sparc/linux/simple-atomic/stderr | 2 +- .../70.twolf/ref/sparc/linux/simple-atomic/stdout | 13 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 8 +- .../70.twolf/ref/sparc/linux/simple-timing/stderr | 2 +- .../70.twolf/ref/sparc/linux/simple-timing/stdout | 13 +- .../ref/x86/linux/simple-atomic/m5stats.txt | 8 +- .../70.twolf/ref/x86/linux/simple-atomic/stderr | 2 +- .../70.twolf/ref/x86/linux/simple-atomic/stdout | 11 +- .../sparc/solaris/t1000-simple-atomic/config.ini | 6 +- .../sparc/solaris/t1000-simple-atomic/m5stats.txt | 8 +- .../ref/sparc/solaris/t1000-simple-atomic/stderr | 2 +- .../ref/sparc/solaris/t1000-simple-atomic/stdout | 11 +- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 9 - .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 6 +- .../00.hello/ref/alpha/linux/o3-timing/stderr | 2 +- .../00.hello/ref/alpha/linux/o3-timing/stdout | 11 +- .../ref/alpha/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/alpha/linux/simple-atomic/stderr | 2 +- .../00.hello/ref/alpha/linux/simple-atomic/stdout | 11 +- .../ref/alpha/linux/simple-timing/config.ini | 9 - .../ref/alpha/linux/simple-timing/m5stats.txt | 6 +- .../00.hello/ref/alpha/linux/simple-timing/stderr | 2 +- .../00.hello/ref/alpha/linux/simple-timing/stdout | 11 +- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 9 - .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/o3-timing/stderr | 2 +- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 11 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-atomic/stderr | 2 +- .../00.hello/ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 9 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-timing/stderr | 2 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 11 +- .../ref/mips/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/mips/linux/simple-atomic/stderr | 2 +- .../00.hello/ref/mips/linux/simple-atomic/stdout | 11 +- .../ref/mips/linux/simple-timing/config.ini | 9 - .../ref/mips/linux/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/mips/linux/simple-timing/stderr | 2 +- .../00.hello/ref/mips/linux/simple-timing/stdout | 11 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/sparc/linux/simple-atomic/stderr | 2 +- .../00.hello/ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/sparc/linux/simple-timing/stderr | 2 +- .../00.hello/ref/sparc/linux/simple-timing/stdout | 11 +- .../ref/x86/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/x86/linux/simple-atomic/stderr | 2 +- .../00.hello/ref/x86/linux/simple-atomic/stdout | 11 +- .../ref/alpha/linux/o3-timing/config.ini | 9 - .../ref/alpha/linux/o3-timing/m5stats.txt | 8 +- .../ref/alpha/linux/o3-timing/stderr | 2 +- .../ref/alpha/linux/o3-timing/stdout | 11 +- .../ref/sparc/linux/o3-timing/config.ini | 9 - .../ref/sparc/linux/o3-timing/m5stats.txt | 8 +- .../02.insttest/ref/sparc/linux/o3-timing/stderr | 2 +- .../02.insttest/ref/sparc/linux/o3-timing/stdout | 11 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../ref/sparc/linux/simple-atomic/stderr | 2 +- .../ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 9 - .../ref/sparc/linux/simple-timing/m5stats.txt | 6 +- .../ref/sparc/linux/simple-timing/stderr | 2 +- .../ref/sparc/linux/simple-timing/stdout | 11 +- .../linux/tsunami-simple-atomic-dual/config.ini | 30 +- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 8 +- .../alpha/linux/tsunami-simple-atomic-dual/stderr | 2 +- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 11 +- .../alpha/linux/tsunami-simple-atomic/config.ini | 18 +- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-simple-atomic/stderr | 2 +- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 11 +- .../linux/tsunami-simple-timing-dual/config.ini | 30 +- .../linux/tsunami-simple-timing-dual/m5stats.txt | 8 +- .../alpha/linux/tsunami-simple-timing-dual/stderr | 2 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 11 +- .../alpha/linux/tsunami-simple-timing/config.ini | 18 +- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-simple-timing/stderr | 2 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 11 +- .../ref/alpha/eio/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/eio/simple-atomic/stderr | 2 +- .../ref/alpha/eio/simple-atomic/stdout | 11 +- .../ref/alpha/eio/simple-timing/config.ini | 9 - .../ref/alpha/eio/simple-timing/m5stats.txt | 8 +- .../ref/alpha/eio/simple-timing/stderr | 2 +- .../ref/alpha/eio/simple-timing/stdout | 11 +- .../50.memtest/ref/alpha/linux/memtest/config.ini | 27 -- .../50.memtest/ref/alpha/linux/memtest/m5stats.txt | 6 +- .../50.memtest/ref/alpha/linux/memtest/stderr | 2 +- .../50.memtest/ref/alpha/linux/memtest/stdout | 11 +- .../linux/twosys-tsunami-simple-atomic/config.ini | 16 +- .../linux/twosys-tsunami-simple-atomic/m5stats.txt | 14 +- .../linux/twosys-tsunami-simple-atomic/stderr | 2 +- .../linux/twosys-tsunami-simple-atomic/stdout | 11 +- 208 files changed, 884 insertions(+), 1160 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2cac9c854..65280a84c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index c09103f51..8e02b536f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4206850 # Nu global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted global.BPredUnit.lookups 76039028 # Number of BP lookups global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 225803 # Simulator instruction rate (inst/s) -host_mem_usage 201396 # Number of bytes of host memory used -host_seconds 2504.62 # Real time elapsed on the host -host_tick_rate 66707870 # Simulator tick rate (ticks/s) +host_inst_rate 204243 # Simulator instruction rate (inst/s) +host_mem_usage 202188 # Number of bytes of host memory used +host_seconds 2769.01 # Real time elapsed on the host +host_tick_rate 60338522 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index e18bd34ec..8133509b4 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:09:41 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 21:40:15 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index c668a0459..c226b8d4c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2906348 # Simulator instruction rate (inst/s) -host_mem_usage 174252 # Number of bytes of host memory used -host_seconds 207.08 # Real time elapsed on the host -host_tick_rate 1453183573 # Simulator tick rate (ticks/s) +host_inst_rate 3818661 # Simulator instruction rate (inst/s) +host_mem_usage 193720 # Number of bytes of host memory used +host_seconds 157.61 # Real time elapsed on the host +host_tick_rate 1909343313 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 5da808ef6..63dd02070 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:12:32 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:05:35 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index cbfde3c7a..9d3e94dd6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5ddd02f93..cf41fab83 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1676744 # Simulator instruction rate (inst/s) -host_mem_usage 200380 # Number of bytes of host memory used -host_seconds 358.94 # Real time elapsed on the host -host_tick_rate 2167478980 # Simulator tick rate (ticks/s) +host_inst_rate 1993278 # Simulator instruction rate (inst/s) +host_mem_usage 201176 # Number of bytes of host memory used +host_seconds 301.94 # Real time elapsed on the host +host_tick_rate 2576653236 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index ccbbe4b14..7bb6940cc 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:14:02 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:08:13 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 497d0c7b3..4b4d2436b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 38b460055..b1499e0a2 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 83681535 # Nu global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted global.BPredUnit.lookups 254458067 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 99984 # Simulator instruction rate (inst/s) -host_mem_usage 203500 # Number of bytes of host memory used -host_seconds 14058.38 # Real time elapsed on the host -host_tick_rate 78434309 # Simulator tick rate (ticks/s) +host_inst_rate 116972 # Simulator instruction rate (inst/s) +host_mem_usage 204276 # Number of bytes of host memory used +host_seconds 12016.73 # Real time elapsed on the host +host_tick_rate 91760367 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index 168a468b1..cf3fc26c2 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:21:26 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:58 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index 7483949da..6ee039121 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4187360 # Simulator instruction rate (inst/s) -host_mem_usage 206704 # Number of bytes of host memory used -host_seconds 355.72 # Real time elapsed on the host -host_tick_rate 2093685937 # Simulator tick rate (ticks/s) +host_inst_rate 2833353 # Simulator instruction rate (inst/s) +host_mem_usage 195884 # Number of bytes of host memory used +host_seconds 525.71 # Real time elapsed on the host +host_tick_rate 1416680719 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index 9aba34a0b..959e9811f 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:22:26 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:45:38 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 550c53eb7..2760624c7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index da605e80a..21ee70af0 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1927863 # Simulator instruction rate (inst/s) -host_mem_usage 202560 # Number of bytes of host memory used -host_seconds 772.63 # Real time elapsed on the host -host_tick_rate 2692643700 # Simulator tick rate (ticks/s) +host_inst_rate 2121797 # Simulator instruction rate (inst/s) +host_mem_usage 203340 # Number of bytes of host memory used +host_seconds 702.01 # Real time elapsed on the host +host_tick_rate 2963511011 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.080416 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index fbc427ffb..696328daa 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:25:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:13 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt index e1904a94f..4f9664bbc 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1864345 # Simulator instruction rate (inst/s) -host_mem_usage 194404 # Number of bytes of host memory used -host_seconds 868.62 # Real time elapsed on the host -host_tick_rate 1108605034 # Simulator tick rate (ticks/s) +host_inst_rate 1613706 # Simulator instruction rate (inst/s) +host_mem_usage 195008 # Number of bytes of host memory used +host_seconds 1003.53 # Real time elapsed on the host +host_tick_rate 959566027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619398860 # Number of instructions simulated sim_seconds 0.962952 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr index c07fe7d68..12f446c64 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented warn: instruction 'prefetch_t0' unimplemented @@ -7,3 +6,4 @@ warn: instruction 'prefetch_t0' unimplemented warn: instruction 'prefetch_t0' unimplemented warn: instruction 'prefetch_t0' unimplemented warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout index 92309e31c..7b8dadcc0 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:20:39 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:03:28 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index dca62b55f..e35ca8bb4 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -132,7 +132,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -150,8 +149,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -309,7 +306,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -327,8 +323,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -446,7 +440,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -464,8 +457,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -623,7 +614,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -641,8 +631,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -722,7 +710,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -740,8 +727,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -758,7 +743,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -776,8 +760,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt index 39d149122..c498474d4 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt @@ -16,10 +16,10 @@ global.BPredUnit.lookups 10092697 # Nu global.BPredUnit.lookups 5530798 # Number of BP lookups global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 132625 # Simulator instruction rate (inst/s) -host_mem_usage 292844 # Number of bytes of host memory used -host_seconds 423.41 # Real time elapsed on the host -host_tick_rate 4505618304 # Simulator tick rate (ticks/s) +host_inst_rate 130617 # Simulator instruction rate (inst/s) +host_mem_usage 292856 # Number of bytes of host memory used +host_seconds 429.91 # Real time elapsed on the host +host_tick_rate 4437424208 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. @@ -211,13 +211,13 @@ system.cpu0.fetch.rateDist.end_dist system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.489789 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526812999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked @@ -230,13 +230,13 @@ system.cpu0.icache.blocked_cycles_no_targets 0 system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526812999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed @@ -244,14 +244,14 @@ system.cpu0.icache.mshr_cap_events 0 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 5806036 # number of overall hits system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses system.cpu0.icache.overall_misses 650298 # number of overall misses system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526812999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -272,7 +272,7 @@ system.cpu0.icache.tagsinuse 509.829045 # Cy system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30377938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate @@ -413,9 +413,9 @@ system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # nu system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871607297000 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 397999500 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl @@ -467,7 +467,7 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.numCycles 100900934 # number of cpu cycles simulated +system.cpu0.numCycles 100900932 # number of cpu cycles simulated system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full @@ -490,9 +490,9 @@ system.cpu1.commit.COM:branches 2941268 # Nu system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37417437 +system.cpu1.commit.COM:committed_per_cycle.samples 37417436 system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29372798 7850.03% + 0 29372797 7850.03% 1 3570649 954.27% 2 1730450 462.47% 3 1048421 280.20% @@ -552,15 +552,15 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 49361.667333 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.267300 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34265289889 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7736833634 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles @@ -573,29 +573,29 @@ system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 33109.914913 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44248421389 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12908645134 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 33109.914913 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 4480566 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44248421389 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses system.cpu1.dcache.overall_misses 1336410 # number of overall misses system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12908645134 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles @@ -616,11 +616,11 @@ system.cpu1.dcache.tagsinuse 486.799078 # Cy system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 158256 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17763600 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14707751 # Number of cycles decode is idle +system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode @@ -649,9 +649,9 @@ system.cpu1.fetch.icacheStallCycles 3081765 # Nu system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38058468 +system.cpu1.fetch.rateDist.samples 38058467 system.cpu1.fetch.rateDist.min_value 0 - 0 33027825 8678.18% + 0 33027824 8678.18% 1 336540 88.43% 2 683303 179.54% 3 398795 104.78% @@ -664,14 +664,14 @@ system.cpu1.fetch.rateDist.max_value 8 system.cpu1.fetch.rateDist.end_dist system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14557.233772 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.243441 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6814080999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5188832000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked @@ -683,29 +683,29 @@ system.cpu1.icache.blocked_cycles_no_mshrs 287500 # system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14557.233772 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency +system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6814080999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5188832000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14557.233772 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency +system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 2613676 # number of overall hits -system.cpu1.icache.overall_miss_latency 6814080999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses system.cpu1.icache.overall_misses 468089 # number of overall misses system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5188832000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -726,7 +726,7 @@ system.cpu1.icache.tagsinuse 504.476146 # Cy system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4701181 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate @@ -807,9 +807,9 @@ system.cpu1.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full.end_dist system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058468 +system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467 system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28368883 7454.03% + 0 28368882 7454.03% 1 4650018 1221.81% 2 1988549 522.50% 3 1356758 356.49% @@ -904,7 +904,7 @@ system.cpu1.numCycles 42759649 # nu system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15176070 # Number of cycles rename is idle +system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made @@ -914,11 +914,11 @@ system.cpu1.rename.RENAME:RunCycles 4323376 # Nu system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12475543 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480243 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1084,7 +1084,7 @@ system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 system.l2c.replacements 402113 # number of replacements system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31146.703912 # Cycle average of tags in use +system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use system.l2c.total_refs 2097138 # Total number of references to valid blocks. system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 124275 # number of writebacks diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout index 974343499..3839b0231 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 20 2008 18:39:58 -M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6 -M5 commit date Sun Oct 19 22:50:53 2008 -0400 -M5 started Oct 20 2008 18:47:58 +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:30:16 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 808108731..1ce4a49e9 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -132,7 +132,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -150,8 +149,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -309,7 +306,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -327,8 +323,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -408,7 +402,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -426,8 +419,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -444,7 +435,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -462,8 +452,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt index 094233a29..7b34dbd2c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828381 # Nu global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted global.BPredUnit.lookups 14559443 # Number of BP lookups global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 211094 # Simulator instruction rate (inst/s) -host_mem_usage 290796 # Number of bytes of host memory used -host_seconds 251.32 # Real time elapsed on the host -host_tick_rate 7430116049 # Simulator tick rate (ticks/s) +host_inst_rate 200905 # Simulator instruction rate (inst/s) +host_mem_usage 290800 # Number of bytes of host memory used +host_seconds 264.07 # Real time elapsed on the host +host_tick_rate 7071490969 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout index 3c523295b..4989a72b8 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 20 2008 18:39:58 -M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6 -M5 commit date Sun Oct 19 22:50:53 2008 -0400 -M5 started Oct 20 2008 18:47:58 +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:28:27 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index f2490f7d0..042194df8 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3434883 # Simulator instruction rate (inst/s) -host_mem_usage 338884 # Number of bytes of host memory used -host_seconds 70.99 # Real time elapsed on the host -host_tick_rate 1721637062 # Simulator tick rate (ticks/s) +host_inst_rate 2390204 # Simulator instruction rate (inst/s) +host_mem_usage 328072 # Number of bytes of host memory used +host_seconds 102.01 # Real time elapsed on the host +host_tick_rate 1198022319 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index 9799173e4..2fac0077c 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:28:02 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:56:43 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 91c1b4f58..e22470f97 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index eb056d4cc..8d551e127 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1384402 # Simulator instruction rate (inst/s) -host_mem_usage 334744 # Number of bytes of host memory used -host_seconds 176.13 # Real time elapsed on the host -host_tick_rate 2080531769 # Simulator tick rate (ticks/s) +host_inst_rate 1337728 # Simulator instruction rate (inst/s) +host_mem_usage 335528 # Number of bytes of host memory used +host_seconds 182.28 # Real time elapsed on the host +host_tick_rate 2010386962 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.366446 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 81c01b3d2..0d7d366fc 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:28:38 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:52:55 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt index 5d9da19d3..ee5db6e3c 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1324719 # Simulator instruction rate (inst/s) -host_mem_usage 328816 # Number of bytes of host memory used -host_seconds 203.59 # Real time elapsed on the host -host_tick_rate 814052041 # Simulator tick rate (ticks/s) +host_inst_rate 1935457 # Simulator instruction rate (inst/s) +host_mem_usage 329540 # Number of bytes of host memory used +host_seconds 139.35 # Real time elapsed on the host +host_tick_rate 1189355805 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269697303 # Number of instructions simulated sim_seconds 0.165732 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr index 88df04dd8..72ba90ece 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout index 00ec2119c..195b58e3f 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:20:39 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:20:12 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt index f1fef537b..6c9e86c42 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1855549 # Simulator instruction rate (inst/s) -host_mem_usage 197988 # Number of bytes of host memory used -host_seconds 805.96 # Real time elapsed on the host -host_tick_rate 1077833305 # Simulator tick rate (ticks/s) +host_inst_rate 1589069 # Simulator instruction rate (inst/s) +host_mem_usage 198676 # Number of bytes of host memory used +host_seconds 941.11 # Real time elapsed on the host +host_tick_rate 923042875 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492697 # Number of instructions simulated +sim_insts 1495492702 # Number of instructions simulated sim_seconds 0.868687 # Number of seconds simulated -sim_ticks 868687488000 # Number of ticks simulated +sim_ticks 868687490500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737374977 # number of cpu cycles simulated -system.cpu.num_insts 1495492697 # Number of instructions executed +system.cpu.numCycles 1737374982 # number of cpu cycles simulated +system.cpu.num_insts 1495492702 # Number of instructions executed system.cpu.num_refs 533549000 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr index 4a54d0384..eae22fffc 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout index 03a15d3cc..90786ddde 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:20:39 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:22:32 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -71,4 +72,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868687488000 because target called exit() +Exiting @ tick 868687490500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 67cb70d64..206ca6cd4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index ec7c6b89a..756f9cdc8 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted global.BPredUnit.lookups 62209737 # Number of BP lookups global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 169173 # Simulator instruction rate (inst/s) -host_mem_usage 208828 # Number of bytes of host memory used -host_seconds 2220.07 # Real time elapsed on the host -host_tick_rate 60807494 # Simulator tick rate (ticks/s) +host_inst_rate 185748 # Simulator instruction rate (inst/s) +host_mem_usage 209620 # Number of bytes of host memory used +host_seconds 2021.96 # Real time elapsed on the host +host_tick_rate 66765374 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index b72d69553..19732539d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index ce9f5b7a4..e6ff44d85 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:14:55 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:33:01 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Eon, Version 1.1 OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index e32cacf16..651cb243c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2526947 # Simulator instruction rate (inst/s) -host_mem_usage 181828 # Number of bytes of host memory used -host_seconds 157.77 # Real time elapsed on the host -host_tick_rate 1263471125 # Simulator tick rate (ticks/s) +host_inst_rate 3323718 # Simulator instruction rate (inst/s) +host_mem_usage 201288 # Number of bytes of host memory used +host_seconds 119.95 # Real time elapsed on the host +host_tick_rate 1661856596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index b72d69553..19732539d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 0c68e7560..913be9f23 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:59 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:13:17 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Eon, Version 1.1 OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index a0f5ff1cc..5e43f3356 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 193a2e752..3ff76c5f4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1657758 # Simulator instruction rate (inst/s) -host_mem_usage 207956 # Number of bytes of host memory used -host_seconds 240.48 # Real time elapsed on the host -host_tick_rate 2359203743 # Simulator tick rate (ticks/s) +host_inst_rate 1753697 # Simulator instruction rate (inst/s) +host_mem_usage 208744 # Number of bytes of host memory used +host_seconds 227.33 # Real time elapsed on the host +host_tick_rate 2495737915 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index b72d69553..19732539d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 6317641d5..caf805d08 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:19:23 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:58:04 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Eon, Version 1.1 OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index bc6eef39f..d47448621 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt index 655aa8500..9069620c7 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 29107758 # Nu global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted global.BPredUnit.lookups 349424732 # Number of BP lookups global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target. -host_inst_rate 256177 # Simulator instruction rate (inst/s) -host_mem_usage 209160 # Number of bytes of host memory used -host_seconds 7116.35 # Real time elapsed on the host -host_tick_rate 99090030 # Simulator tick rate (ticks/s) +host_inst_rate 250324 # Simulator instruction rate (inst/s) +host_mem_usage 209520 # Number of bytes of host memory used +host_seconds 7282.75 # Real time elapsed on the host +host_tick_rate 96826033 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr index 70f4beb45..ac5607abe 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout index 157f726f1..14154444a 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 28 2008 07:36:20 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:35 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 3a5a57719..841932c00 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2579952 # Simulator instruction rate (inst/s) -host_mem_usage 180972 # Number of bytes of host memory used -host_seconds 778.69 # Real time elapsed on the host -host_tick_rate 1290253991 # Simulator tick rate (ticks/s) +host_inst_rate 5368625 # Simulator instruction rate (inst/s) +host_mem_usage 200452 # Number of bytes of host memory used +host_seconds 374.21 # Real time elapsed on the host +host_tick_rate 2684890322 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr index 70f4beb45..ac5607abe 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index ff0b6f94d..315befb59 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:15:46 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:06:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index d888b1d3a..fb670395d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index a29c5dd96..6e65ba05d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1695111 # Simulator instruction rate (inst/s) -host_mem_usage 207112 # Number of bytes of host memory used -host_seconds 1185.17 # Real time elapsed on the host -host_tick_rate 2375153470 # Simulator tick rate (ticks/s) +host_inst_rate 2795907 # Simulator instruction rate (inst/s) +host_mem_usage 207904 # Number of bytes of host memory used +host_seconds 718.55 # Real time elapsed on the host +host_tick_rate 3917565207 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index 70f4beb45..ac5607abe 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index bb638ab73..f4fff795a 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:24 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 21:28:15 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 8de3e1042..2cf1e1f30 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 6cd7ed43b..60ec1554f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 452707 # Nu global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted global.BPredUnit.lookups 16249458 # Number of BP lookups global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 176565 # Simulator instruction rate (inst/s) -host_mem_usage 212168 # Number of bytes of host memory used -host_seconds 450.78 # Real time elapsed on the host -host_tick_rate 60195419 # Simulator tick rate (ticks/s) +host_inst_rate 272001 # Simulator instruction rate (inst/s) +host_mem_usage 212988 # Number of bytes of host memory used +host_seconds 292.62 # Real time elapsed on the host +host_tick_rate 92731689 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index 3c7b7f584..61aa77324 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:23 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:42:31 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index f06392b4f..fba592412 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2496642 # Simulator instruction rate (inst/s) -host_mem_usage 184388 # Number of bytes of host memory used -host_seconds 35.38 # Real time elapsed on the host -host_tick_rate 1249741953 # Simulator tick rate (ticks/s) +host_inst_rate 5277091 # Simulator instruction rate (inst/s) +host_mem_usage 203864 # Number of bytes of host memory used +host_seconds 16.74 # Real time elapsed on the host +host_tick_rate 2641544350 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index 4f6e61da0..a2c31ed4b 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:32 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:13:00 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 65c1a4eef..7718ab128 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index fcf32cd99..828a42be2 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1478736 # Simulator instruction rate (inst/s) -host_mem_usage 210524 # Number of bytes of host memory used -host_seconds 59.74 # Real time elapsed on the host -host_tick_rate 2262580844 # Simulator tick rate (ticks/s) +host_inst_rate 1704355 # Simulator instruction rate (inst/s) +host_mem_usage 211324 # Number of bytes of host memory used +host_seconds 51.83 # Real time elapsed on the host +host_tick_rate 2607795037 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index 04c3255fb..8bed4881a 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:24 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 21:27:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index d8596d3fc..25cbdfb32 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3368510 # Simulator instruction rate (inst/s) -host_mem_usage 185484 # Number of bytes of host memory used -host_seconds 40.42 # Real time elapsed on the host -host_tick_rate 1686201794 # Simulator tick rate (ticks/s) +host_inst_rate 2431097 # Simulator instruction rate (inst/s) +host_mem_usage 204768 # Number of bytes of host memory used +host_seconds 56.00 # Real time elapsed on the host +host_tick_rate 1216955986 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index 942c388e0..06afeeef2 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) warn: ignoring syscall time(4026527312, 1, ...) @@ -562,3 +561,4 @@ warn: ignoring syscall time(4026525968, 4026526436, ...) warn: ignoring syscall time(4026526056, 7004192, ...) warn: ignoring syscall time(4026527512, 4, ...) warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 068a01d62..b0eadd5ad 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:29:09 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:47 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 685fc165c..1868a281c 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 398922df0..9b35ba579 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1368614 # Simulator instruction rate (inst/s) -host_mem_usage 211448 # Number of bytes of host memory used -host_seconds 99.47 # Real time elapsed on the host -host_tick_rate 2062044712 # Simulator tick rate (ticks/s) +host_inst_rate 1344201 # Simulator instruction rate (inst/s) +host_mem_usage 212228 # Number of bytes of host memory used +host_seconds 101.28 # Real time elapsed on the host +host_tick_rate 2025263348 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.205117 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index 942c388e0..06afeeef2 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) warn: ignoring syscall time(4026527312, 1, ...) @@ -562,3 +561,4 @@ warn: ignoring syscall time(4026525968, 4026526436, ...) warn: ignoring syscall time(4026526056, 7004192, ...) warn: ignoring syscall time(4026527512, 4, ...) warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 5a2b5220b..2b1927ccc 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:30:05 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:57 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 26fa15dd4..7cd689e97 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 3ee235d33..2aa5eaaa5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 312845728 # Number of BTB hits -global.BPredUnit.BTBLookups 319575550 # Number of BTB lookups +global.BPredUnit.BTBHits 312845737 # Number of BTB hits +global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19647323 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 266741487 # Number of conditional branches predicted -global.BPredUnit.lookups 345502581 # Number of BP lookups -global.BPredUnit.usedRAS 23750301 # Number of times the RAS was used to get a target. -host_inst_rate 237180 # Simulator instruction rate (inst/s) -host_mem_usage 201180 # Number of bytes of host memory used -host_seconds 7319.53 # Real time elapsed on the host -host_tick_rate 101414942 # Simulator tick rate (ticks/s) +global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted +global.BPredUnit.lookups 345502589 # Number of BP lookups +global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. +host_inst_rate 152874 # Simulator instruction rate (inst/s) +host_mem_usage 201972 # Number of bytes of host memory used +host_seconds 11356.03 # Real time elapsed on the host +host_tick_rate 65366964 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 67515290 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 621608429 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 234046219 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated -sim_ticks 742309410500 # Number of ticks simulated +sim_ticks 742309425500 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 62782580 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1379215313 +system.cpu.commit.COM:committed_per_cycle.samples 1379215338 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 736540795 5340.29% - 1 260049510 1885.49% + 0 736540830 5340.29% + 1 260049504 1885.49% 2 126970462 920.60% - 3 77723430 563.53% - 4 51327443 372.15% + 3 77723426 563.53% + 4 51327439 372.15% 5 27759546 201.27% - 6 26179569 189.81% + 6 26179568 189.81% 7 9881978 71.65% - 8 62782580 455.21% + 8 62782585 455.21% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,10 +43,10 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19646822 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 627314196 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction @@ -61,62 +61,62 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 523259958 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16887.800030 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.117004 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 512954318 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 174039587500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 10305640 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3030506 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 81969786000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7275134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33917.186217 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824413 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155297499 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184204340094 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5431003 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 83541340193 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248526 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 73.053389 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 683988460 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22764.952321 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency -system.cpu.dcache.demand_hits 668251817 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 358243927594 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses -system.cpu.dcache.demand_misses 15736643 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6212983 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 165511126193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523660 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 683988460 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22764.952321 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 668251817 # number of overall hits -system.cpu.dcache.overall_miss_latency 358243927594 # number of overall miss cycles +system.cpu.dcache.overall_hits 668251814 # number of overall hits +system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses -system.cpu.dcache.overall_misses 15736643 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6212983 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 165511126193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 15736652 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523660 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,63 +128,63 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155770 # number of replacements -system.cpu.dcache.sampled_refs 9159866 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9155775 # number of replacements +system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4082.023671 # Cycle average of tags in use -system.cpu.dcache.total_refs 669159252 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use +system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245448 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 98604485 # Number of cycles decode is blocked +system.cpu.dcache.writebacks 2245449 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2810650716 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 726334598 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 549143095 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 93084197 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 768331628 # DTB accesses +system.cpu.dtb.accesses 768331639 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 752318827 # DTB hits +system.cpu.dtb.hits 752318838 # DTB hits system.cpu.dtb.misses 16012801 # DTB misses -system.cpu.dtb.read_accesses 566617541 # DTB read accesses +system.cpu.dtb.read_accesses 566617551 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 557381515 # DTB read hits +system.cpu.dtb.read_hits 557381525 # DTB read hits system.cpu.dtb.read_misses 9236026 # DTB read misses -system.cpu.dtb.write_accesses 201714087 # DTB write accesses +system.cpu.dtb.write_accesses 201714088 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 194937312 # DTB write hits +system.cpu.dtb.write_hits 194937313 # DTB write hits system.cpu.dtb.write_misses 6776775 # DTB write misses -system.cpu.fetch.Branches 345502581 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355180514 # Number of cache lines fetched -system.cpu.fetch.Cycles 920206753 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7941780 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2863046416 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28103164 # Number of cycles fetch has spent squashing +system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched +system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355180514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336596029 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1472299511 +system.cpu.fetch.rateDist.samples 1472299541 system.cpu.fetch.rateDist.min_value 0 - 0 907273306 6162.29% + 0 907273323 6162.29% 1 47886355 325.25% - 2 34613457 235.10% + 2 34613456 235.10% 3 52095475 353.84% - 4 125971052 855.61% + 4 125971058 855.61% 5 69335096 470.93% 6 50458684 342.72% 7 40993758 278.43% - 8 143672328 975.84% + 8 143672336 975.84% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 355180514 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355179280 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses @@ -194,16 +194,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # ms system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 393768.603104 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355180514 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency -system.cpu.icache.demand_hits 355179280 # number of demand (read+write) hits +system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses @@ -214,11 +214,11 @@ system.cpu.icache.demand_mshr_misses 902 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 355180514 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355179280 # number of overall hits +system.cpu.icache.overall_hits 355179284 # number of overall hits system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 1234 # number of overall misses @@ -240,59 +240,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 711.425376 # Cycle average of tags in use -system.cpu.icache.total_refs 355179280 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use +system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 282186317 # Number of branches executed +system.cpu.iew.EXEC:branches 282186314 # Number of branches executed system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate -system.cpu.iew.EXEC:refs 769619313 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 201925300 # Number of stores executed +system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 201925301 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1531990742 # num instructions consuming a value -system.cpu.iew.WB:count 2240290220 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value +system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243717846 # num instructions producing a value +system.cpu.iew.WB:producers 1243717865 # num instructions producing a value system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle -system.cpu.iew.WB:sent 2261678921 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21342133 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 621608429 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 234046219 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2621719070 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 567694013 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 36858072 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2278986798 # Number of executed instructions +system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 93084197 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 33889592 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 175942068 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 73141237 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20638337 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2315844870 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1532920234 66.19% # Type of FU issued + IntAlu 1532920254 66.19% # Type of FU issued IntMult 99 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 234 0.00% # Type of FU issued @@ -301,8 +301,8 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 16 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 577889725 24.95% # Type of FU issued - MemWrite 205034375 8.85% # Type of FU issued + MemRead 577889733 24.95% # Type of FU issued + MemWrite 205034377 8.85% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist @@ -325,31 +325,31 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299511 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 577695747 3923.77% - 1 271543753 1844.35% - 2 242868164 1649.58% - 3 139713871 948.95% - 4 122021081 828.78% - 5 69652696 473.09% - 6 39670195 269.44% - 7 8017830 54.46% + 0 577695763 3923.77% + 1 271543756 1844.35% + 2 242868170 1649.58% + 3 139713874 948.95% + 4 122021082 828.78% + 5 69652698 473.09% + 6 39670196 269.44% + 7 8017828 54.46% 8 1116174 7.58% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate -system.cpu.iq.iqInstsAdded 2492922470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2315844870 # Number of instructions issued +system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 739697575 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1501742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 329349436 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 355180548 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 355180552 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 355180514 # ITB hits +system.cpu.itb.hits 355180518 # ITB hits system.cpu.itb.misses 34 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency @@ -360,39 +360,39 @@ system.cpu.l2cache.ReadExReq_misses 1884731 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7276037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5387449 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363810 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.097532 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459886 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 12488541353 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363810 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373231721 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363810 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245448 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2245448 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.417948 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160768 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5387449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses @@ -403,11 +403,11 @@ system.cpu.l2cache.demand_mshr_misses 3773319 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160768 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5387449 # number of overall hits +system.cpu.l2cache.overall_hits 5387454 # number of overall hits system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3773319 # number of overall misses @@ -429,27 +429,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2759426 # number of replacements system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25902.034995 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6731616 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1195718 # number of writebacks -system.cpu.numCycles 1484618822 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 68342800 # Number of cycles rename is blocking +system.cpu.numCycles 1484618852 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 744648223 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 20682073 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3556218268 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2749142878 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2059304818 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 535957515 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 93084197 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 30265718 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 683101855 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 60936720 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index 8867143dd..fd3c8e17c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index d0f2d73e9..bf92c70e1 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:54 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:13:16 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index ac280ef36..c3eb995b5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2729023 # Simulator instruction rate (inst/s) -host_mem_usage 174164 # Number of bytes of host memory used -host_seconds 666.82 # Real time elapsed on the host -host_tick_rate 1369458693 # Simulator tick rate (ticks/s) +host_inst_rate 3454414 # Simulator instruction rate (inst/s) +host_mem_usage 193640 # Number of bytes of host memory used +host_seconds 526.80 # Real time elapsed on the host +host_tick_rate 1733469179 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr index 8867143dd..fd3c8e17c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index cab37301e..2550b2dca 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:46 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:32:56 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 811d5b2e6..896ad9c05 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 0c5d69c2d..65a250806 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2488083 # Simulator instruction rate (inst/s) -host_mem_usage 200292 # Number of bytes of host memory used -host_seconds 731.40 # Real time elapsed on the host -host_tick_rate 3729826518 # Simulator tick rate (ticks/s) +host_inst_rate 2843037 # Simulator instruction rate (inst/s) +host_mem_usage 201092 # Number of bytes of host memory used +host_seconds 640.08 # Real time elapsed on the host +host_tick_rate 4261930074 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 8867143dd..fd3c8e17c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index aa4d0233f..e112321fe 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:57 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:47:24 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt index 891b17a00..a2bce703e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1763085 # Simulator instruction rate (inst/s) -host_mem_usage 194072 # Number of bytes of host memory used -host_seconds 2639.25 # Real time elapsed on the host -host_tick_rate 1074249302 # Simulator tick rate (ticks/s) +host_inst_rate 2012716 # Simulator instruction rate (inst/s) +host_mem_usage 194900 # Number of bytes of host memory used +host_seconds 2311.91 # Real time elapsed on the host +host_tick_rate 1226349708 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653219791 # Number of instructions simulated sim_seconds 2.835211 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr index 4a54d0384..eae22fffc 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout index 196cf8f42..bedb92044 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:55:01 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:38:14 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 3d1cca219..9dd2a52cb 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 36295ae14..8c4b78811 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted global.BPredUnit.lookups 19468548 # Number of BP lookups global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 157592 # Simulator instruction rate (inst/s) -host_mem_usage 206456 # Number of bytes of host memory used -host_seconds 534.16 # Real time elapsed on the host -host_tick_rate 76416157 # Simulator tick rate (ticks/s) +host_inst_rate 134854 # Simulator instruction rate (inst/s) +host_mem_usage 207240 # Number of bytes of host memory used +host_seconds 624.23 # Real time elapsed on the host +host_tick_rate 65390701 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index 1669451f7..7f155cd9b 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -5,13 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:10:53 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 21:16:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index 127e45547..f322d0c86 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2451408 # Simulator instruction rate (inst/s) -host_mem_usage 179100 # Number of bytes of host memory used -host_seconds 37.49 # Real time elapsed on the host -host_tick_rate 1225693454 # Simulator tick rate (ticks/s) +host_inst_rate 5620505 # Simulator instruction rate (inst/s) +host_mem_usage 198560 # Number of bytes of host memory used +host_seconds 16.35 # Real time elapsed on the host +host_tick_rate 2810224606 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index f2321006a..e5e1bfe2b 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout @@ -5,13 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:38 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:18 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index fdbe4055f..c80a77e5d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 58a892eca..e6e809818 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1888440 # Simulator instruction rate (inst/s) -host_mem_usage 205224 # Number of bytes of host memory used -host_seconds 48.67 # Real time elapsed on the host -host_tick_rate 2440025498 # Simulator tick rate (ticks/s) +host_inst_rate 1922347 # Simulator instruction rate (inst/s) +host_mem_usage 206016 # Number of bytes of host memory used +host_seconds 47.81 # Real time elapsed on the host +host_tick_rate 2483835101 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index 7edb64427..cd7a7fb23 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index 2f63f8309..50f9ae74a 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,13 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:14:06 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:41:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index e8167a62f..0c05fead2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3028318 # Simulator instruction rate (inst/s) -host_mem_usage 211228 # Number of bytes of host memory used -host_seconds 63.88 # Real time elapsed on the host -host_tick_rate 1514162901 # Simulator tick rate (ticks/s) +host_inst_rate 2346541 # Simulator instruction rate (inst/s) +host_mem_usage 200408 # Number of bytes of host memory used +host_seconds 82.44 # Real time elapsed on the host +host_tick_rate 1173274177 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr index 7edb64427..5ff857a03 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 5631e050f..997da0518 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -5,13 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:31:36 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:54:24 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 05096323e..afa783463 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 40cd826e7..c4bd23868 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409829 # Simulator instruction rate (inst/s) -host_mem_usage 207084 # Number of bytes of host memory used -host_seconds 137.21 # Real time elapsed on the host -host_tick_rate 1971980655 # Simulator tick rate (ticks/s) +host_inst_rate 1243989 # Simulator instruction rate (inst/s) +host_mem_usage 207864 # Number of bytes of host memory used +host_seconds 155.50 # Real time elapsed on the host +host_tick_rate 1740014863 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270579 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 7edb64427..5ff857a03 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index f7be3ede4..98f64dfde 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,13 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:31:45 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:20 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt index c4fe4712d..2581f730b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1300052 # Simulator instruction rate (inst/s) -host_mem_usage 201460 # Number of bytes of host memory used -host_seconds 168.14 # Real time elapsed on the host -host_tick_rate 773204086 # Simulator tick rate (ticks/s) +host_inst_rate 2311586 # Simulator instruction rate (inst/s) +host_mem_usage 202280 # Number of bytes of host memory used +host_seconds 94.57 # Real time elapsed on the host +host_tick_rate 1374811015 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595322 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr index c336b1cb3..27f336eb4 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr @@ -1,6 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented warn: Increasing stack size by one page. warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout index fcbdb82ed..1d99c3015 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -5,15 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:20:39 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 6 2008 00:16:46 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 96250b233..279ca6f7b 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -47,7 +47,7 @@ side_b=system.membus.port[2] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer clock=1 cpu_id=0 defer_registration=false @@ -57,6 +57,7 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -78,6 +79,9 @@ icache_port=system.membus.port[9] type=SparcDTB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcITB size=64 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt index 34b89818c..fb4170969 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1839897 # Simulator instruction rate (inst/s) -host_mem_usage 481416 # Number of bytes of host memory used -host_seconds 1211.57 # Real time elapsed on the host -host_tick_rate 1843707 # Simulator tick rate (ticks/s) +host_inst_rate 2656730 # Simulator instruction rate (inst/s) +host_mem_usage 499828 # Number of bytes of host memory used +host_seconds 839.06 # Real time elapsed on the host +host_tick_rate 2662232 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr index 5c083e687..6814dd775 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -9,7 +9,7 @@ warn: Sockets disabled, not accepting terminal connections Warning: rounding error > tolerance 0.002000 rounded to 0 warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. +warn: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout index 18ed44091..2f6efdd10 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:09 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:21:11 -M5 executing on piton +M5 compiled Nov 5 2008 15:59:58 +M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e +M5 commit date Wed Nov 05 15:30:49 2008 -0500 +M5 started Nov 5 2008 16:00:22 +M5 executing on zizzer command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 80cb33a4e..3764c941e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 684f7196b..cbad9353d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted global.BPredUnit.lookups 2108 # Number of BP lookups global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target. -host_inst_rate 87257 # Simulator instruction rate (inst/s) -host_mem_usage 198272 # Number of bytes of host memory used +host_inst_rate 86240 # Simulator instruction rate (inst/s) +host_mem_usage 198988 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 171219532 # Simulator tick rate (ticks/s) +host_tick_rate 169229614 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. memdepunit.memDep.conflictingStores 28 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 7edb64427..5ff857a03 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 55062a489..2fe8c587c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:38 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:13:15 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 12391500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 6f4810c44..15e8bed82 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 74368 # Simulator instruction rate (inst/s) -host_mem_usage 201628 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 37260110 # Simulator tick rate (ticks/s) +host_inst_rate 598748 # Simulator instruction rate (inst/s) +host_mem_usage 190820 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 294136747 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6315 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr index 7edb64427..5ff857a03 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 34663e210..b3d91abb5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:32 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 21:40:14 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 3170500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 1f66e65a5..0b9f96b2e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 7935839f7..a3039b303 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 496189 # Simulator instruction rate (inst/s) -host_mem_usage 197472 # Number of bytes of host memory used +host_inst_rate 472326 # Simulator instruction rate (inst/s) +host_mem_usage 198180 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2580329636 # Simulator tick rate (ticks/s) +host_tick_rate 2462369543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6315 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 7edb64427..5ff857a03 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index ac2c65392..c97b9deb2 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:24 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:13:17 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 33503000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index a04865714..21f8bc603 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 110788930..c3f97c1a9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 209 # Nu global.BPredUnit.condPredicted 447 # Number of conditional branches predicted global.BPredUnit.lookups 859 # Number of BP lookups global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 67408 # Simulator instruction rate (inst/s) -host_mem_usage 197188 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 201701674 # Simulator tick rate (ticks/s) +host_inst_rate 5854 # Simulator instruction rate (inst/s) +host_mem_usage 197984 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host +host_tick_rate 17609622 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index 8c3c8342e..28251ddf8 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 9f9b0550a..55e76881d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:12:32 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:32:55 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 28ff448c6..9ae501100 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 124133 # Simulator instruction rate (inst/s) -host_mem_usage 171628 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 61574601 # Simulator tick rate (ticks/s) +host_inst_rate 229372 # Simulator instruction rate (inst/s) +host_mem_usage 189868 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 113875724 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr index 8c3c8342e..28251ddf8 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 5ed36f668..b6b984d4a 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:58 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:35 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index bfcd95204..6a2eadca9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index ae6876b28..5e0dacddf 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 96492 # Simulator instruction rate (inst/s) -host_mem_usage 196528 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 644436202 # Simulator tick rate (ticks/s) +host_inst_rate 251832 # Simulator instruction rate (inst/s) +host_mem_usage 197320 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 1657349995 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index 8c3c8342e..28251ddf8 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 1cedfe45b..5af4e5b77 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:24 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:17 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 7c3074e0a..6c370ab2d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 493457 # Simulator instruction rate (inst/s) -host_mem_usage 191128 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 241461749 # Simulator tick rate (ticks/s) +host_inst_rate 10079 # Simulator instruction rate (inst/s) +host_mem_usage 192068 # Number of bytes of host memory used +host_seconds 0.56 # Real time elapsed on the host +host_tick_rate 5037819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr index 7edb64427..5ff857a03 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index d2ef70029..77c8639ab 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:20:59 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:21:01 -M5 executing on piton +M5 compiled Nov 5 2008 22:37:22 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:37:50 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello World! Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 53b4a0368..9ef900f1f 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -96,7 +96,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -114,8 +113,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -136,7 +133,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -154,8 +150,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -176,7 +170,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -194,8 +187,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index c07fb7a13..d5658e44c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 142745 # Simulator instruction rate (inst/s) -host_mem_usage 198836 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 810420480 # Simulator tick rate (ticks/s) +host_inst_rate 334992 # Simulator instruction rate (inst/s) +host_mem_usage 199532 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1887416058 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr index 7edb64427..5ff857a03 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 289b969c4..17fb9f581 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:20:59 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:21:02 -M5 executing on piton +M5 compiled Nov 5 2008 22:37:22 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:37:51 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello World! Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index c2853cc3f..8a19f5ea4 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 31798 # Simulator instruction rate (inst/s) -host_mem_usage 202884 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 16065810 # Simulator tick rate (ticks/s) +host_inst_rate 371297 # Simulator instruction rate (inst/s) +host_mem_usage 191740 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 185101425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 11bda0e5c..946edd9f0 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:32:52 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:47 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 9cdba6f24..c8a9fb583 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 39cffe2aa..7d5ee5db9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 288337 # Simulator instruction rate (inst/s) -host_mem_usage 198672 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1546587822 # Simulator tick rate (ticks/s) +host_inst_rate 419811 # Simulator instruction rate (inst/s) +host_mem_usage 199192 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2213741040 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 134f2661f..92edc3116 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:32:53 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:19 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index bacf33c33..3c3c458ce 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8984 # Simulator instruction rate (inst/s) -host_mem_usage 189888 # Number of bytes of host memory used -host_seconds 1.06 # Real time elapsed on the host -host_tick_rate 5221453 # Simulator tick rate (ticks/s) +host_inst_rate 557395 # Simulator instruction rate (inst/s) +host_mem_usage 190704 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 320851262 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9493 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr index 88df04dd8..72ba90ece 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index e87534cec..7fa8be29e 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2008 20:20:37 -M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617 -M5 commit date Wed Oct 08 20:18:02 2008 -0700 -M5 started Oct 8 2008 20:20:39 -M5 executing on tater +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 6 2008 00:18:22 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 5518000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 6c266b8a4..62ebb142a 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 14012208f..02399594b 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1443 # Nu global.BPredUnit.condPredicted 2855 # Number of conditional branches predicted global.BPredUnit.lookups 5041 # Number of BP lookups global.BPredUnit.usedRAS 646 # Number of times the RAS was used to get a target. -host_inst_rate 37318 # Simulator instruction rate (inst/s) -host_mem_usage 199092 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host -host_tick_rate 41547100 # Simulator tick rate (ticks/s) +host_inst_rate 76947 # Simulator instruction rate (inst/s) +host_mem_usage 199748 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 85614119 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 42 # Number of conflicting loads. memdepunit.memDep.conflictingStores 9 # Number of conflicting stores. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 8867143dd..fc5805f9e 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 57e2874c3..10049ad35 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:23 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 18:30:32 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Hello world! Hello world! Exiting @ tick 14029500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 6ee9f16a8..b0fb0c129 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -104,7 +104,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -122,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -299,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,7 +315,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index f90003dbb..d80957aed 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 2923 # Nu global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted global.BPredUnit.lookups 11413 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 50656 # Simulator instruction rate (inst/s) -host_mem_usage 199212 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -host_tick_rate 97240761 # Simulator tick rate (ticks/s) +host_inst_rate 55497 # Simulator instruction rate (inst/s) +host_mem_usage 199732 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +host_tick_rate 106451563 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index ba74f1637..1f6eb4b07 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:32:53 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:55 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 8d9b3b609..fa5cbc97a 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15225 # Simulator instruction rate (inst/s) -host_mem_usage 202592 # Number of bytes of host memory used -host_seconds 1.00 # Real time elapsed on the host -host_tick_rate 7641899 # Simulator tick rate (ticks/s) +host_inst_rate 641188 # Simulator instruction rate (inst/s) +host_mem_usage 191520 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 319099476 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 777898779..7103e96c6 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:32:54 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:56 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 7773c920e..35e384fb9 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 42336245f..f45ffd986 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 494493 # Simulator instruction rate (inst/s) -host_mem_usage 198556 # Number of bytes of host memory used +host_inst_rate 494848 # Simulator instruction rate (inst/s) +host_mem_usage 199068 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1381087807 # Simulator tick rate (ticks/s) +host_tick_rate 1383502218 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr index 0598945b4..ee69ae99e 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index 1426e329d..796520389 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:21:24 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:32:54 -M5 executing on piton +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:56 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index a3b119b60..9d8e5c8ed 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -70,7 +71,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -88,8 +88,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -110,7 +108,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -128,8 +125,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -138,6 +133,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=AlphaInterrupts + [system.cpu0.itb] type=AlphaITB size=48 @@ -147,7 +145,7 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=1 defer_registration=false @@ -157,6 +155,7 @@ do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -182,7 +181,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -200,8 +198,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -222,7 +218,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -240,8 +235,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -250,6 +243,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=AlphaInterrupts + [system.cpu1.itb] type=AlphaITB size=48 @@ -318,7 +314,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -336,8 +331,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -354,7 +347,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -372,8 +364,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index af3c5730d..adb5935db 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4441196 # Simulator instruction rate (inst/s) -host_mem_usage 289900 # Number of bytes of host memory used -host_seconds 14.21 # Real time elapsed on the host -host_tick_rate 131610473505 # Simulator tick rate (ticks/s) +host_inst_rate 4457341 # Simulator instruction rate (inst/s) +host_mem_usage 291000 # Number of bytes of host memory used +host_seconds 14.16 # Real time elapsed on the host +host_tick_rate 132088621816 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63113507 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 9825eea69..d445cb942 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,5 +1,5 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 69f528e17..4c93eabec 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:32:52 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index f63d2144d..a6db3884d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -70,7 +71,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -88,8 +88,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -110,7 +108,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -128,8 +125,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -138,6 +133,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaITB size=48 @@ -206,7 +204,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -224,8 +221,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -242,7 +237,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -260,8 +254,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 5018c7d30..bd2b86aca 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3096300 # Simulator instruction rate (inst/s) -host_mem_usage 288712 # Number of bytes of host memory used -host_seconds 19.38 # Real time elapsed on the host -host_tick_rate 94358252114 # Simulator tick rate (ticks/s) +host_inst_rate 2960159 # Simulator instruction rate (inst/s) +host_mem_usage 289760 # Number of bytes of host memory used +host_seconds 20.27 # Real time elapsed on the host +host_tick_rate 90209540739 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59995351 # Number of instructions simulated sim_seconds 1.828356 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 45392f539..1a557daf8 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 4d9c075f2..e7d4d476c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:28:06 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 29f87c7e0..de9bfc9e4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -67,7 +68,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -85,8 +85,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -107,7 +105,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -125,8 +122,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -135,6 +130,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=AlphaInterrupts + [system.cpu0.itb] type=AlphaITB size=48 @@ -144,7 +142,7 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=1 defer_registration=false @@ -154,6 +152,7 @@ do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -176,7 +175,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -194,8 +192,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -216,7 +212,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -234,8 +229,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -244,6 +237,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=AlphaInterrupts + [system.cpu1.itb] type=AlphaITB size=48 @@ -312,7 +308,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -330,8 +325,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -348,7 +341,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -366,8 +358,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 3478349a5..67988d1e0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1987058 # Simulator instruction rate (inst/s) -host_mem_usage 287224 # Number of bytes of host memory used -host_seconds 29.88 # Real time elapsed on the host -host_tick_rate 65994111033 # Simulator tick rate (ticks/s) +host_inst_rate 1529547 # Simulator instruction rate (inst/s) +host_mem_usage 287776 # Number of bytes of host memory used +host_seconds 38.82 # Real time elapsed on the host +host_tick_rate 50799321587 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59379829 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index c03c0154e..dad1cad88 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,5 +1,5 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: 591544000: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 02b572ec9..447da7e4d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:29:36 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index c6c4209f5..3e8e04375 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -67,7 +68,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -85,8 +85,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -107,7 +105,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -125,8 +122,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -135,6 +130,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaITB size=48 @@ -203,7 +201,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -221,8 +218,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -239,7 +234,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -257,8 +251,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 7b835d1b3..5185f8b73 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1555255 # Simulator instruction rate (inst/s) -host_mem_usage 285892 # Number of bytes of host memory used -host_seconds 36.11 # Real time elapsed on the host -host_tick_rate 53447376481 # Simulator tick rate (ticks/s) +host_inst_rate 1640475 # Simulator instruction rate (inst/s) +host_mem_usage 286536 # Number of bytes of host memory used +host_seconds 34.24 # Real time elapsed on the host +host_tick_rate 56375976626 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56165112 # Number of instructions simulated sim_seconds 1.930166 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 45392f539..1a557daf8 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 6ec325f9b..5cef637b5 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:27:38 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 064beb313..b55acc4e4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1676309 # Simulator instruction rate (inst/s) -host_mem_usage 188356 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 837474668 # Simulator tick rate (ticks/s) +host_inst_rate 3131465 # Simulator instruction rate (inst/s) +host_mem_usage 189960 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 1563505663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr index ea818e9b8..a1d152694 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index e002b4982..1f91d28a0 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:14:06 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:34 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries 49508 bytes wasted >Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 8c926f583..0f1cefdac 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -40,7 +40,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -58,8 +57,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -80,7 +77,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -98,8 +94,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -120,7 +114,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 @@ -138,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index fdebad7d8..c3508e466 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1585966 # Simulator instruction rate (inst/s) -host_mem_usage 196712 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host -host_tick_rate 2336933545 # Simulator tick rate (ticks/s) +host_inst_rate 1653831 # Simulator instruction rate (inst/s) +host_mem_usage 197344 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 2436827913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr index ea818e9b8..a1d152694 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index fec2f14b8..04f8b3fb2 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:23 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:15:35 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries 49508 bytes wasted >Exiting @ tick 737389000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index ce3301742..3ae48f3b4 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -33,7 +33,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -51,8 +50,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -85,7 +82,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -103,8 +99,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -137,7 +131,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -155,8 +148,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -189,7 +180,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -207,8 +197,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -241,7 +229,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -259,8 +246,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -293,7 +278,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -311,8 +295,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -345,7 +327,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -363,8 +344,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -397,7 +376,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 @@ -415,8 +393,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -443,7 +419,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -461,8 +436,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=65536 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index c4e841ee5..765a44d97 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 323512 # Number of bytes of host memory used -host_seconds 193.82 # Real time elapsed on the host -host_tick_rate 1387453 # Simulator tick rate (ticks/s) +host_mem_usage 324448 # Number of bytes of host memory used +host_seconds 222.79 # Real time elapsed on the host +host_tick_rate 1207024 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index a93b081cc..507652626 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,4 +1,3 @@ -warn: Entering event queue @ 0. Starting simulation... system.cpu3: completed 10000 read accesses @26226880 system.cpu6: completed 10000 read accesses @26416342 system.cpu2: completed 10000 read accesses @26427251 @@ -72,3 +71,4 @@ system.cpu5: completed 90000 read accesses @243633950 system.cpu4: completed 90000 read accesses @243710816 system.cpu2: completed 90000 read accesses @243974160 system.cpu6: completed 100000 read accesses @268915439 +warn: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 0fc21b2ef..048969ee8 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:21 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:09:08 -M5 executing on piton +M5 compiled Nov 5 2008 18:30:06 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 19:01:52 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 2dc579fd2..c935ec207 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/n/iceaxe/Users/nate/work/m5/work/configs/boot/netperf-server.rcS +readfile=/z/hsul/work/m5/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -35,7 +35,7 @@ side_b=drivesys.membus.port[0] [drivesys.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer clock=1 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=drivesys.cpu.dtb function_trace=false function_trace_start=0 +interrupts=drivesys.cpu.interrupts itb=drivesys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -66,6 +67,9 @@ icache_port=drivesys.membus.port[2] type=AlphaDTB size=64 +[drivesys.cpu.interrupts] +type=AlphaInterrupts + [drivesys.cpu.itb] type=AlphaITB size=48 @@ -699,7 +703,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/n/iceaxe/Users/nate/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/z/hsul/work/m5/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -720,7 +724,7 @@ side_b=testsys.membus.port[0] [testsys.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer clock=1 cpu_id=0 defer_registration=false @@ -730,6 +734,7 @@ do_statistics_insts=true dtb=testsys.cpu.dtb function_trace=false function_trace_start=0 +interrupts=testsys.cpu.interrupts itb=testsys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -751,6 +756,9 @@ icache_port=testsys.membus.port[2] type=AlphaDTB size=64 +[testsys.cpu.interrupts] +type=AlphaInterrupts + [testsys.cpu.itb] type=AlphaITB size=48 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 6315d7b3d..11d12fd63 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 162488534 # Simulator instruction rate (inst/s) -host_mem_usage 477336 # Number of bytes of host memory used -host_seconds 1.68 # Real time elapsed on the host -host_tick_rate 118897556170 # Simulator tick rate (ticks/s) +host_inst_rate 161007148 # Simulator instruction rate (inst/s) +host_mem_usage 478492 # Number of bytes of host memory used +host_seconds 1.70 # Real time elapsed on the host +host_tick_rate 117815722486 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294177 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 147646773096 # Simulator instruction rate (inst/s) -host_mem_usage 477336 # Number of bytes of host memory used +host_inst_rate 142489143379 # Simulator instruction rate (inst/s) +host_mem_usage 478492 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 399988804 # Simulator tick rate (ticks/s) +host_tick_rate 385850761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294177 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index c0d2c6cc2..73103c03f 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -2,5 +2,5 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 ivlb instruction encountered. +warn: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 3d3f5d1b8..487c48aa8 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:28:13 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint -- cgit v1.2.3 From c981b7ed50167a9598f6f8773ab78b47b81aa08a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 9 Nov 2008 21:57:15 -0800 Subject: X86: Add x86 reference output for the timing CPU. --- .../00.gzip/ref/x86/linux/simple-timing/config.ini | 193 ++++ .../ref/x86/linux/simple-timing/m5stats.txt | 234 +++++ .../00.gzip/ref/x86/linux/simple-timing/stderr | 9 + .../00.gzip/ref/x86/linux/simple-timing/stdout | 47 + .../10.mcf/ref/x86/linux/simple-timing/config.ini | 193 ++++ .../10.mcf/ref/x86/linux/simple-timing/m5stats.txt | 234 +++++ .../10.mcf/ref/x86/linux/simple-timing/mcf.out | 999 +++++++++++++++++++++ .../long/10.mcf/ref/x86/linux/simple-timing/stderr | 4 + .../long/10.mcf/ref/x86/linux/simple-timing/stdout | 32 + .../ref/x86/linux/simple-timing/config.ini | 193 ++++ .../ref/x86/linux/simple-timing/m5stats.txt | 234 +++++ .../20.parser/ref/x86/linux/simple-timing/stderr | 7 + .../20.parser/ref/x86/linux/simple-timing/stdout | 75 ++ .../ref/x86/linux/simple-timing/config.ini | 193 ++++ .../ref/x86/linux/simple-timing/m5stats.txt | 234 +++++ .../60.bzip2/ref/x86/linux/simple-timing/stderr | 7 + .../60.bzip2/ref/x86/linux/simple-timing/stdout | 30 + .../ref/x86/linux/simple-timing/config.ini | 193 ++++ .../ref/x86/linux/simple-timing/m5stats.txt | 234 +++++ .../70.twolf/ref/x86/linux/simple-timing/smred.out | 276 ++++++ .../70.twolf/ref/x86/linux/simple-timing/smred.pin | 17 + .../70.twolf/ref/x86/linux/simple-timing/smred.pl1 | 11 + .../70.twolf/ref/x86/linux/simple-timing/smred.pl2 | 2 + .../70.twolf/ref/x86/linux/simple-timing/smred.sav | 18 + .../70.twolf/ref/x86/linux/simple-timing/smred.sv2 | 19 + .../70.twolf/ref/x86/linux/simple-timing/smred.twf | 29 + .../70.twolf/ref/x86/linux/simple-timing/stderr | 6 + .../70.twolf/ref/x86/linux/simple-timing/stdout | 31 + .../ref/x86/linux/simple-timing/config.ini | 193 ++++ .../ref/x86/linux/simple-timing/m5stats.txt | 232 +++++ .../00.hello/ref/x86/linux/simple-timing/stderr | 4 + .../00.hello/ref/x86/linux/simple-timing/stdout | 17 + 32 files changed, 4200 insertions(+) create mode 100644 tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt create mode 100755 tests/long/00.gzip/ref/x86/linux/simple-timing/stderr create mode 100755 tests/long/00.gzip/ref/x86/linux/simple-timing/stdout create mode 100644 tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt create mode 100644 tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out create mode 100755 tests/long/10.mcf/ref/x86/linux/simple-timing/stderr create mode 100755 tests/long/10.mcf/ref/x86/linux/simple-timing/stdout create mode 100644 tests/long/20.parser/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt create mode 100755 tests/long/20.parser/ref/x86/linux/simple-timing/stderr create mode 100755 tests/long/20.parser/ref/x86/linux/simple-timing/stdout create mode 100644 tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt create mode 100755 tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr create mode 100755 tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 create mode 100644 tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf create mode 100755 tests/long/70.twolf/ref/x86/linux/simple-timing/stderr create mode 100755 tests/long/70.twolf/ref/x86/linux/simple-timing/stdout create mode 100644 tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini create mode 100644 tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt create mode 100755 tests/quick/00.hello/ref/x86/linux/simple-timing/stderr create mode 100755 tests/quick/00.hello/ref/x86/linux/simple-timing/stdout (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..7d5cc5629 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..76b073830 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1159099 # Simulator instruction rate (inst/s) +host_mem_usage 201888 # Number of bytes of host memory used +host_seconds 1397.12 # Real time elapsed on the host +host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 2.554133 # Number of seconds simulated +sim_ticks 2554132875000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses +system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses +system.cpu.dcache.overall_misses 506099 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 439707 # number of replacements +system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use +system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 308507 # number of writebacks +system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 721 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 721 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use +system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 161820 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 282704 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 82097 # number of replacements +system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61702 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5108265750 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr b/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..12f446c64 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout b/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..5b0e0d9ff --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:23:58 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2554132875000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..106b52826 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:268435455 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..21761f34b --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1094085 # Simulator instruction rate (inst/s) +host_mem_usage 336424 # Number of bytes of host memory used +host_seconds 246.51 # Real time elapsed on the host +host_tick_rate 2009645019 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269697303 # Number of instructions simulated +sim_seconds 0.495388 # Number of seconds simulated +sim_ticks 495387670000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.899641 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.899641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12833889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 12146358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20116.007644 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 43840123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 37302028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20116.007644 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 120039828 # number of overall hits +system.cpu.dcache.overall_miss_latency 43840123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2179365 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 37302028000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2049944 # number of replacements +system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use +system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 229129 # number of writebacks +system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses 807 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 331462528 # number of overall hits +system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses 807 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use +system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5400304000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10027680000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1862007 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10027680000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192840 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 108885 # number of replacements +system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 70892 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 990775340 # number of cpu cycles simulated +system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.num_refs 124054655 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() 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b/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..70a595464 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 01:13:22 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 495387670000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..d6948bfb4 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..803dc9bdb --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 588841 # Simulator instruction rate (inst/s) +host_mem_usage 206816 # Number of bytes of host memory used +host_seconds 2539.72 # Real time elapsed on the host +host_tick_rate 941590971 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1495492697 # Number of instructions simulated +sim_seconds 2.391380 # Number of seconds simulated +sim_ticks 2391380378000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 530069450 # number of overall hits +system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3192961 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2513875 # number of replacements +system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1463913 # number of writebacks +system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1737372102 # number of overall hits +system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses 2813 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use +system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1310104 # number of overall hits +system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1210680 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 663512 # number of replacements +system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 481430 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4782760756 # number of cpu cycles simulated +system.cpu.num_insts 1495492697 # Number of instructions executed +system.cpu.num_refs 533549000 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stderr b/tests/long/20.parser/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stdout b/tests/long/20.parser/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..f24226fff --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 9 2008 18:23:31 +M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e +M5 commit date Sat Nov 08 21:06:07 2008 -0800 +M5 started Nov 9 2008 18:34:37 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 2391380378000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..caa9f8677 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5c98d4cbd --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1139442 # Simulator instruction rate (inst/s) +host_mem_usage 201800 # Number of bytes of host memory used +host_seconds 4083.77 # Real time elapsed on the host +host_tick_rate 1872105757 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4653219791 # Number of instructions simulated +sim_seconds 7.645253 # Number of seconds simulated +sim_ticks 7645253019000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1668242528 # number of overall hits +system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470550 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 9108982 # number of replacements +system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244013 # number of writebacks +system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 675 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5670421196 # number of overall hits +system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 675 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use +system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5328546 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785207 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2772128 # number of replacements +system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199171 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 15290506038 # number of cpu cycles simulated +system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.num_refs 1686313781 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..c5e3246b3 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 10:43:38 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 7645253019000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..86cbaffb4 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..897f4bc38 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 937563 # Simulator instruction rate (inst/s) +host_mem_usage 210412 # Number of bytes of host memory used +host_seconds 233.15 # Real time elapsed on the host +host_tick_rate 1447418160 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218595322 # Number of instructions simulated +sim_seconds 0.337470 # Number of seconds simulated +sim_ticks 337469714000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 77163409 # number of overall hits +system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1920 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 27 # number of replacements +system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use +system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 260013903 # number of overall hits +system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 4693 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 2835 # number of replacements +system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use +system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1855 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4732 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 674939428 # number of cpu cycles simulated +system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.num_refs 77165364 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr b/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..27f336eb4 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,6 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout b/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..764f17d51 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 9 2008 18:23:31 +M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e +M5 commit date Sat Nov 08 21:06:07 2008 -0800 +M5 started Nov 9 2008 18:29:22 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 337469714000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..6b3961ac8 --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..cb9de2cde --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,232 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 106773 # Simulator instruction rate (inst/s) +host_mem_usage 197592 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 379942758 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9493 # Number of instructions simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33851000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses +system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1835 # number of overall hits +system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses +system.cpu.dcache.overall_misses 152 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use +system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses +system.cpu.icache.demand_misses 228 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 10779 # number of overall hits +system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses +system.cpu.icache.overall_misses 228 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use +system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 360 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 67702 # number of cpu cycles simulated +system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr b/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout b/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..9c811f04f --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:19:20 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 33851000 because target called exit() -- cgit v1.2.3 From bcfd284d24e1321de863b7578e7ba567a69ba44f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 13 Nov 2008 23:30:15 -0800 Subject: X86: Update the mcf stats. I must have missed updating these for the change to send both parts of a split packet at the same time. --- .../10.mcf/ref/x86/linux/simple-timing/m5stats.txt | 44 +++++++++++----------- .../long/10.mcf/ref/x86/linux/simple-timing/stdout | 8 ++-- 2 files changed, 26 insertions(+), 26 deletions(-) (limited to 'tests') diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt index 21761f34b..94a44a507 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1094085 # Simulator instruction rate (inst/s) -host_mem_usage 336424 # Number of bytes of host memory used -host_seconds 246.51 # Real time elapsed on the host -host_tick_rate 2009645019 # Simulator tick rate (ticks/s) +host_inst_rate 1084581 # Simulator instruction rate (inst/s) +host_mem_usage 336400 # Number of bytes of host memory used +host_seconds 248.67 # Real time elapsed on the host +host_tick_rate 1992187591 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269697303 # Number of instructions simulated sim_seconds 0.495388 # Number of seconds simulated @@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.899641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.899641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12833889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 12146358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20116.007644 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43840123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 37302028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20116.007644 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 120039828 # number of overall hits -system.cpu.dcache.overall_miss_latency 43840123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses system.cpu.dcache.overall_misses 2179365 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 37302028000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -144,9 +144,9 @@ system.cpu.icache.warmup_cycle 0 # Cy system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5400304000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles @@ -182,10 +182,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10027680000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -196,11 +196,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1862007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10027680000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses system.cpu.l2cache.overall_misses 192840 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout index 70a595464..a552023cf 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 01:13:22 +M5 compiled Nov 13 2008 21:51:42 +M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 +M5 commit date Sun Nov 09 21:57:15 2008 -0800 +M5 started Nov 13 2008 21:51:43 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -- cgit v1.2.3 From 47789cc9745f3f708f3d6fb6e609fe3796fc00e4 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 17 Nov 2008 14:11:09 -0500 Subject: Update stats for brk fix (cset f28f020f3006). --- .../ref/sparc/linux/simple-timing/m5stats.txt | 104 ++++++++++----------- .../70.twolf/ref/sparc/linux/simple-timing/stdout | 12 +-- 2 files changed, 57 insertions(+), 59 deletions(-) (limited to 'tests') diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index c4bd23868..304bdc3f9 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1243989 # Simulator instruction rate (inst/s) -host_mem_usage 207864 # Number of bytes of host memory used -host_seconds 155.50 # Real time elapsed on the host -host_tick_rate 1740014863 # Simulator tick rate (ticks/s) +host_inst_rate 1229412 # Simulator instruction rate (inst/s) +host_mem_usage 207888 # Number of bytes of host memory used +host_seconds 157.35 # Real time elapsed on the host +host_tick_rate 1719613407 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270579 # Number of seconds simulated -sim_ticks 270578958000 # Number of ticks simulated +sim_ticks 270578573000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -31,16 +31,16 @@ system.cpu.dcache.SwapReq_mshr_misses 2 # nu system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 48472.729627 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -49,14 +49,14 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 89936000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 85118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -64,14 +64,14 @@ system.cpu.dcache.overall_accesses 76711508 # nu system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76709902 # number of overall hits -system.cpu.dcache.overall_miss_latency 89936000 # number of overall miss cycles +system.cpu.dcache.overall_hits 76709909 # number of overall hits +system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1606 # number of overall misses +system.cpu.dcache.overall_misses 1599 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 85118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 26 # number of replacements -system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2 # number of replacements +system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1235.200907 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 23 # number of writebacks +system.cpu.dcache.writebacks 2 # number of writebacks system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency @@ -148,20 +148,20 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.567399 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 56420000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -181,42 +181,42 @@ system.cpu.l2cache.UpgradeReq_misses 25 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.127019 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 269360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 207200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.overall_miss_latency 269360000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5180 # number of overall misses +system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5173 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 207200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,14 +229,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.336317 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541157916 # number of cpu cycles simulated +system.cpu.numCycles 541157146 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index 98f64dfde..e76e61d8a 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:20 +M5 compiled Nov 17 2008 13:45:49 +M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f +M5 commit date Sat Nov 15 23:42:11 2008 -0500 +M5 started Nov 17 2008 13:46:11 M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 270578958000 because target called exit() +122 123 124 Exiting @ tick 270578573000 because target called exit() -- cgit v1.2.3 From f1430941cf17fc15a8b86eba41f9c856ad9347d8 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 5 Dec 2008 12:09:29 -0500 Subject: This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. --- .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 300 ++++---- .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../00.gzip/ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 10 +- .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/alpha/linux/tsunami-o3-dual/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-o3-dual/stdout | 8 +- .../ref/alpha/linux/tsunami-o3/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-o3/stdout | 8 +- .../30.eon/ref/alpha/tru64/o3-timing/m5stats.txt | 78 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../30.eon/ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../30.eon/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 168 ++--- .../40.perlbmk/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 280 ++++---- .../50.vortex/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../50.vortex/ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 118 ++-- .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 8 +- .../60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../long/60.bzip2/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../60.bzip2/ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../60.bzip2/ref/alpha/tru64/simple-timing/stdout | 8 +- .../70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt | 94 +-- .../long/70.twolf/ref/alpha/tru64/o3-timing/stdout | 10 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../70.twolf/ref/alpha/tru64/simple-atomic/stdout | 10 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 112 +-- .../70.twolf/ref/alpha/tru64/simple-timing/stdout | 10 +- .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 536 +++++++------- .../00.hello/ref/alpha/linux/o3-timing/stdout | 10 +- .../ref/alpha/linux/simple-atomic/m5stats.txt | 34 +- .../00.hello/ref/alpha/linux/simple-atomic/stdout | 10 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 176 ++--- .../00.hello/ref/alpha/linux/simple-timing/stdout | 10 +- .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 8 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 6 +- .../00.hello/ref/alpha/tru64/simple-atomic/stdout | 8 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 8 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 782 ++++++++++----------- .../ref/alpha/linux/o3-timing/stdout | 10 +- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 8 +- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 8 +- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 8 +- .../linux/tsunami-simple-timing-dual/m5stats.txt | 8 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 8 +- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 8 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 8 +- .../ref/alpha/eio/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/eio/simple-atomic/stdout | 8 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 8 +- .../ref/alpha/eio/simple-timing/stdout | 8 +- .../ref/alpha/eio/simple-atomic-mp/m5stats.txt | 7 +- .../ref/alpha/eio/simple-atomic-mp/stderr | 5 +- .../ref/alpha/eio/simple-atomic-mp/stdout | 12 +- .../ref/alpha/eio/simple-timing-mp/m5stats.txt | 7 +- .../ref/alpha/eio/simple-timing-mp/stderr | 5 +- .../ref/alpha/eio/simple-timing-mp/stdout | 12 +- .../50.memtest/ref/alpha/linux/memtest/m5stats.txt | 6 +- .../50.memtest/ref/alpha/linux/memtest/stdout | 8 +- .../linux/twosys-tsunami-simple-atomic/config.ini | 4 +- .../linux/twosys-tsunami-simple-atomic/m5stats.txt | 14 +- .../linux/twosys-tsunami-simple-atomic/stdout | 8 +- 77 files changed, 1605 insertions(+), 1615 deletions(-) mode change 100644 => 100755 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr mode change 100644 => 100755 tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout mode change 100644 => 100755 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr mode change 100644 => 100755 tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8e02b536f..4e08b47b3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718863 # Number of BTB hits -global.BPredUnit.BTBLookups 73181378 # Number of BTB lookups +global.BPredUnit.BTBHits 65718859 # Number of BTB hits +global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted -global.BPredUnit.lookups 76039028 # Number of BP lookups +global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +global.BPredUnit.lookups 76039018 # Number of BP lookups global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 204243 # Simulator instruction rate (inst/s) -host_mem_usage 202188 # Number of bytes of host memory used -host_seconds 2769.01 # Real time elapsed on the host -host_tick_rate 60338522 # Simulator tick rate (ticks/s) +host_inst_rate 193677 # Simulator instruction rate (inst/s) +host_mem_usage 202220 # Number of bytes of host memory used +host_seconds 2920.07 # Real time elapsed on the host +host_tick_rate 57217081 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078186500 # Number of ticks simulated +sim_ticks 167078146500 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711309 +system.cpu.commit.COM:committed_per_cycle.samples 322711249 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088817 3349.40% + 0 108088757 3349.40% 1 100475751 3113.49% 2 37367184 1157.91% 3 9733028 301.60% 4 10676883 330.85% - 5 22147835 686.30% + 5 22147835 686.31% 6 13251874 410.64% 7 3269687 101.32% 8 17700250 548.49% @@ -46,22 +46,22 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146791 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.218520 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.236909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293702 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853089 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636812 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688309500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) @@ -77,36 +77,36 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # m system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598112 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.568696 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415338 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177518881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182774 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629219 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708104495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 152598112 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.568696 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415338 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177518881 # number of overall miss cycles +system.cpu.dcache.overall_hits 149415339 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182774 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629219 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708104495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 3182768 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,99 +123,99 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 468828 # number of replacements system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.202443 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001656 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126621000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202535 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696251 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199512 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896072 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869869 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163077395 # DTB accesses +system.cpu.dtb.accesses 163077390 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163013885 # DTB hits +system.cpu.dtb.hits 163013880 # DTB hits system.cpu.dtb.misses 63510 # DTB misses -system.cpu.dtb.read_accesses 122284114 # DTB read accesses +system.cpu.dtb.read_accesses 122284109 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260501 # DTB read hits +system.cpu.dtb.read_hits 122260496 # DTB read hits system.cpu.dtb.read_misses 23613 # DTB read misses system.cpu.dtb.write_accesses 40793281 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 40753384 # DTB write hits system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039028 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014416 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864070 # Number of instructions fetch has processed +system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014416 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411082 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091428 # Number of inst fetches per cycle +system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581179 +system.cpu.fetch.rateDist.samples 332581112 system.cpu.fetch.rateDist.min_value 0 - 0 201466276 6057.66% - 1 10360751 311.53% - 2 15882086 477.54% + 0 201466223 6057.66% + 1 10360747 311.53% + 2 15882081 477.54% 3 14599006 438.96% 4 12362950 371.73% - 5 14822133 445.67% + 5 14822134 445.67% 6 6008311 180.66% 7 3307530 99.45% - 8 53772136 1616.81% + 8 53772130 1616.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66014416 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36203.165098 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35497.228381 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013247 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.417960 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014416 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36203.165098 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013247 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66014416 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36203.165098 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency +system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013247 # number of overall hits -system.cpu.icache.overall_miss_latency 42321500 # number of overall miss cycles +system.cpu.icache.overall_hits 66013237 # number of overall hits +system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses system.cpu.icache.overall_misses 1169 # number of overall misses system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -232,40 +232,40 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803769 # Cycle average of tags in use -system.cpu.icache.total_refs 66013247 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use +system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316863 # Number of branches executed +system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316859 # Number of branches executed system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017998 # number of memory reference insts executed +system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed system.cpu.iew.EXEC:stores 41189464 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237026 # num instructions consuming a value -system.cpu.iew.WB:count 596051181 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value +system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375822 # num instructions producing a value -system.cpu.iew.WB:rate 1.783749 # insts written-back per cycle -system.cpu.iew.WB:sent 597227214 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671564 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251991 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977207 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395375802 # num instructions producing a value +system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle +system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663380014 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828534 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459967 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258177 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2444 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869869 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84553 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927697 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540318 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692478 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692478 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718144 # Type of FU issued +system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834867 72.45% # Type of FU issued + IntAlu 438834840 72.45% # Type of FU issued IntMult 6546 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued @@ -293,16 +293,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855458 20.61% # Type of FU issued + MemRead 124855453 20.61% # Type of FU issued MemWrite 42021230 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 7232327 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390835 74.54% # attempts to use FU when none available + IntAlu 5390831 74.54% # attempts to use FU when none available IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -317,31 +317,31 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 332581179 +system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92203834 2772.37% - 1 67051351 2016.09% - 2 80133785 2409.45% - 3 36043476 1083.75% + 0 92203773 2772.37% + 1 67051353 2016.09% + 2 80133780 2409.45% + 3 36043478 1083.75% 4 30084945 904.59% 5 14579095 438.36% - 6 10850498 326.25% + 6 10850493 326.25% 7 1143008 34.37% 8 491187 14.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382610 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718144 # Number of instructions issued +system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66014456 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014446 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66014416 # ITB hits +system.cpu.itb.hits 66014406 # ITB hits system.cpu.itb.misses 40 # ITB misses system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency @@ -353,13 +353,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.958543 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.588334 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227944500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110234000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) @@ -382,29 +382,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.680834 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020758500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102616500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.680834 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020758500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses system.cpu.l2cache.overall_misses 292443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102616500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,29 +421,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 85262 # number of replacements system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.158558 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.numCycles 334156374 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214869 # Number of cycles rename is blocking +system.cpu.numCycles 334156294 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587364 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899466 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816435 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424801 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473844 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116401000 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869869 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195269 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618955 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660301 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36535 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index 8133509b4..4ea4c0572 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:40:15 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:25:12 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index c226b8d4c..96bd5579b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3818661 # Simulator instruction rate (inst/s) -host_mem_usage 193720 # Number of bytes of host memory used -host_seconds 157.61 # Real time elapsed on the host -host_tick_rate 1909343313 # Simulator tick rate (ticks/s) +host_inst_rate 3417919 # Simulator instruction rate (inst/s) +host_mem_usage 193752 # Number of bytes of host memory used +host_seconds 176.09 # Real time elapsed on the host +host_tick_rate 1708971531 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 63dd02070..4f98f10a9 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:05:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:47 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index cf41fab83..5fbfd3d3d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1993278 # Simulator instruction rate (inst/s) -host_mem_usage 201176 # Number of bytes of host memory used -host_seconds 301.94 # Real time elapsed on the host -host_tick_rate 2576653236 # Simulator tick rate (ticks/s) +host_inst_rate 1797646 # Simulator instruction rate (inst/s) +host_mem_usage 201208 # Number of bytes of host memory used +host_seconds 334.80 # Real time elapsed on the host +host_tick_rate 2323765799 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225224 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 7bb6940cc..912067c8f 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:08:13 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt index c498474d4..cbdec272c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt @@ -16,10 +16,10 @@ global.BPredUnit.lookups 10092697 # Nu global.BPredUnit.lookups 5530798 # Number of BP lookups global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 130617 # Simulator instruction rate (inst/s) -host_mem_usage 292856 # Number of bytes of host memory used -host_seconds 429.91 # Real time elapsed on the host -host_tick_rate 4437424208 # Simulator tick rate (ticks/s) +host_inst_rate 121094 # Simulator instruction rate (inst/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 463.72 # Real time elapsed on the host +host_tick_rate 4113887240 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout index 3839b0231..bace1f0ca 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:30:16 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:35:52 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt index 7b34dbd2c..4860b3f1d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828381 # Nu global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted global.BPredUnit.lookups 14559443 # Number of BP lookups global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 200905 # Simulator instruction rate (inst/s) -host_mem_usage 290800 # Number of bytes of host memory used -host_seconds 264.07 # Real time elapsed on the host -host_tick_rate 7071490969 # Simulator tick rate (ticks/s) +host_inst_rate 123231 # Simulator instruction rate (inst/s) +host_mem_usage 290820 # Number of bytes of host memory used +host_seconds 430.51 # Real time elapsed on the host +host_tick_rate 4337505567 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout index 4989a72b8..f6f2f7d37 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:28:27 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:31:00 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 756f9cdc8..704dd86aa 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted global.BPredUnit.lookups 62209737 # Number of BP lookups global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 185748 # Simulator instruction rate (inst/s) -host_mem_usage 209620 # Number of bytes of host memory used -host_seconds 2021.96 # Real time elapsed on the host -host_tick_rate 66765374 # Simulator tick rate (ticks/s) +host_inst_rate 151728 # Simulator instruction rate (inst/s) +host_mem_usage 209656 # Number of bytes of host memory used +host_seconds 2475.31 # Real time elapsed on the host +host_tick_rate 54537175 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. @@ -54,13 +54,13 @@ system.cpu.cpi_total 0.718880 # CP system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33012.273524 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95499598 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 56484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1711 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses @@ -77,20 +77,20 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # m system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40460.273163 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169002314 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 602471492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19724 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses @@ -98,14 +98,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169002314 # number of overall hits -system.cpu.dcache.overall_miss_latency 602471492 # number of overall miss cycles +system.cpu.dcache.overall_hits 169002312 # number of overall hits +system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19724 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15431 # number of overall MSHR hits +system.cpu.dcache.overall_misses 19726 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 782 # nu system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use -system.cpu.dcache.total_refs 169002561 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 635 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked @@ -237,21 +237,21 @@ system.cpu.icache.total_refs 63861348 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50976852 # Number of branches executed +system.cpu.iew.EXEC:branches 50976851 # Number of branches executed system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed system.cpu.iew.EXEC:stores 80676625 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285463488 # num instructions consuming a value -system.cpu.iew.WB:count 415481244 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value +system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200770523 # num instructions producing a value +system.cpu.iew.WB:producers 200770520 # num instructions producing a value system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle -system.cpu.iew.WB:sent 416287471 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6390314 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions @@ -259,8 +259,8 @@ system.cpu.iew.iewDispSquashedInsts 6302760 # Nu system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10261542 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 419338657 # Number of executed instructions +system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall @@ -278,13 +278,13 @@ system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # N system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5542510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429600199 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 166319017 38.71% # Type of FU issued + IntAlu 166319014 38.71% # Type of FU issued IntMult 2152935 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 35077566 8.17% # Type of FU issued @@ -321,11 +321,11 @@ system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 99465935 3685.94% 1 57766030 2140.65% - 2 39984555 1481.72% - 3 29664957 1099.30% - 4 23966119 888.12% - 5 10452564 387.34% - 6 5712017 211.67% + 2 39984554 1481.72% + 3 29664959 1099.30% + 4 23966120 888.12% + 5 10452563 387.34% + 6 5712016 211.67% 7 2252970 83.49% 8 587500 21.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 @@ -333,12 +333,12 @@ system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429600199 # Number of instructions issued +system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68228106 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 63866476 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 63866189 # ITB hits diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index e6ff44d85..2bc3bdeed 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:33:01 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index 651cb243c..520bb514f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3323718 # Simulator instruction rate (inst/s) -host_mem_usage 201288 # Number of bytes of host memory used -host_seconds 119.95 # Real time elapsed on the host -host_tick_rate 1661856596 # Simulator tick rate (ticks/s) +host_inst_rate 3407773 # Simulator instruction rate (inst/s) +host_mem_usage 201328 # Number of bytes of host memory used +host_seconds 116.99 # Real time elapsed on the host +host_tick_rate 1703884563 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 913be9f23..bb141923e 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:17 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:02 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 3ff76c5f4..99f2593a9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1753697 # Simulator instruction rate (inst/s) -host_mem_usage 208744 # Number of bytes of host memory used -host_seconds 227.33 # Real time elapsed on the host -host_tick_rate 2495737915 # Simulator tick rate (ticks/s) +host_inst_rate 1526276 # Simulator instruction rate (inst/s) +host_mem_usage 208780 # Number of bytes of host memory used +host_seconds 261.20 # Real time elapsed on the host +host_tick_rate 2172088412 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index caf805d08..c8c05bf7d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:58:04 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:22:18 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt index 9069620c7..2e0ae6799 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt @@ -6,15 +6,15 @@ global.BPredUnit.BTBLookups 294213603 # Nu global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -global.BPredUnit.lookups 349424732 # Number of BP lookups -global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target. -host_inst_rate 250324 # Simulator instruction rate (inst/s) -host_mem_usage 209520 # Number of bytes of host memory used -host_seconds 7282.75 # Real time elapsed on the host -host_tick_rate 96826033 # Simulator tick rate (ticks/s) +global.BPredUnit.lookups 349424731 # Number of BP lookups +global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +host_inst_rate 157306 # Simulator instruction rate (inst/s) +host_mem_usage 209560 # Number of bytes of host memory used +host_seconds 11589.17 # Real time elapsed on the host +host_tick_rate 60846406 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated @@ -26,14 +26,14 @@ system.cpu.commit.COM:bw_limited 0 # nu system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 1310002800 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 603585598 4607.51% - 1 273587002 2088.45% + 0 603585596 4607.51% + 1 273587005 2088.45% 2 174037133 1328.52% - 3 65399709 499.23% - 4 48333002 368.95% - 5 34003109 259.57% - 6 18481317 141.08% - 7 23715686 181.04% + 3 65399708 499.23% + 4 48333001 368.95% + 5 34003110 259.57% + 6 18481318 141.08% + 7 23715685 181.04% 8 68860244 525.65% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,21 +46,21 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 696013928 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 465737270 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37550.777258 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 463802713 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72644119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 475264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses @@ -77,35 +77,35 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # m system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 440.284638 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 676532166 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674038254 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94226058985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2493912 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 959838 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 676532166 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674038254 # number of overall hits -system.cpu.dcache.overall_miss_latency 94226058985 # number of overall miss cycles +system.cpu.dcache.overall_hits 674038251 # number of overall hits +system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2493912 # number of overall misses -system.cpu.dcache.overall_mshr_hits 959838 # number of overall MSHR hits +system.cpu.dcache.overall_misses 2493914 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses @@ -124,39 +124,39 @@ system.cpu.dcache.replacements 1526847 # nu system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use -system.cpu.dcache.total_refs 674050685 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2936172394 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 716337475 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561391035 # Number of cycles decode is running +system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 775959989 # DTB accesses +system.cpu.dtb.accesses 775959987 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 775335045 # DTB hits +system.cpu.dtb.hits 775335043 # DTB hits system.cpu.dtb.misses 624944 # DTB misses -system.cpu.dtb.read_accesses 516992086 # DTB read accesses +system.cpu.dtb.read_accesses 516992085 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 516404964 # DTB read hits +system.cpu.dtb.read_hits 516404963 # DTB read hits system.cpu.dtb.read_misses 587122 # DTB read misses -system.cpu.dtb.write_accesses 258967903 # DTB write accesses +system.cpu.dtb.write_accesses 258967902 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258930081 # DTB write hits +system.cpu.dtb.write_hits 258930080 # DTB write hits system.cpu.dtb.write_misses 37822 # DTB write misses -system.cpu.fetch.Branches 349424732 # Number of branches that fetch encountered +system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3030218621 # Number of instructions fetch has processed +system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 290350353 # Number of branches that fetch has predicted taken +system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 1410161885 @@ -165,9 +165,9 @@ system.cpu.fetch.rateDist.min_value 0 1 53463106 379.13% 2 39766072 282.00% 3 63538024 450.57% - 4 121390718 860.83% + 4 121390719 860.83% 5 35256321 250.02% - 6 38761683 274.87% + 6 38761682 274.87% 7 6988644 49.56% 8 220409277 1563.01% system.cpu.fetch.rateDist.max_value 8 @@ -237,30 +237,30 @@ system.cpu.icache.total_refs 348437250 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274534146 # Number of branches executed +system.cpu.iew.EXEC:branches 274534145 # Number of branches executed system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate -system.cpu.iew.EXEC:refs 776495505 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258968901 # Number of stores executed +system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258968900 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1631503181 # num instructions consuming a value -system.cpu.iew.WB:count 2002130592 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value +system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136229271 # num instructions producing a value +system.cpu.iew.WB:producers 1136229268 # num instructions producing a value system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle -system.cpu.iew.WB:sent 2003425038 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 31680134 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655954744 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2715209776 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 517526604 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85279851 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2004227959 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144359442 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30863144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2089507810 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2752 0.00% # Type of FU issued - IntAlu 1204412682 57.64% # Type of FU issued + IntAlu 1204412678 57.64% # Type of FU issued IntMult 17591 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 27851349 1.33% # Type of FU issued @@ -294,11 +294,11 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 557993260 26.70% # Type of FU issued - MemWrite 283770832 13.58% # Type of FU issued + MemWrite 283770831 13.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37093549 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available @@ -311,34 +311,34 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 28032979 75.57% # attempts to use FU when none available - MemWrite 9052279 24.40% # attempts to use FU when none available + MemRead 28032977 75.57% # attempts to use FU when none available + MemWrite 9052278 24.40% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 537278440 3810.05% - 1 285217725 2022.59% - 2 273546794 1939.83% - 3 154810622 1097.82% - 4 63341839 449.18% - 5 51438518 364.77% - 6 32491112 230.41% - 7 9036667 64.08% + 0 537278436 3810.05% + 1 285217724 2022.59% + 2 273546804 1939.83% + 3 154810620 1097.82% + 4 63341841 449.18% + 5 51438515 364.77% + 6 32491109 230.41% + 7 9036668 64.08% 8 3000168 21.28% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate -system.cpu.iq.iqInstsAdded 2386031658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2089507810 # Number of instructions issued +system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 562621265 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12403595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 516017441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 348448092 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 348447899 # ITB hits diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout index 14154444a..7f7e7a869 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 841932c00..028814426 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5368625 # Simulator instruction rate (inst/s) -host_mem_usage 200452 # Number of bytes of host memory used -host_seconds 374.21 # Real time elapsed on the host -host_tick_rate 2684890322 # Simulator tick rate (ticks/s) +host_inst_rate 3237524 # Simulator instruction rate (inst/s) +host_mem_usage 200500 # Number of bytes of host memory used +host_seconds 620.53 # Real time elapsed on the host +host_tick_rate 1619110797 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index 315befb59..30786b895 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:06:43 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:39 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 6e65ba05d..c24e3b046 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2795907 # Simulator instruction rate (inst/s) -host_mem_usage 207904 # Number of bytes of host memory used -host_seconds 718.55 # Real time elapsed on the host -host_tick_rate 3917565207 # Simulator tick rate (ticks/s) +host_inst_rate 1407375 # Simulator instruction rate (inst/s) +host_mem_usage 207960 # Number of bytes of host memory used +host_seconds 1427.47 # Real time elapsed on the host +host_tick_rate 1971983298 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index f4fff795a..5e421444e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:28:15 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 60ec1554f..36c3049e3 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8039248 # Number of BTB hits -global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups +global.BPredUnit.BTBHits 8039250 # Number of BTB hits +global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted -global.BPredUnit.lookups 16249458 # Number of BP lookups +global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +global.BPredUnit.lookups 16249463 # Number of BP lookups global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 272001 # Simulator instruction rate (inst/s) -host_mem_usage 212988 # Number of bytes of host memory used -host_seconds 292.62 # Real time elapsed on the host -host_tick_rate 92731689 # Simulator tick rate (ticks/s) +host_inst_rate 155507 # Simulator instruction rate (inst/s) +host_mem_usage 212996 # Number of bytes of host memory used +host_seconds 511.82 # Real time elapsed on the host +host_tick_rate 53016132 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134783500 # Number of ticks simulated +sim_ticks 27134794500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51751153 +system.cpu.commit.COM:committed_per_cycle.samples 51751168 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22506428 4348.97% - 1 11357580 2194.65% + 0 22506445 4348.97% + 1 11357579 2194.65% 2 5114502 988.29% 3 3560855 688.07% - 4 2552506 493.23% - 5 1532718 296.17% - 6 1008932 194.96% + 4 2552504 493.23% + 5 1532717 296.17% + 6 1008933 194.96% 7 796739 153.96% - 8 3320893 641.70% + 8 3320894 641.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,21 +46,21 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses @@ -77,35 +77,35 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # m system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838927 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles +system.cpu.dcache.overall_hits 33838925 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199961 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits +system.cpu.dcache.overall_misses 1199965 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses @@ -123,83 +123,83 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200933 # number of replacements system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36599686 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599689 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36425478 # DTB hits +system.cpu.dtb.hits 36425481 # DTB hits system.cpu.dtb.misses 174208 # DTB misses -system.cpu.dtb.read_accesses 21541286 # DTB read accesses +system.cpu.dtb.read_accesses 21541288 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383018 # DTB read hits +system.cpu.dtb.read_hits 21383020 # DTB read hits system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058400 # DTB write accesses +system.cpu.dtb.write_accesses 15058401 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042460 # DTB write hits +system.cpu.dtb.write_hits 15042461 # DTB write hits system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered +system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed +system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken +system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53041252 +system.cpu.fetch.rateDist.samples 53041270 system.cpu.fetch.rateDist.min_value 0 - 0 33206262 6260.46% + 0 33206277 6260.46% 1 1871594 352.86% 2 1529415 288.34% 3 1809626 341.17% 4 3985239 751.35% - 5 1867237 352.03% + 5 1867239 352.04% 6 695846 131.19% 7 1111736 209.60% - 8 6964297 1313.00% + 8 6964298 1313.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses @@ -207,14 +207,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297365 # number of overall hits -system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles +system.cpu.icache.overall_hits 13297366 # number of overall hits +system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88707 # number of overall misses -system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits +system.cpu.icache.overall_misses 88706 # number of overall misses +system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses @@ -232,40 +232,40 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 83888 # number of replacements system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use -system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use +system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745483 # Number of branches executed +system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745486 # Number of branches executed system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate -system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291391 # Number of stores executed +system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate +system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291392 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value -system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value +system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396966 # num instructions producing a value +system.cpu.iew.WB:producers 32396987 # num instructions producing a value system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed +system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47898540 56.12% # Type of FU issued + IntAlu 47898565 56.12% # Type of FU issued IntMult 42953 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 121655 0.14% # Type of FU issued @@ -293,16 +293,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 53 0.00% # Type of FU issued FloatDiv 38535 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21753620 25.49% # Type of FU issued - MemWrite 15368768 18.01% # Type of FU issued + MemRead 21753622 25.49% # Type of FU issued + MemWrite 15368770 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 97095 9.91% # attempts to use FU when none available + IntAlu 97100 9.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -317,28 +317,28 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252 +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17563400 3311.27% - 1 13937997 2627.77% - 2 8266118 1558.43% - 3 4784811 902.09% - 4 4627571 872.45% - 5 2066742 389.65% - 6 1112371 209.72% - 7 454506 85.69% - 8 227736 42.94% + 0 17563410 3311.27% + 1 13937999 2627.76% + 2 8266125 1558.43% + 3 4784809 902.09% + 4 4627568 872.45% + 5 2066740 389.65% + 6 1112374 209.72% + 7 454507 85.69% + 8 227738 42.94% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued +system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 13412237 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 13386072 # ITB hits @@ -354,12 +354,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) @@ -383,13 +383,13 @@ system.cpu.l2cache.blocked_cycles_no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed @@ -397,14 +397,14 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 102894 # number of overall hits system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses system.cpu.l2cache.overall_misses 188071 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,27 +421,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 148779 # number of replacements system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.numCycles 54269568 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking +system.cpu.numCycles 54269590 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index 61aa77324..305b9e178 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:42:31 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index fba592412..7b2d6e4f7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5277091 # Simulator instruction rate (inst/s) -host_mem_usage 203864 # Number of bytes of host memory used -host_seconds 16.74 # Real time elapsed on the host -host_tick_rate 2641544350 # Simulator tick rate (ticks/s) +host_inst_rate 3156054 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 27.99 # Real time elapsed on the host +host_tick_rate 1579824710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index a2c31ed4b..f78544a3c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:00 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 828a42be2..4078e993e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1704355 # Simulator instruction rate (inst/s) -host_mem_usage 211324 # Number of bytes of host memory used -host_seconds 51.83 # Real time elapsed on the host -host_tick_rate 2607795037 # Simulator tick rate (ticks/s) +host_inst_rate 1655989 # Simulator instruction rate (inst/s) +host_mem_usage 211348 # Number of bytes of host memory used +host_seconds 53.35 # Real time elapsed on the host +host_tick_rate 2533794438 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated -sim_ticks 135168711000 # Number of ticks simulated +sim_ticks 135168766000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency @@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # m system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210558 # number of overall misses +system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,12 +73,12 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200247 # number of replacements -system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 143578 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses 147714 # nu system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186874 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -234,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147560 # number of replacements -system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270337422 # number of cpu cycles simulated +system.cpu.numCycles 270337532 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index 8bed4881a..7c7d8426c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:27:23 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:00 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 2aa5eaaa5..2cba4195f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19647325 # Nu global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted global.BPredUnit.lookups 345502589 # Number of BP lookups global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. -host_inst_rate 152874 # Simulator instruction rate (inst/s) -host_mem_usage 201972 # Number of bytes of host memory used -host_seconds 11356.03 # Real time elapsed on the host -host_tick_rate 65366964 # Simulator tick rate (ticks/s) +host_inst_rate 178472 # Simulator instruction rate (inst/s) +host_mem_usage 202004 # Number of bytes of host memory used +host_seconds 9727.25 # Real time elapsed on the host +host_tick_rate 76312348 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index bf92c70e1..46c21a733 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:16 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index c3eb995b5..a74bbb7e5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3454414 # Simulator instruction rate (inst/s) -host_mem_usage 193640 # Number of bytes of host memory used -host_seconds 526.80 # Real time elapsed on the host -host_tick_rate 1733469179 # Simulator tick rate (ticks/s) +host_inst_rate 3337847 # Simulator instruction rate (inst/s) +host_mem_usage 193672 # Number of bytes of host memory used +host_seconds 545.20 # Real time elapsed on the host +host_tick_rate 1674974438 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index 2550b2dca..6c0c37f87 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:32:56 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 65a250806..027e53548 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2843037 # Simulator instruction rate (inst/s) -host_mem_usage 201092 # Number of bytes of host memory used -host_seconds 640.08 # Real time elapsed on the host -host_tick_rate 4261930074 # Simulator tick rate (ticks/s) +host_inst_rate 1294592 # Simulator instruction rate (inst/s) +host_mem_usage 201124 # Number of bytes of host memory used +host_seconds 1405.68 # Real time elapsed on the host +host_tick_rate 1940692275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index e112321fe..15467090e 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:47:24 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 8c4b78811..bf979a603 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted global.BPredUnit.lookups 19468548 # Number of BP lookups global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 134854 # Simulator instruction rate (inst/s) -host_mem_usage 207240 # Number of bytes of host memory used -host_seconds 624.23 # Real time elapsed on the host -host_tick_rate 65390701 # Simulator tick rate (ticks/s) +host_inst_rate 123995 # Simulator instruction rate (inst/s) +host_mem_usage 207276 # Number of bytes of host memory used +host_seconds 678.90 # Real time elapsed on the host +host_tick_rate 60124800 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. @@ -21,20 +21,20 @@ sim_insts 84179709 # Nu sim_seconds 0.040819 # Number of seconds simulated sim_ticks 40818658500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73457195 +system.cpu.commit.COM:committed_per_cycle.samples 73457196 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36278942 4938.79% - 1 18156305 2471.69% - 2 7455514 1014.95% - 3 3880418 528.26% + 0 36278941 4938.79% + 1 18156304 2471.68% + 2 7455517 1014.95% + 3 3880419 528.26% 4 2046448 278.59% 5 1301140 177.13% 6 721823 98.26% 7 760802 103.57% - 8 2855803 388.77% + 8 2855802 388.77% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -54,14 +54,14 @@ system.cpu.cpi_total 0.969798 # CP system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) @@ -84,29 +84,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 26497 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses system.cpu.dcache.overall_misses 9171 # number of overall misses system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,7 +123,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks @@ -131,7 +131,7 @@ system.cpu.decode.DECODE:BlockedCycles 3781084 # Nu system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode @@ -159,9 +159,9 @@ system.cpu.fetch.icacheStallCycles 19230003 # Nu system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81528342 +system.cpu.fetch.rateDist.samples 81528343 system.cpu.fetch.rateDist.min_value 0 - 0 50560377 6201.57% + 0 50560378 6201.57% 1 3114212 381.98% 2 2012618 246.86% 3 3505366 429.96% @@ -236,19 +236,19 @@ system.cpu.icache.tagsinuse 1543.991602 # Cy system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 12812003 # Number of branches executed system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed system.cpu.iew.EXEC:stores 7194632 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value +system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837671 # num instructions producing a value +system.cpu.iew.WB:producers 65837672 # num instructions producing a value system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute @@ -317,11 +317,11 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 35305774 4330.49% - 1 18904883 2318.81% - 2 11574998 1419.75% + 1 18904885 2318.81% + 2 11574997 1419.75% 3 6762756 829.50% 4 5075415 622.53% 5 2394533 293.71% @@ -353,13 +353,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) @@ -382,29 +382,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5110 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,7 +421,7 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -429,7 +429,7 @@ system.cpu.numCycles 81637318 # nu system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index 7f155cd9b..4aef79cf1 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:16:59 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:52 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index f322d0c86..fd63e8611 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5620505 # Simulator instruction rate (inst/s) -host_mem_usage 198560 # Number of bytes of host memory used -host_seconds 16.35 # Real time elapsed on the host -host_tick_rate 2810224606 # Simulator tick rate (ticks/s) +host_inst_rate 2797283 # Simulator instruction rate (inst/s) +host_mem_usage 198592 # Number of bytes of host memory used +host_seconds 32.85 # Real time elapsed on the host +host_tick_rate 1398634763 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index e5e1bfe2b..17a346373 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:18 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index e6e809818..3b3e2ccb7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1922347 # Simulator instruction rate (inst/s) -host_mem_usage 206016 # Number of bytes of host memory used -host_seconds 47.81 # Real time elapsed on the host -host_tick_rate 2483835101 # Simulator tick rate (ticks/s) +host_inst_rate 1637033 # Simulator instruction rate (inst/s) +host_mem_usage 206044 # Number of bytes of host memory used +host_seconds 56.14 # Real time elapsed on the host +host_tick_rate 2115189911 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated -sim_ticks 118747191000 # Number of ticks simulated +sim_ticks 118747246000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency @@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # m system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles +system.cpu.dcache.overall_hits 26494967 # number of overall hits +system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2333 # number of overall misses +system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.dtb.accesses 26497334 # DTB accesses @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 1748 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.970090 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4790 # number of overall misses +system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4791 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -235,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237494382 # number of cpu cycles simulated +system.cpu.numCycles 237494492 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index 50f9ae74a..a43a9ad37 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:41:43 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:54 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cbad9353d..93747295c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 649 # Number of BTB hits -global.BPredUnit.BTBLookups 1748 # Number of BTB lookups +global.BPredUnit.BTBHits 806 # Number of BTB hits +global.BPredUnit.BTBLookups 1937 # Number of BTB lookups global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted -global.BPredUnit.lookups 2108 # Number of BP lookups -global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target. -host_inst_rate 86240 # Simulator instruction rate (inst/s) -host_mem_usage 198988 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 169229614 # Simulator tick rate (ticks/s) +global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted +global.BPredUnit.lookups 2263 # Number of BP lookups +global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +host_inst_rate 7058 # Simulator instruction rate (inst/s) +host_mem_usage 199016 # Number of bytes of host memory used +host_seconds 0.90 # Real time elapsed on the host +host_tick_rate 13784618 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 28 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6297 # Number of instructions simulated +sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12391500 # Number of ticks simulated -system.cpu.commit.COM:branches 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached +sim_ticks 12474500 # Number of ticks simulated +system.cpu.commit.COM:branches 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12114 +system.cpu.commit.COM:committed_per_cycle.samples 12416 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 9249 7634.97% - 1 1607 1326.56% - 2 479 395.41% - 3 271 223.71% - 4 137 113.09% - 5 121 99.88% - 6 87 71.82% - 7 43 35.50% - 8 120 99.06% + 0 9513 7661.89% + 1 1627 1310.41% + 2 488 393.04% + 3 267 215.05% + 4 153 123.23% + 5 104 83.76% + 6 96 77.32% + 7 53 42.69% + 8 115 92.62% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 6314 # Number of instructions committed -system.cpu.commit.COM:loads 1168 # Number of loads committed +system.cpu.commit.COM:count 6403 # Number of instructions committed +system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2030 # Number of memory references committed +system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions +system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit -system.cpu.committedInsts 6297 # Number of Instructions Simulated -system.cpu.committedInsts_total 6297 # Number of Instructions Simulated -system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedInsts_total 6386 # Number of Instructions Simulated +system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses -system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses +system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2058 # number of overall hits -system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses -system.cpu.dcache.overall_misses 542 # number of overall misses -system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2104 # number of overall hits +system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses +system.cpu.dcache.overall_misses 554 # number of overall misses +system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,103 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use -system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use +system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2892 # DTB accesses +system.cpu.dtb.accesses 2951 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2831 # DTB hits +system.cpu.dtb.hits 2890 # DTB hits system.cpu.dtb.misses 61 # DTB misses -system.cpu.dtb.read_accesses 1821 # DTB read accesses +system.cpu.dtb.read_accesses 1876 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1785 # DTB read hits +system.cpu.dtb.read_hits 1840 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1071 # DTB write accesses +system.cpu.dtb.write_accesses 1075 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1046 # DTB write hits +system.cpu.dtb.write_hits 1050 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched -system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle +system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 12970 +system.cpu.fetch.rateDist.samples 13314 system.cpu.fetch.rateDist.min_value 0 - 0 10663 8221.28% - 1 241 185.81% - 2 214 165.00% - 3 169 130.30% - 4 208 160.37% - 5 163 125.67% - 6 215 165.77% - 7 128 98.69% - 8 969 747.11% + 0 10844 8144.81% + 1 252 189.27% + 2 238 178.76% + 3 230 172.75% + 4 272 204.30% + 5 162 121.68% + 6 232 174.25% + 7 129 96.89% + 8 955 717.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency -system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses -system.cpu.icache.demand_misses 426 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses +system.cpu.icache.demand_misses 424 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1278 # number of overall hits -system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses -system.cpu.icache.overall_misses 426 # number of overall misses -system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses +system.cpu.icache.overall_hits 1378 # number of overall hits +system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses +system.cpu.icache.overall_misses 424 # number of overall misses +system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,42 +228,42 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use -system.cpu.icache.total_refs 1278 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use +system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1375 # Number of branches executed -system.cpu.iew.EXEC:nop 76 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate -system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1073 # Number of stores executed +system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1450 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate +system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1077 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5878 # num instructions consuming a value -system.cpu.iew.WB:count 8512 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back +system.cpu.iew.WB:consumers 6020 # num instructions consuming a value +system.cpu.iew.WB:count 8734 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4396 # num instructions producing a value -system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle -system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4491 # num instructions producing a value +system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle +system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores @@ -272,17 +272,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued +system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6072 66.72% # Type of FU issued + IntAlu 6254 66.92% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1928 21.18% # Type of FU issued - MemWrite 1096 12.04% # Type of FU issued + MemRead 1986 21.25% # Type of FU issued + MemWrite 1100 11.77% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2 2.15% # attempts to use FU when none available + IntAlu 14 13.33% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 56 60.22% # attempts to use FU when none available - MemWrite 35 37.63% # attempts to use FU when none available + MemRead 56 53.33% # attempts to use FU when none available + MemWrite 35 33.33% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 12970 +system.cpu.iq.ISSUE:issued_per_cycle.samples 13314 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 8890 6854.28% - 1 1667 1285.27% - 2 1037 799.54% - 3 696 536.62% - 4 340 262.14% - 5 189 145.72% - 6 103 79.41% - 7 35 26.99% - 8 13 10.02% + 0 9113 6844.67% + 1 1716 1288.87% + 2 1071 804.42% + 3 725 544.54% + 4 355 266.64% + 5 172 129.19% + 6 115 86.38% + 7 34 25.54% + 8 13 9.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate -system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1737 # ITB accesses +system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate +system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1838 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1704 # ITB hits -system.cpu.itb.misses 33 # ITB misses +system.cpu.itb.hits 1802 # ITB hits +system.cpu.itb.misses 36 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 479 # number of overall misses +system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,30 +415,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 24784 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing +system.cpu.numCycles 24950 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 2fe8c587c..b502697af 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:15 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12391500 because target called exit() +Exiting @ tick 12474500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 15e8bed82..712fc898c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 598748 # Simulator instruction rate (inst/s) -host_mem_usage 190820 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 294136747 # Simulator tick rate (ticks/s) +host_inst_rate 6758 # Simulator instruction rate (inst/s) +host_mem_usage 190848 # Number of bytes of host memory used +host_seconds 0.95 # Real time elapsed on the host +host_tick_rate 3391912 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6315 # Number of instructions simulated +sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 3170500 # Number of ticks simulated -system.cpu.dtb.accesses 2040 # DTB accesses +sim_ticks 3215000 # Number of ticks simulated +system.cpu.dtb.accesses 2060 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2030 # DTB hits +system.cpu.dtb.hits 2050 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 1175 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1168 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 865 # DTB write accesses +system.cpu.dtb.write_accesses 868 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 862 # DTB write hits +system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 6342 # ITB accesses +system.cpu.itb.accesses 6431 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 6325 # ITB hits +system.cpu.itb.hits 6414 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 6342 # number of cpu cycles simulated -system.cpu.num_insts 6315 # Number of instructions executed -system.cpu.num_refs 2040 # Number of memory references +system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index b3d91abb5..9a255c446 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:40:14 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 3170500 because target called exit() +Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index a3039b303..f97f1c530 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 472326 # Simulator instruction rate (inst/s) -host_mem_usage 198180 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2462369543 # Simulator tick rate (ticks/s) +host_inst_rate 68165 # Simulator instruction rate (inst/s) +host_mem_usage 198212 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 358563073 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6315 # Number of instructions simulated +sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33503000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) +sim_ticks 33777000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.303030 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses -system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses +system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1851 # number of overall hits -system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses -system.cpu.dcache.overall_misses 179 # number of overall misses +system.cpu.dcache.overall_hits 1868 # number of overall hits +system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses +system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,67 +74,67 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use -system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 2040 # DTB accesses +system.cpu.dtb.accesses 2060 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2030 # DTB hits +system.cpu.dtb.hits 2050 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 1175 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1168 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 865 # DTB write accesses +system.cpu.dtb.write_accesses 868 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 862 # DTB write hits +system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 21.673835 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits +system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6047 # number of overall hits +system.cpu.icache.overall_hits 6136 # number of overall hits system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -150,14 +150,14 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use -system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 6343 # ITB accesses +system.cpu.itb.accesses 6432 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 6326 # ITB hits +system.cpu.itb.hits 6415 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 73 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -189,38 +189,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002809 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 443 # number of overall misses +system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 446 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -233,16 +233,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67006 # number of cpu cycles simulated -system.cpu.num_insts 6315 # Number of instructions executed -system.cpu.num_refs 2040 # Number of memory references +system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index c97b9deb2..c3d847e3f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:17 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33503000 because target called exit() +Exiting @ tick 33777000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index c3f97c1a9..12af7d1b2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 209 # Nu global.BPredUnit.condPredicted 447 # Number of conditional branches predicted global.BPredUnit.lookups 859 # Number of BP lookups global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 5854 # Simulator instruction rate (inst/s) -host_mem_usage 197984 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 17609622 # Simulator tick rate (ticks/s) +host_inst_rate 31288 # Simulator instruction rate (inst/s) +host_mem_usage 198012 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 93885607 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 55e76881d..e4872d461 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:32:55 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:52 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 9ae501100..051f6dec4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229372 # Simulator instruction rate (inst/s) -host_mem_usage 189868 # Number of bytes of host memory used +host_inst_rate 334328 # Simulator instruction rate (inst/s) +host_mem_usage 189900 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 113875724 # Simulator tick rate (ticks/s) +host_tick_rate 162370166 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index b6b984d4a..55a4a98f7 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 5e0dacddf..af7d3609f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 251832 # Simulator instruction rate (inst/s) -host_mem_usage 197320 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 1657349995 # Simulator tick rate (ticks/s) +host_inst_rate 59950 # Simulator instruction rate (inst/s) +host_mem_usage 197352 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 402241104 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 5af4e5b77..779993228 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:17 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 02399594b..ecc7ae363 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 854 # Number of BTB hits -global.BPredUnit.BTBLookups 4386 # Number of BTB lookups -global.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1443 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2855 # Number of conditional branches predicted -global.BPredUnit.lookups 5041 # Number of BP lookups -global.BPredUnit.usedRAS 646 # Number of times the RAS was used to get a target. -host_inst_rate 76947 # Simulator instruction rate (inst/s) -host_mem_usage 199748 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 85614119 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 42 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 9 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 25 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2333 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1249 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 916 # Number of BTB hits +global.BPredUnit.BTBLookups 4733 # Number of BTB lookups +global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted +global.BPredUnit.lookups 5548 # Number of BP lookups +global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. +host_inst_rate 85524 # Simulator instruction rate (inst/s) +host_mem_usage 199540 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 95322021 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 12595 # Number of instructions simulated +sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14029500 # Number of ticks simulated -system.cpu.commit.COM:branches 2024 # Number of branches committed -system.cpu.commit.COM:branches_0 1012 # Number of branches committed -system.cpu.commit.COM:branches_1 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 158 # number cycles where commit BW limit reached +sim_ticks 14251500 # Number of ticks simulated +system.cpu.commit.COM:branches 2102 # Number of branches committed +system.cpu.commit.COM:branches_0 1051 # Number of branches committed +system.cpu.commit.COM:branches_1 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 21929 +system.cpu.commit.COM:committed_per_cycle.samples 22837 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16145 7362.40% - 1 3000 1368.05% - 2 1194 544.48% - 3 576 262.67% - 4 357 162.80% - 5 253 115.37% - 6 166 75.70% - 7 80 36.48% - 8 158 72.05% + 0 16880 7391.51% + 1 3016 1320.66% + 2 1386 606.91% + 3 576 252.22% + 4 326 142.75% + 5 268 117.35% + 6 170 74.44% + 7 93 40.72% + 8 122 53.42% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 12629 # Number of instructions committed -system.cpu.commit.COM:count_0 6314 # Number of instructions committed -system.cpu.commit.COM:count_1 6315 # Number of instructions committed -system.cpu.commit.COM:loads 2336 # Number of loads committed -system.cpu.commit.COM:loads_0 1168 # Number of loads committed -system.cpu.commit.COM:loads_1 1168 # Number of loads committed +system.cpu.commit.COM:count 12807 # Number of instructions committed +system.cpu.commit.COM:count_0 6403 # Number of instructions committed +system.cpu.commit.COM:count_1 6404 # Number of instructions committed +system.cpu.commit.COM:loads 2370 # Number of loads committed +system.cpu.commit.COM:loads_0 1185 # Number of loads committed +system.cpu.commit.COM:loads_1 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 4060 # Number of memory references committed -system.cpu.commit.COM:refs_0 2030 # Number of memory references committed -system.cpu.commit.COM:refs_1 2030 # Number of memory references committed +system.cpu.commit.COM:refs 4100 # Number of memory references committed +system.cpu.commit.COM:refs_0 2050 # Number of memory references committed +system.cpu.commit.COM:refs_1 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1061 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions +system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9861 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6297 # Number of Instructions Simulated -system.cpu.committedInsts_1 6298 # Number of Instructions Simulated -system.cpu.committedInsts_total 12595 # Number of Instructions Simulated -system.cpu.cpi_0 4.456090 # CPI: Cycles Per Instruction -system.cpu.cpi_1 4.455383 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.227868 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 35521.212121 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36972.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3416 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3416 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11722000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 11722000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.088094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 330 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 132 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7320500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 7320500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052856 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 33638.157895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 35974.137931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 964 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 964 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25565000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 25565000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.440835 # miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6386 # Number of Instructions Simulated +system.cpu.committedInsts_1 6387 # Number of Instructions Simulated +system.cpu.committedInsts_total 12773 # Number of Instructions Simulated +system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction +system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 6259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.915698 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5470 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5470 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 34208.256881 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 37287000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 37287000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.199269 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1090 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 718 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 718 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 13580000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.068007 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 372 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5470 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5470 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 34208.256881 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4380 # number of overall hits -system.cpu.dcache.overall_hits_0 4380 # number of overall hits +system.cpu.dcache.overall_hits 4550 # number of overall hits +system.cpu.dcache.overall_hits_0 4550 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 37287000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 37287000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.199269 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1090 # number of overall misses -system.cpu.dcache.overall_misses_0 1090 # number of overall misses +system.cpu.dcache.overall_misses 1105 # number of overall misses +system.cpu.dcache.overall_misses_0 1105 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 718 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 718 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13580000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 13580000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.068007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 218.241072 # Cycle average of tags in use -system.cpu.dcache.total_refs 4443 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use +system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5036 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 400 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 534 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 25996 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32008 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4597 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1938 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 173 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 6094 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 6300 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5949 # DTB hits +system.cpu.dtb.hits 6155 # DTB hits system.cpu.dtb.misses 145 # DTB misses -system.cpu.dtb.read_accesses 3938 # DTB read accesses +system.cpu.dtb.read_accesses 4144 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3853 # DTB read hits -system.cpu.dtb.read_misses 85 # DTB read misses +system.cpu.dtb.read_hits 4056 # DTB read hits +system.cpu.dtb.read_misses 88 # DTB read misses system.cpu.dtb.write_accesses 2156 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2096 # DTB write hits -system.cpu.dtb.write_misses 60 # DTB write misses -system.cpu.fetch.Branches 5041 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3820 # Number of cache lines fetched -system.cpu.fetch.Cycles 8809 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 28977 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1559 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.179651 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1500 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.032680 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 2099 # DTB write hits +system.cpu.dtb.write_misses 57 # DTB write misses +system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched +system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 21971 +system.cpu.fetch.rateDist.samples 22904 system.cpu.fetch.rateDist.min_value 0 - 0 17033 7752.49% - 1 423 192.53% - 2 326 148.38% - 3 380 172.96% - 4 411 187.06% - 5 313 142.46% - 6 429 195.26% - 7 269 122.43% - 8 2387 1086.43% + 0 17622 7693.85% + 1 416 181.63% + 2 353 154.12% + 3 477 208.26% + 4 425 185.56% + 5 349 152.38% + 6 442 192.98% + 7 261 113.95% + 8 2559 1117.27% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 35987.893462 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35566.129032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2994 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2994 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 29726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.216230 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 826 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 826 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 206 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 206 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 22051000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 22051000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.162304 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.829032 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3820 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3820 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 35987.893462 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2994 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2994 # number of demand (read+write) hits +system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 29726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.216230 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 826 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 826 # number of demand (read+write) misses +system.cpu.icache.demand_misses 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 206 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 206 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 22051000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 22051000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.162304 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3820 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3820 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 35987.893462 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2994 # number of overall hits -system.cpu.icache.overall_hits_0 2994 # number of overall hits +system.cpu.icache.overall_hits 3272 # number of overall hits +system.cpu.icache.overall_hits_0 3272 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 29726000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 29726000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.216230 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 826 # number of overall misses -system.cpu.icache.overall_misses_0 826 # number of overall misses +system.cpu.icache.overall_misses 841 # number of overall misses +system.cpu.icache.overall_misses_0 841 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 206 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 206 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 22051000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 22051000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.162304 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +381,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6 # number of replacements system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 322.256979 # Cycle average of tags in use -system.cpu.icache.total_refs 2994 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use +system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2958 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1488 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1470 # Number of branches executed -system.cpu.iew.EXEC:nop 133 # number of nop insts executed +system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3160 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed +system.cpu.iew.EXEC:nop 135 # number of nop insts executed system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 63 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.660299 # Inst execution rate -system.cpu.iew.EXEC:refs 6116 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 3062 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3054 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2176 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1102 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1074 # Number of stores executed +system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate +system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2175 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11542 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5820 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5722 # num instructions consuming a value -system.cpu.iew.WB:count 17828 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8981 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8847 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.545155 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.771649 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.773506 # average fanout of values written-back +system.cpu.iew.WB:consumers 11901 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value +system.cpu.iew.WB:count 18426 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8917 # num instructions producing a value -system.cpu.iew.WB:producers_0 4491 # num instructions producing a value -system.cpu.iew.WB:producers_1 4426 # num instructions producing a value -system.cpu.iew.WB:rate 0.635353 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.320064 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.315289 # insts written-back per cycle -system.cpu.iew.WB:sent 18058 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 9082 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 8976 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1215 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1067 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4660 # Number of dispatched load instructions +system.cpu.iew.WB:producers 9240 # num instructions producing a value +system.cpu.iew.WB:producers_0 4646 # num instructions producing a value +system.cpu.iew.WB:producers_1 4594 # num instructions producing a value +system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle +system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 801 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2511 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 22574 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3940 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1960 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1980 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1001 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18528 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1938 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1159 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1165 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 387 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 127 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 964 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 251 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.224412 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.224448 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.448860 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9816 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6598 67.22% # Type of FU issued + IntAlu 6830 67.10% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2077 21.16% # Type of FU issued - MemWrite 1136 11.57% # Type of FU issued + MemRead 2173 21.35% # Type of FU issued + MemWrite 1171 11.50% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 9713 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6508 67.00% # Type of FU issued + IntAlu 6842 67.01% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2085 21.47% # Type of FU issued - MemWrite 1115 11.48% # Type of FU issued + MemRead 2230 21.84% # Type of FU issued + MemWrite 1134 11.11% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 19529 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 13106 67.11% # Type of FU issued + IntAlu 13672 67.05% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4162 21.31% # Type of FU issued - MemWrite 2251 11.53% # Type of FU issued + MemRead 4403 21.59% # Type of FU issued + MemWrite 2305 11.30% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 165 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 86 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 79 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004404 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004045 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5 3.03% # attempts to use FU when none available + IntAlu 13 7.56% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,136 +543,136 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 94 56.97% # attempts to use FU when none available - MemWrite 66 40.00% # attempts to use FU when none available + MemRead 96 55.81% # attempts to use FU when none available + MemWrite 63 36.63% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 21971 +system.cpu.iq.ISSUE:issued_per_cycle.samples 22904 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 13541 6163.12% - 1 3190 1451.91% - 2 2253 1025.44% - 3 1351 614.90% - 4 834 379.59% - 5 490 223.02% - 6 205 93.30% - 7 92 41.87% - 8 15 6.83% + 0 14156 6180.58% + 1 3289 1435.99% + 2 2351 1026.46% + 3 1373 599.46% + 4 854 372.86% + 5 535 233.58% + 6 261 113.95% + 7 57 24.89% + 8 28 12.22% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.695973 # Inst issue rate -system.cpu.iq.iqInstsAdded 22397 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19529 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate +system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8499 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4789 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3871 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 4162 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3820 # ITB hits -system.cpu.itb.misses 51 # ITB misses +system.cpu.itb.hits 4113 # ITB hits +system.cpu.itb.misses 49 # ITB misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34517.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31445.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5039500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 5039500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4591000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4591000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 34572.916667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31431.372549 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 28211500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 28211500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 816 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 816 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 25648000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25648000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 816 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 816 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34410.714286 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31232.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 963500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 963500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 874500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 874500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002538 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 964 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 964 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 34564.449064 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33251000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 33251000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 30239000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 30239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 964 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 964 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 34564.449064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency @@ -680,26 +680,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_hits_0 2 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33251000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 33251000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 962 # number of overall misses -system.cpu.l2cache.overall_misses_0 962 # number of overall misses +system.cpu.l2cache.overall_misses 969 # number of overall misses +system.cpu.l2cache.overall_misses_0 969 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 30239000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 30239000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -719,34 +719,34 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 788 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 431.449507 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 28060 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2889 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 32446 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1291 # Number of times rename has blocked due to LSQ full +system.cpu.numCycles 28504 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 31166 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 24765 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 18538 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4270 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1938 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1355 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9464 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 854 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3364 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 254 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 10049ad35..958798ce3 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:30:32 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:54 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! Hello world! -Exiting @ tick 14029500 because target called exit() +Exiting @ tick 14251500 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index adb5935db..1e6af66f7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4457341 # Simulator instruction rate (inst/s) -host_mem_usage 291000 # Number of bytes of host memory used -host_seconds 14.16 # Real time elapsed on the host -host_tick_rate 132088621816 # Simulator tick rate (ticks/s) +host_inst_rate 3333474 # Simulator instruction rate (inst/s) +host_mem_usage 290708 # Number of bytes of host memory used +host_seconds 18.93 # Real time elapsed on the host +host_tick_rate 98784311223 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63113507 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 4c93eabec..a9bd0ea3f 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:32:52 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:23 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index bd2b86aca..8c53afda6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2960159 # Simulator instruction rate (inst/s) -host_mem_usage 289760 # Number of bytes of host memory used -host_seconds 20.27 # Real time elapsed on the host -host_tick_rate 90209540739 # Simulator tick rate (ticks/s) +host_inst_rate 2786128 # Simulator instruction rate (inst/s) +host_mem_usage 289464 # Number of bytes of host memory used +host_seconds 21.53 # Real time elapsed on the host +host_tick_rate 84905818409 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59995351 # Number of instructions simulated sim_seconds 1.828356 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index e7d4d476c..6989105c7 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:28:06 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:01 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 67988d1e0..39aa94315 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1529547 # Simulator instruction rate (inst/s) -host_mem_usage 287776 # Number of bytes of host memory used -host_seconds 38.82 # Real time elapsed on the host -host_tick_rate 50799321587 # Simulator tick rate (ticks/s) +host_inst_rate 1388930 # Simulator instruction rate (inst/s) +host_mem_usage 287800 # Number of bytes of host memory used +host_seconds 42.75 # Real time elapsed on the host +host_tick_rate 46129218174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59379829 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 447da7e4d..06723d964 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:29:36 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:38:12 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 5185f8b73..bcad4cd62 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1640475 # Simulator instruction rate (inst/s) -host_mem_usage 286536 # Number of bytes of host memory used -host_seconds 34.24 # Real time elapsed on the host -host_tick_rate 56375976626 # Simulator tick rate (ticks/s) +host_inst_rate 1283720 # Simulator instruction rate (inst/s) +host_mem_usage 286560 # Number of bytes of host memory used +host_seconds 43.75 # Real time elapsed on the host +host_tick_rate 44115985890 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56165112 # Number of instructions simulated sim_seconds 1.930166 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 5cef637b5..b4ba00cf0 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:27:38 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:43 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index b55acc4e4..51d5de7dc 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3131465 # Simulator instruction rate (inst/s) -host_mem_usage 189960 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 1563505663 # Simulator tick rate (ticks/s) +host_inst_rate 4911987 # Simulator instruction rate (inst/s) +host_mem_usage 189996 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 2448419888 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 1f91d28a0..539afef68 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:34 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index c3508e466..041421492 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1653831 # Simulator instruction rate (inst/s) -host_mem_usage 197344 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 2436827913 # Simulator tick rate (ticks/s) +host_inst_rate 883179 # Simulator instruction rate (inst/s) +host_mem_usage 197372 # Number of bytes of host memory used +host_seconds 0.57 # Real time elapsed on the host +host_tick_rate 1301859777 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 04f8b3fb2..337a3a052 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:51 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt index 5a19ce746..12655b8fd 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt @@ -1,8 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1660926 # Simulator instruction rate (inst/s) -host_seconds 1.20 # Real time elapsed on the host -host_tick_rate 207598549 # Simulator tick rate (ticks/s) +host_inst_rate 2958551 # Simulator instruction rate (inst/s) +host_mem_usage 1121980 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 369689554 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr old mode 100644 new mode 100755 index e0d5d4d73..496a7244f --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr @@ -1,7 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout old mode 100644 new mode 100755 index b79194a00..b1dd747a5 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 17:12:56 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 17:19:26 -M5 executing on dhcp128036150089.central.yale.edu -command line: build/ALPHA_SE/m5.fast -d simple-atomic wrapper.py +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt index d00f39e87..5dc3a25b6 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt @@ -1,8 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 803390 # Simulator instruction rate (inst/s) -host_seconds 2.49 # Real time elapsed on the host -host_tick_rate 296594923 # Simulator tick rate (ticks/s) +host_inst_rate 1370296 # Simulator instruction rate (inst/s) +host_mem_usage 204468 # Number of bytes of host memory used +host_seconds 1.46 # Real time elapsed on the host +host_tick_rate 505820394 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr old mode 100644 new mode 100755 index e0d5d4d73..496a7244f --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr @@ -1,7 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Sockets disabled, not accepting gdb connections warn: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout old mode 100644 new mode 100755 index 2976be712..edbace7b2 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 17:12:56 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 17:26:45 -M5 executing on dhcp128036150089.central.yale.edu -command line: build/ALPHA_SE/m5.fast -d output wrapper.py +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:30:50 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 765a44d97..07a437af0 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 324448 # Number of bytes of host memory used -host_seconds 222.79 # Real time elapsed on the host -host_tick_rate 1207024 # Simulator tick rate (ticks/s) +host_mem_usage 324480 # Number of bytes of host memory used +host_seconds 257.27 # Real time elapsed on the host +host_tick_rate 1045249 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 048969ee8..a9b5dbd1a 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:01:52 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index c935ec207..3e554a663 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/hsul/work/m5/m5/configs/boot/netperf-server.rcS +readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -703,7 +703,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/hsul/work/m5/m5/configs/boot/netperf-stream-client.rcS +readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 11d12fd63..3a06809c5 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 161007148 # Simulator instruction rate (inst/s) -host_mem_usage 478492 # Number of bytes of host memory used -host_seconds 1.70 # Real time elapsed on the host -host_tick_rate 117815722486 # Simulator tick rate (ticks/s) +host_inst_rate 200792296 # Simulator instruction rate (inst/s) +host_mem_usage 476644 # Number of bytes of host memory used +host_seconds 1.36 # Real time elapsed on the host +host_tick_rate 146922204609 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294177 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 142489143379 # Simulator instruction rate (inst/s) -host_mem_usage 478492 # Number of bytes of host memory used +host_inst_rate 214516622449 # Simulator instruction rate (inst/s) +host_mem_usage 476644 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 385850761 # Simulator tick rate (ticks/s) +host_tick_rate 582637509 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294177 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 487c48aa8..b7a61e7b4 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:28:13 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:38:27 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -- cgit v1.2.3 From 19273164da50011d59b7f362026f8e80260807d4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 8 Dec 2008 07:16:40 -0800 Subject: output: Change default output directory and files and update tests. --HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => 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tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt --- tests/SConscript | 20 +- .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 449 ----- .../long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 2 + .../long/00.gzip/ref/alpha/tru64/o3-timing/simout | 46 + .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 449 +++++ .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 - .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 46 - 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tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr create mode 100755 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout create mode 100644 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt delete mode 100755 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr delete mode 100755 tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 3e0eed941..016b3a26a 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -58,7 +58,7 @@ def check_test(target, source, env): if os.path.exists(t.abspath): Execute(Delete(t.abspath)) # Run diff on output & ref directories to find differences. - # Exclude m5stats.txt since we will use diff-out on that. + # Exclude the stats file since we will use diff-out on that. Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + '-I "^command line:" ' + # for stdout file '-I "^M5 compiled " ' + # for stderr file @@ -67,12 +67,12 @@ def check_test(target, source, env): '-I "^Simulation complete at" ' + # for stderr file '-I "^Listening for" ' + # for stderr file '-I "listening for remote gdb" ' + # for stderr file - '--exclude=m5stats.txt --exclude=SCCS ' + + '--exclude=stats.txt --exclude=SCCS ' + '--exclude=${TARGETS[0].file} ' + '> ${TARGETS[0]}', target=target, source=source), None) print "===== Output differences =====" print contents(target[0]) - # Run diff-out on m5stats.txt file + # Run diff-out on stats.txt file status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}', target=target, source=source), strfunction=None) @@ -111,14 +111,14 @@ Note: The following file(s) will not be copied. New non-standard inputs and are ignored. ''' # - reference files always needed -needed_files = set(['stdout', 'stderr', 'm5stats.txt', 'config.ini']) +needed_files = set(['simout', 'simerr', 'stats.txt', 'config.ini']) # - source files we always want to ignore known_ignores = set(['status', 'outdiff', 'statsdiff']) def update_test(target, source, env): """Update reference test outputs. - Target is phony. First two sources are the ref & new m5stats.txt + Target is phony. First two sources are the ref & new stats.txt file files, respectively. We actually copy everything in the respective directories except the status & diff output files. @@ -170,17 +170,15 @@ def test_builder(env, ref_dir): def tgt(f): return os.path.join(tgt_dir, f) - ref_stats = os.path.join(ref_dir, 'm5stats.txt') - new_stats = tgt('m5stats.txt') + ref_stats = os.path.join(ref_dir, 'stats.txt') + new_stats = tgt('stats.txt') status_file = tgt('status') # Base command for running test. We mess around with indirectly # referring to files via SOURCES and TARGETS so that scons can # mess with paths all it wants to and we still get the right # files. - cmd = '${SOURCES[0]} -d $TARGET.dir' - cmd += ' -re --stdout-file stdout --stderr-file stderr' - cmd += ' ${SOURCES[1]} %s' % tgt_dir + cmd = '${SOURCES[0]} -d $TARGET.dir -re ${SOURCES[1]} %s' % tgt_dir # Prefix test run with batch job submission command if appropriate. # Batch command also supports timeout arg (in seconds, not minutes). @@ -188,7 +186,7 @@ def test_builder(env, ref_dir): if env['BATCH']: cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) - env.Command([tgt('stdout'), tgt('stderr'), new_stats], + env.Command([tgt('simout'), tgt('simerr'), new_stats], [env.M5Binary, 'run.py'], cmd) # order of targets is important... see check_test diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 4e08b47b3..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718859 # Number of BTB hits -global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -global.BPredUnit.lookups 76039018 # Number of BP lookups -global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 193677 # Simulator instruction rate (inst/s) -host_mem_usage 202220 # Number of bytes of host memory used -host_seconds 2920.07 # Real time elapsed on the host -host_tick_rate 57217081 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078146500 # Number of ticks simulated -system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711249 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088757 3349.40% - 1 100475751 3113.49% - 2 37367184 1157.91% - 3 9733028 301.60% - 4 10676883 330.85% - 5 22147835 686.31% - 6 13251874 410.64% - 7 3269687 101.32% - 8 17700250 548.49% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:loads 115049510 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 154862033 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit -system.cpu.committedInsts 565552443 # Number of Instructions Simulated -system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415339 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182768 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468828 # number of replacements -system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163077390 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163013880 # DTB hits -system.cpu.dtb.misses 63510 # DTB misses -system.cpu.dtb.read_accesses 122284109 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260496 # DTB read hits -system.cpu.dtb.read_misses 23613 # DTB read misses -system.cpu.dtb.write_accesses 40793281 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40753384 # DTB write hits -system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581112 -system.cpu.fetch.rateDist.min_value 0 - 0 201466223 6057.66% - 1 10360747 311.53% - 2 15882081 477.54% - 3 14599006 438.96% - 4 12362950 371.73% - 5 14822134 445.67% - 6 6008311 180.66% - 7 3307530 99.45% - 8 53772130 1616.81% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013237 # number of overall hits -system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1169 # number of overall misses -system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use -system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316859 # Number of branches executed -system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41189464 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value -system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375802 # num instructions producing a value -system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle -system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834840 72.45% # Type of FU issued - IntMult 6546 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 29 0.00% # Type of FU issued - FloatCmp 5 0.00% # Type of FU issued - FloatCvt 5 0.00% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855453 20.61% # Type of FU issued - MemWrite 42021230 6.94% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390831 74.54% # attempts to use FU when none available - IntMult 67 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 1490139 20.60% # attempts to use FU when none available - MemWrite 351286 4.86% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92203773 2772.37% - 1 67051353 2016.09% - 2 80133780 2409.45% - 3 36043478 1083.75% - 4 30084945 904.59% - 5 14579095 438.36% - 6 10850493 326.25% - 7 1143008 34.37% - 8 491187 14.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66014446 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66014406 # ITB hits -system.cpu.itb.misses 40 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292443 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 85262 # number of replacements -system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.numCycles 334156294 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..4ea4c0572 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:25:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..4e08b47b3 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 65718859 # Number of BTB hits +global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups +global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +global.BPredUnit.lookups 76039018 # Number of BP lookups +global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. +host_inst_rate 193677 # Simulator instruction rate (inst/s) +host_mem_usage 202220 # Number of bytes of host memory used +host_seconds 2920.07 # Real time elapsed on the host +host_tick_rate 57217081 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 565552443 # Number of instructions simulated +sim_seconds 0.167078 # Number of seconds simulated +sim_ticks 167078146500 # Number of ticks simulated +system.cpu.commit.COM:branches 62547159 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 322711249 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 108088757 3349.40% + 1 100475751 3113.49% + 2 37367184 1157.91% + 3 9733028 301.60% + 4 10676883 330.85% + 5 22147835 686.31% + 6 13251874 410.64% + 7 3269687 101.32% + 8 17700250 548.49% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:loads 115049510 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 154862033 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit +system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated +system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 149415339 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3182768 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 468828 # number of replacements +system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334123 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 163077390 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 163013880 # DTB hits +system.cpu.dtb.misses 63510 # DTB misses +system.cpu.dtb.read_accesses 122284109 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 122260496 # DTB read hits +system.cpu.dtb.read_misses 23613 # DTB read misses +system.cpu.dtb.write_accesses 40793281 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 40753384 # DTB write hits +system.cpu.dtb.write_misses 39897 # DTB write misses +system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 332581112 +system.cpu.fetch.rateDist.min_value 0 + 0 201466223 6057.66% + 1 10360747 311.53% + 2 15882081 477.54% + 3 14599006 438.96% + 4 12362950 371.73% + 5 14822134 445.67% + 6 6008311 180.66% + 7 3307530 99.45% + 8 53772130 1616.81% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 66013237 # number of overall hits +system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 1169 # number of overall misses +system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use +system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316859 # Number of branches executed +system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate +system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41189464 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value +system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 395375802 # num instructions producing a value +system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle +system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 438834840 72.45% # Type of FU issued + IntMult 6546 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 29 0.00% # Type of FU issued + FloatCmp 5 0.00% # Type of FU issued + FloatCvt 5 0.00% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 124855453 20.61% # Type of FU issued + MemWrite 42021230 6.94% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 5390831 74.54% # attempts to use FU when none available + IntMult 67 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 1490139 20.60% # attempts to use FU when none available + MemWrite 351286 4.86% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 92203773 2772.37% + 1 67051353 2016.09% + 2 80133780 2409.45% + 3 36043478 1083.75% + 4 30084945 904.59% + 5 14579095 438.36% + 6 10850493 326.25% + 7 1143008 34.37% + 8 491187 14.77% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate +system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014446 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 66014406 # ITB hits +system.cpu.itb.misses 40 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 181383 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292443 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 85262 # number of replacements +system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use +system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 63236 # number of writebacks +system.cpu.numCycles 334156294 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 4ea4c0572..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:25:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 96bd5579b..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3417919 # Simulator instruction rate (inst/s) -host_mem_usage 193752 # Number of bytes of host memory used -host_seconds 176.09 # Real time elapsed on the host -host_tick_rate 1708971531 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.300931 # Number of seconds simulated -sim_ticks 300930958000 # Number of ticks simulated -system.cpu.dtb.accesses 153970296 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 153965363 # DTB hits -system.cpu.dtb.misses 4933 # DTB misses -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 601861917 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 601861897 # ITB hits -system.cpu.itb.misses 20 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 601861917 # number of cpu cycles simulated -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..4f98f10a9 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:47 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..96bd5579b --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3417919 # Simulator instruction rate (inst/s) +host_mem_usage 193752 # Number of bytes of host memory used +host_seconds 176.09 # Real time elapsed on the host +host_tick_rate 1708971531 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.300931 # Number of seconds simulated +sim_ticks 300930958000 # Number of ticks simulated +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861917 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861897 # ITB hits +system.cpu.itb.misses 20 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 4f98f10a9..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:47 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 5fbfd3d3d..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1797646 # Simulator instruction rate (inst/s) -host_mem_usage 201208 # Number of bytes of host memory used -host_seconds 334.80 # Real time elapsed on the host -host_tick_rate 2323765799 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.778004 # Number of seconds simulated -sim_ticks 778003833000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses -system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses -system.cpu.dcache.overall_misses 530123 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use -system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325723 # number of writebacks -system.cpu.dtb.accesses 153970296 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 153965363 # DTB hits -system.cpu.dtb.misses 4933 # DTB misses -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use -system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 601861918 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 601861898 # ITB hits -system.cpu.itb.misses 20 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 288954 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84513 # number of replacements -system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63194 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1556007666 # number of cpu cycles simulated -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..912067c8f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..5fbfd3d3d --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1797646 # Simulator instruction rate (inst/s) +host_mem_usage 201208 # Number of bytes of host memory used +host_seconds 334.80 # Real time elapsed on the host +host_tick_rate 2323765799 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.778004 # Number of seconds simulated +sim_ticks 778003833000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses +system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 153435240 # number of overall hits +system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses +system.cpu.dcache.overall_misses 530123 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use +system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 795 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 601861103 # number of overall hits +system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 795 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use +system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861918 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861898 # ITB hits +system.cpu.itb.misses 20 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 167236 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 288954 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 84513 # number of replacements +system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 63194 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1556007666 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 912067c8f..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt deleted file mode 100644 index b1499e0a2..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,439 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 182414509 # Number of BTB hits -global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted -global.BPredUnit.lookups 254458067 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116972 # Simulator instruction rate (inst/s) -host_mem_usage 204276 # Number of bytes of host memory used -host_seconds 12016.73 # Real time elapsed on the host -host_tick_rate 91760367 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618365 # Number of instructions simulated -sim_seconds 1.102659 # Number of seconds simulated -sim_ticks 1102659164000 # Number of ticks simulated -system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1964055138 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1088074348 5539.94% - 1 575643775 2930.89% - 2 120435536 613.20% - 3 120975808 615.95% - 4 27955061 142.33% - 5 8084154 41.16% - 6 10447088 53.19% - 7 4343249 22.11% - 8 8096119 41.22% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 1489537508 # Number of instructions committed -system.cpu.commit.COM:loads 402517243 # Number of loads committed -system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375199 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618365 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated -system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency -system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 589980362 # number of overall hits -system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3138202 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 523278 # number of replacements -system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use -system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 348745 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched -system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2203815119 -system.cpu.fetch.rateDist.min_value 0 - 0 1359103013 6167.05% - 1 256500552 1163.89% - 2 81150170 368.23% - 3 38425919 174.36% - 4 85384466 387.44% - 5 41200028 186.95% - 6 32567288 147.78% - 7 20688755 93.88% - 8 288794928 1310.43% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354586500 # number of overall hits -system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2127 # number of overall misses -system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 222 # number of replacements -system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use -system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 128154505 # Number of branches executed -system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate -system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207432555 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value -system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1435567316 # num instructions producing a value -system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle -system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186637130 59.65% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2990817 0.15% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 571681967 28.74% # Type of FU issued - MemWrite 227997762 11.46% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 142220 3.54% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 232758 5.80% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3328923 82.92% # attempts to use FU when none available - MemWrite 310728 7.74% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1083882017 4918.21% - 1 586425796 2660.96% - 2 298714416 1355.44% - 3 164995052 748.68% - 4 47215795 214.25% - 5 14943133 67.81% - 6 6716024 30.47% - 7 790185 3.59% - 8 132701 0.60% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate -system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 214675 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 314078 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84497 # number of replacements -system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61945 # number of writebacks -system.cpu.numCycles 2205318329 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed -system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout new file mode 100755 index 000000000..cf3fc26c2 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:58 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1102659164000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt new file mode 100644 index 000000000..b1499e0a2 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -0,0 +1,439 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 182414509 # Number of BTB hits +global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups +global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted +global.BPredUnit.lookups 254458067 # Number of BP lookups +global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +host_inst_rate 116972 # Simulator instruction rate (inst/s) +host_mem_usage 204276 # Number of bytes of host memory used +host_seconds 12016.73 # Real time elapsed on the host +host_tick_rate 91760367 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1405618365 # Number of instructions simulated +sim_seconds 1.102659 # Number of seconds simulated +sim_ticks 1102659164000 # Number of ticks simulated +system.cpu.commit.COM:branches 86248929 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1964055138 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 1088074348 5539.94% + 1 575643775 2930.89% + 2 120435536 613.20% + 3 120975808 615.95% + 4 27955061 142.33% + 5 8084154 41.16% + 6 10447088 53.19% + 7 4343249 22.11% + 8 8096119 41.22% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 1489537508 # Number of instructions committed +system.cpu.commit.COM:loads 402517243 # Number of loads committed +system.cpu.commit.COM:membars 51356 # Number of memory barriers committed +system.cpu.commit.COM:refs 569375199 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618365 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated +system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 589980362 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3138202 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 523278 # number of replacements +system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use +system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 348745 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 2203815119 +system.cpu.fetch.rateDist.min_value 0 + 0 1359103013 6167.05% + 1 256500552 1163.89% + 2 81150170 368.23% + 3 38425919 174.36% + 4 85384466 387.44% + 5 41200028 186.95% + 6 32567288 147.78% + 7 20688755 93.88% + 8 288794928 1310.43% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 354586500 # number of overall hits +system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 2127 # number of overall misses +system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 222 # number of replacements +system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use +system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128154505 # Number of branches executed +system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate +system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207432555 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value +system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1435567316 # num instructions producing a value +system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle +system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 1186637130 59.65% # Type of FU issued + IntMult 0 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2990817 0.15% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 571681967 28.74% # Type of FU issued + MemWrite 227997762 11.46% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 142220 3.54% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 232758 5.80% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 3328923 82.92% # attempts to use FU when none available + MemWrite 310728 7.74% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 1083882017 4918.21% + 1 586425796 2660.96% + 2 298714416 1355.44% + 3 164995052 748.68% + 4 47215795 214.25% + 5 14943133 67.81% + 6 6716024 30.47% + 7 790185 3.59% + 8 132701 0.60% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate +system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 214675 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314078 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 84497 # number of replacements +system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.numCycles 2205318329 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed +system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout deleted file mode 100755 index cf3fc26c2..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:58 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1102659164000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 6ee039121..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2833353 # Simulator instruction rate (inst/s) -host_mem_usage 195884 # Number of bytes of host memory used -host_seconds 525.71 # Real time elapsed on the host -host_tick_rate 1416680719 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489523295 # Number of instructions simulated -sim_seconds 0.744764 # Number of seconds simulated -sim_ticks 744764119000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489528239 # number of cpu cycles simulated -system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..959e9811f --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:45:38 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..6ee039121 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2833353 # Simulator instruction rate (inst/s) +host_mem_usage 195884 # Number of bytes of host memory used +host_seconds 525.71 # Real time elapsed on the host +host_tick_rate 1416680719 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 0.744764 # Number of seconds simulated +sim_ticks 744764119000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 959e9811f..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:45:38 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 21ee70af0..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2121797 # Simulator instruction rate (inst/s) -host_mem_usage 203340 # Number of bytes of host memory used -host_seconds 702.01 # Real time elapsed on the host -host_tick_rate 2963511011 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.080416 # Number of seconds simulated -sim_ticks 2080416155000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568846579 # number of overall hits -system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513081 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316420 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489527099 # number of overall hits -system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1107 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use -system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160847 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293481 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82905 # number of replacements -system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61861 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4160832310 # number of cpu cycles simulated -system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..696328daa --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:13 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2080416155000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..21ee70af0 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2121797 # Simulator instruction rate (inst/s) +host_mem_usage 203340 # Number of bytes of host memory used +host_seconds 702.01 # Real time elapsed on the host +host_tick_rate 2963511011 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.080416 # Number of seconds simulated +sim_ticks 2080416155000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses +system.cpu.dcache.overall_misses 513081 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316420 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 1107 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use +system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 160847 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293481 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 82905 # number of replacements +system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61861 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4160832310 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 696328daa..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:13 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2080416155000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 4f9664bbc..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1613706 # Simulator instruction rate (inst/s) -host_mem_usage 195008 # Number of bytes of host memory used -host_seconds 1003.53 # Real time elapsed on the host -host_tick_rate 959566027 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 0.962952 # Number of seconds simulated -sim_ticks 962951801000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925903603 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..12f446c64 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..7b8dadcc0 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:03:28 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 962951801000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..4f9664bbc --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1613706 # Simulator instruction rate (inst/s) +host_mem_usage 195008 # Number of bytes of host memory used +host_seconds 1003.53 # Real time elapsed on the host +host_tick_rate 959566027 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 0.962952 # Number of seconds simulated +sim_ticks 962951801000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1925903603 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index 12f446c64..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,9 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 7b8dadcc0..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:03:28 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 962951801000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 76b073830..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1159099 # Simulator instruction rate (inst/s) -host_mem_usage 201888 # Number of bytes of host memory used -host_seconds 1397.12 # Real time elapsed on the host -host_tick_rate 1828142910 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 2.554133 # Number of seconds simulated -sim_ticks 2554132875000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses -system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606644555 # number of overall hits -system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses -system.cpu.dcache.overall_misses 506099 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 439707 # number of replacements -system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use -system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 721 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925902841 # number of overall hits -system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 721 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use -system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 161820 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 282704 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82097 # number of replacements -system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use -system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61702 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108265750 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..12f446c64 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..5b0e0d9ff --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:23:58 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2554132875000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..76b073830 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1159099 # Simulator instruction rate (inst/s) +host_mem_usage 201888 # Number of bytes of host memory used +host_seconds 1397.12 # Real time elapsed on the host +host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 2.554133 # Number of seconds simulated +sim_ticks 2554132875000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses +system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses +system.cpu.dcache.overall_misses 506099 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 439707 # number of replacements +system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use +system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 308507 # number of writebacks +system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 721 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 721 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use +system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 161820 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 282704 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 82097 # number of replacements +system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61702 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5108265750 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr b/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index 12f446c64..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,9 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout b/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index 5b0e0d9ff..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:23:58 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2554132875000 because target called exit() diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt deleted file mode 100644 index cbdec272c..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt +++ /dev/null @@ -1,1123 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4974822 # Number of BTB hits -global.BPredUnit.BTBHits 2263931 # Number of BTB hits -global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups -global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups -global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions. -global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect -global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted -global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted -global.BPredUnit.lookups 10092697 # Number of BP lookups -global.BPredUnit.lookups 5530798 # Number of BP lookups -global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. -global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 121094 # Simulator instruction rate (inst/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 463.72 # Real time elapsed on the host -host_tick_rate 4113887240 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56154063 # Number of instructions simulated -sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705350500 # Number of ticks simulated -system.cpu0.commit.COM:branches 5979955 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached -system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 69429521 -system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 52132882 7508.75% - 1 7659816 1103.25% - 2 4444319 640.12% - 3 2023012 291.38% - 4 1474688 212.40% - 5 453462 65.31% - 6 276660 39.85% - 7 294053 42.35% - 8 670629 96.59% -system.cpu0.commit.COM:committed_per_cycle.max_value 8 -system.cpu0.commit.COM:committed_per_cycle.end_dist - -system.cpu0.commit.COM:count 39866915 # Number of instructions committed -system.cpu0.commit.COM:loads 6404567 # Number of loads committed -system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831807 # Number of memory references committed -system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37661300 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated -system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 8080450 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2592009 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 922698 # number of replacements -system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297324 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking -system.cpu0.dtb.accesses 812630 # DTB accesses -system.cpu0.dtb.acv 800 # DTB access violations -system.cpu0.dtb.hits 11624529 # DTB hits -system.cpu0.dtb.misses 28502 # DTB misses -system.cpu0.dtb.read_accesses 605275 # DTB read accesses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7062851 # DTB read hits -system.cpu0.dtb.read_misses 24043 # DTB read misses -system.cpu0.dtb.write_accesses 207355 # DTB write accesses -system.cpu0.dtb.write_acv 204 # DTB write access violations -system.cpu0.dtb.write_hits 4561678 # DTB write hits -system.cpu0.dtb.write_misses 4459 # DTB write misses -system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 70522996 -system.cpu0.fetch.rateDist.min_value 0 - 0 60301622 8550.63% - 1 760699 107.87% - 2 1434176 203.36% - 3 635243 90.08% - 4 2330465 330.45% - 5 474381 67.27% - 6 552250 78.31% - 7 815542 115.64% - 8 3218618 456.39% -system.cpu0.fetch.rateDist.max_value 8 -system.cpu0.fetch.rateDist.end_dist - -system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency -system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses -system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 5806036 # number of overall hits -system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses -system.cpu0.icache.overall_misses 650298 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 619824 # number of replacements -system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate -system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed -system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value -system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back -system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18821888 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle -system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3324 0.01% # Type of FU issued - IntAlu 28266314 68.97% # Type of FU issued - IntMult 42210 0.10% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 12073 0.03% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 1656 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 7397265 18.05% # Type of FU issued - MemWrite 4611960 11.25% # Type of FU issued - IprAccess 650122 1.59% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.end_dist -system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst) -system.cpu0.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 33477 11.53% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 185557 63.91% # attempts to use FU when none available - MemWrite 71326 24.56% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996 -system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49763845 7056.40% - 1 10504305 1489.49% - 2 4625788 655.93% - 3 2839071 402.57% - 4 1729907 245.30% - 5 663571 94.09% - 6 315326 44.71% - 7 67073 9.51% - 8 14110 2.00% -system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.itb.accesses 875611 # ITB accesses -system.cpu0.itb.acv 895 # ITB acv -system.cpu0.itb.hits 845707 # ITB hits -system.cpu0.itb.misses 29904 # ITB misses -system.cpu0.kern.callpal 129595 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed -system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed -system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed -system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed -system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1284 -system.cpu0.kern.mode_good_user 1284 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2411 # number of times the context was actually changed -system.cpu0.kern.syscall 222 # number of syscalls executed -system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.numCycles 100900932 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.commit.COM:branches 2941268 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached -system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37417436 -system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29372797 7850.03% - 1 3570649 954.27% - 2 1730450 462.47% - 3 1048421 280.20% - 4 705992 188.68% - 5 261184 69.80% - 6 182468 48.77% - 7 141194 37.73% - 8 404281 108.05% -system.cpu1.commit.COM:committed_per_cycle.max_value 8 -system.cpu1.commit.COM:committed_per_cycle.end_dist - -system.cpu1.commit.COM:count 19624114 # Number of instructions committed -system.cpu1.commit.COM:loads 3545101 # Number of loads committed -system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5853378 # Number of memory references committed -system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18492763 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated -system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 4480566 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 1336410 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 531824 # number of replacements -system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158256 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking -system.cpu1.dtb.accesses 434054 # DTB accesses -system.cpu1.dtb.acv 76 # DTB access violations -system.cpu1.dtb.hits 6272530 # DTB hits -system.cpu1.dtb.misses 17149 # DTB misses -system.cpu1.dtb.read_accesses 314239 # DTB read accesses -system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3866975 # DTB read hits -system.cpu1.dtb.read_misses 13433 # DTB read misses -system.cpu1.dtb.write_accesses 119815 # DTB write accesses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_hits 2405555 # DTB write hits -system.cpu1.dtb.write_misses 3716 # DTB write misses -system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38058467 -system.cpu1.fetch.rateDist.min_value 0 - 0 33027824 8678.18% - 1 336540 88.43% - 2 683303 179.54% - 3 398795 104.78% - 4 792602 208.26% - 5 252574 66.36% - 6 340311 89.42% - 7 403731 106.08% - 8 1822787 478.94% -system.cpu1.fetch.rateDist.max_value 8 -system.cpu1.fetch.rateDist.end_dist - -system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency -system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses -system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 2613676 # number of overall hits -system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses -system.cpu1.icache.overall_misses 468089 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 446548 # number of replacements -system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use -system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed -system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate -system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed -system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value -system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back -system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9033918 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle -system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3984 0.02% # Type of FU issued - IntAlu 13446211 65.50% # Type of FU issued - IntMult 28837 0.14% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 13702 0.07% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 1986 0.01% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4170434 20.32% # Type of FU issued - MemWrite 2440876 11.89% # Type of FU issued - IprAccess 421203 2.05% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.end_dist -system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst) -system.cpu1.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 16051 7.28% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 131548 59.63% # attempts to use FU when none available - MemWrite 73016 33.10% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full.end_dist -system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467 -system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28368882 7454.03% - 1 4650018 1221.81% - 2 1988549 522.50% - 3 1356758 356.49% - 4 973103 255.69% - 5 468416 123.08% - 6 186236 48.93% - 7 54105 14.22% - 8 12400 3.26% -system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu1.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.itb.accesses 525300 # ITB accesses -system.cpu1.itb.acv 103 # ITB acv -system.cpu1.itb.hits 518475 # ITB hits -system.cpu1.itb.misses 6825 # ITB misses -system.cpu1.kern.callpal 87347 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed -system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed -system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed -system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed -system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 521 -system.cpu1.kern.mode_good_user 463 -system.cpu1.kern.mode_good_idle 58 -system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches -system.cpu1.kern.mode_switch_user 463 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1839 # number of times the context was actually changed -system.cpu1.kern.syscall 104 # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.numCycles 42759649 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41727 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41727 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41697 # number of replacements -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387818 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1893933 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 310350 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 455580 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.836093 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency -system.l2c.demand_hits 1893933 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses -system.l2c.demand_misses 627845 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1893933 # number of overall hits -system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles -system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses -system.l2c.overall_misses 627845 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 402113 # number of replacements -system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use -system.l2c.total_refs 2097138 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124275 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr new file mode 100755 index 000000000..4cafe060d --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -0,0 +1,5 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: 125740500: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout new file mode 100755 index 000000000..bace1f0ca --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:35:52 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1907705350500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt new file mode 100644 index 000000000..cbdec272c --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -0,0 +1,1123 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 4974822 # Number of BTB hits +global.BPredUnit.BTBHits 2263931 # Number of BTB hits +global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups +global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups +global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions. +global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect +global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted +global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted +global.BPredUnit.lookups 10092697 # Number of BP lookups +global.BPredUnit.lookups 5530798 # Number of BP lookups +global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. +global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. +host_inst_rate 121094 # Simulator instruction rate (inst/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 463.72 # Real time elapsed on the host +host_tick_rate 4113887240 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 56154063 # Number of instructions simulated +sim_seconds 1.907705 # Number of seconds simulated +sim_ticks 1907705350500 # Number of ticks simulated +system.cpu0.commit.COM:branches 5979955 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle.samples 69429521 +system.cpu0.commit.COM:committed_per_cycle.min_value 0 + 0 52132882 7508.75% + 1 7659816 1103.25% + 2 4444319 640.12% + 3 2023012 291.38% + 4 1474688 212.40% + 5 453462 65.31% + 6 276660 39.85% + 7 294053 42.35% + 8 670629 96.59% +system.cpu0.commit.COM:committed_per_cycle.max_value 8 +system.cpu0.commit.COM:committed_per_cycle.end_dist + +system.cpu0.commit.COM:count 39866915 # Number of instructions committed +system.cpu0.commit.COM:loads 6404567 # Number of loads committed +system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed +system.cpu0.commit.COM:refs 10831807 # Number of memory references committed +system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 37661300 # Number of Instructions Simulated +system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated +system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 8080450 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2592009 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 922698 # number of replacements +system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 297324 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking +system.cpu0.dtb.accesses 812630 # DTB accesses +system.cpu0.dtb.acv 800 # DTB access violations +system.cpu0.dtb.hits 11624529 # DTB hits +system.cpu0.dtb.misses 28502 # DTB misses +system.cpu0.dtb.read_accesses 605275 # DTB read accesses +system.cpu0.dtb.read_acv 596 # DTB read access violations +system.cpu0.dtb.read_hits 7062851 # DTB read hits +system.cpu0.dtb.read_misses 24043 # DTB read misses +system.cpu0.dtb.write_accesses 207355 # DTB write accesses +system.cpu0.dtb.write_acv 204 # DTB write access violations +system.cpu0.dtb.write_hits 4561678 # DTB write hits +system.cpu0.dtb.write_misses 4459 # DTB write misses +system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist.samples 70522996 +system.cpu0.fetch.rateDist.min_value 0 + 0 60301622 8550.63% + 1 760699 107.87% + 2 1434176 203.36% + 3 635243 90.08% + 4 2330465 330.45% + 5 474381 67.27% + 6 552250 78.31% + 7 815542 115.64% + 8 3218618 456.39% +system.cpu0.fetch.rateDist.max_value 8 +system.cpu0.fetch.rateDist.end_dist + +system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses +system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 5806036 # number of overall hits +system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses +system.cpu0.icache.overall_misses 650298 # number of overall misses +system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 619824 # number of replacements +system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use +system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate +system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed +system.cpu0.iew.EXEC:swp 0 # number of swp insts executed +system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value +system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back +system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.iew.WB:producers 18821888 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle +system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking +system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3324 0.01% # Type of FU issued + IntAlu 28266314 68.97% # Type of FU issued + IntMult 42210 0.10% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 12073 0.03% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1656 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 7397265 18.05% # Type of FU issued + MemWrite 4611960 11.25% # Type of FU issued + IprAccess 650122 1.59% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 33477 11.53% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 185557 63.91% # attempts to use FU when none available + MemWrite 71326 24.56% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full.end_dist +system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996 +system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 + 0 49763845 7056.40% + 1 10504305 1489.49% + 2 4625788 655.93% + 3 2839071 402.57% + 4 1729907 245.30% + 5 663571 94.09% + 6 315326 44.71% + 7 67073 9.51% + 8 14110 2.00% +system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu0.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate +system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.itb.accesses 875611 # ITB accesses +system.cpu0.itb.acv 895 # ITB acv +system.cpu0.itb.hits 845707 # ITB hits +system.cpu0.itb.misses 29904 # ITB misses +system.cpu0.kern.callpal 129595 # number of callpals executed +system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed +system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed +system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed +system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed +system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1284 +system.cpu0.kern.mode_good_user 1284 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2411 # number of times the context was actually changed +system.cpu0.kern.syscall 222 # number of syscalls executed +system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.numCycles 100900932 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed +system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.commit.COM:branches 2941268 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached +system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle.samples 37417436 +system.cpu1.commit.COM:committed_per_cycle.min_value 0 + 0 29372797 7850.03% + 1 3570649 954.27% + 2 1730450 462.47% + 3 1048421 280.20% + 4 705992 188.68% + 5 261184 69.80% + 6 182468 48.77% + 7 141194 37.73% + 8 404281 108.05% +system.cpu1.commit.COM:committed_per_cycle.max_value 8 +system.cpu1.commit.COM:committed_per_cycle.end_dist + +system.cpu1.commit.COM:count 19624114 # Number of instructions committed +system.cpu1.commit.COM:loads 3545101 # Number of loads committed +system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5853378 # Number of memory references committed +system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 18492763 # Number of Instructions Simulated +system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated +system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 4480566 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 1336410 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 531824 # number of replacements +system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 158256 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking +system.cpu1.dtb.accesses 434054 # DTB accesses +system.cpu1.dtb.acv 76 # DTB access violations +system.cpu1.dtb.hits 6272530 # DTB hits +system.cpu1.dtb.misses 17149 # DTB misses +system.cpu1.dtb.read_accesses 314239 # DTB read accesses +system.cpu1.dtb.read_acv 13 # DTB read access violations +system.cpu1.dtb.read_hits 3866975 # DTB read hits +system.cpu1.dtb.read_misses 13433 # DTB read misses +system.cpu1.dtb.write_accesses 119815 # DTB write accesses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_hits 2405555 # DTB write hits +system.cpu1.dtb.write_misses 3716 # DTB write misses +system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched +system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist.samples 38058467 +system.cpu1.fetch.rateDist.min_value 0 + 0 33027824 8678.18% + 1 336540 88.43% + 2 683303 179.54% + 3 398795 104.78% + 4 792602 208.26% + 5 252574 66.36% + 6 340311 89.42% + 7 403731 106.08% + 8 1822787 478.94% +system.cpu1.fetch.rateDist.max_value 8 +system.cpu1.fetch.rateDist.end_dist + +system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency +system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses +system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 2613676 # number of overall hits +system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses +system.cpu1.icache.overall_misses 468089 # number of overall misses +system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 446548 # number of replacements +system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use +system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed +system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate +system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed +system.cpu1.iew.EXEC:swp 0 # number of swp insts executed +system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value +system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back +system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.iew.WB:producers 9033918 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle +system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking +system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3984 0.02% # Type of FU issued + IntAlu 13446211 65.50% # Type of FU issued + IntMult 28837 0.14% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 13702 0.07% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1986 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 4170434 20.32% # Type of FU issued + MemWrite 2440876 11.89% # Type of FU issued + IprAccess 421203 2.05% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.end_dist +system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 16051 7.28% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 131548 59.63% # attempts to use FU when none available + MemWrite 73016 33.10% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full.end_dist +system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467 +system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 + 0 28368882 7454.03% + 1 4650018 1221.81% + 2 1988549 522.50% + 3 1356758 356.49% + 4 973103 255.69% + 5 468416 123.08% + 6 186236 48.93% + 7 54105 14.22% + 8 12400 3.26% +system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu1.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.itb.accesses 525300 # ITB accesses +system.cpu1.itb.acv 103 # ITB acv +system.cpu1.itb.hits 518475 # ITB hits +system.cpu1.itb.misses 6825 # ITB misses +system.cpu1.kern.callpal 87347 # number of callpals executed +system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed +system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed +system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed +system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed +system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed +system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 521 +system.cpu1.kern.mode_good_user 463 +system.cpu1.kern.mode_good_idle 58 +system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches +system.cpu1.kern.mode_switch_user 463 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1839 # number of times the context was actually changed +system.cpu1.kern.syscall 104 # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.numCycles 42759649 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed +system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 175 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41697 # number of replacements +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.387818 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41522 # number of writebacks +system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1893933 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310350 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 455580 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.836093 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.demand_hits 1893933 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses +system.l2c.demand_misses 627845 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1893933 # number of overall hits +system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles +system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses +system.l2c.overall_misses 627845 # number of overall misses +system.l2c.overall_mshr_hits 17 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 402113 # number of replacements +system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use +system.l2c.total_refs 2097138 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124275 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr deleted file mode 100755 index 4cafe060d..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr +++ /dev/null @@ -1,5 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: 125740500: Trying to launch CPU number 1! -warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout deleted file mode 100755 index bace1f0ca..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:35:52 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705350500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt deleted file mode 100644 index 4860b3f1d..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt +++ /dev/null @@ -1,674 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 6932487 # Number of BTB hits -global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted -global.BPredUnit.lookups 14559443 # Number of BP lookups -global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 123231 # Simulator instruction rate (inst/s) -host_mem_usage 290820 # Number of bytes of host memory used -host_seconds 430.51 # Real time elapsed on the host -host_tick_rate 4337505567 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53052618 # Number of instructions simulated -sim_seconds 1.867359 # Number of seconds simulated -sim_ticks 1867358550500 # Number of ticks simulated -system.cpu.commit.COM:branches 8455188 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 100543308 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 76317924 7590.55% - 1 10743540 1068.55% - 2 5987880 595.55% - 3 2987787 297.16% - 4 2072579 206.14% - 5 671161 66.75% - 6 395328 39.32% - 7 393271 39.11% - 8 973838 96.86% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 56244351 # Number of instructions committed -system.cpu.commit.COM:loads 9302477 # Number of loads committed -system.cpu.commit.COM:membars 227741 # Number of memory barriers committed -system.cpu.commit.COM:refs 15692393 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53052618 # Number of Instructions Simulated -system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated -system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency -system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 11726365 # number of overall hits -system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3763307 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1402096 # number of replacements -system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use -system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430429 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 1229941 # DTB accesses -system.cpu.dtb.acv 828 # DTB access violations -system.cpu.dtb.hits 16757791 # DTB hits -system.cpu.dtb.misses 44378 # DTB misses -system.cpu.dtb.read_accesses 908364 # DTB read accesses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_hits 10166755 # DTB read hits -system.cpu.dtb.read_misses 36227 # DTB read misses -system.cpu.dtb.write_accesses 321577 # DTB write accesses -system.cpu.dtb.write_acv 241 # DTB write access violations -system.cpu.dtb.write_hits 6591036 # DTB write hits -system.cpu.dtb.write_misses 8151 # DTB write misses -system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched -system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 102189280 -system.cpu.fetch.rateDist.min_value 0 - 0 87752503 8587.25% - 1 1049427 102.69% - 2 2020193 197.69% - 3 968502 94.78% - 4 3001129 293.68% - 5 683878 66.92% - 6 831667 81.38% - 7 1217349 119.13% - 8 4664632 456.47% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency -system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses -system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7948798 # number of overall hits -system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses -system.cpu.icache.overall_misses 1047360 # number of overall misses -system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 994691 # number of replacements -system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use -system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9157080 # Number of branches executed -system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate -system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6614103 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value -system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26369407 # num instructions producing a value -system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle -system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 7284 0.01% # Type of FU issued - IntAlu 39585322 68.15% # Type of FU issued - IntMult 61995 0.11% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 25609 0.04% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 3636 0.01% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 10781907 18.56% # Type of FU issued - MemWrite 6666291 11.48% # Type of FU issued - IprAccess 953214 1.64% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 52004 11.98% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 278726 64.23% # attempts to use FU when none available - MemWrite 103217 23.79% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 73101546 7153.54% - 1 14613738 1430.07% - 2 6411296 627.39% - 3 3930297 384.61% - 4 2526857 247.27% - 5 1033193 101.11% - 6 443511 43.40% - 7 107158 10.49% - 8 21684 2.12% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate -system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1300570 # ITB accesses -system.cpu.itb.acv 941 # ITB acv -system.cpu.itb.hits 1261136 # ITB hits -system.cpu.itb.misses 39434 # ITB misses -system.cpu.kern.callpal 192636 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1911 -system.cpu.kern.mode_good_user 1741 -system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches -system.cpu.kern.mode_switch_user 1741 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.numCycles 136890724 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed -system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41725 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41725 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41685 # number of replacements -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267378 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1786309 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 311028 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430429 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency -system.l2c.demand_hits 1786309 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses -system.l2c.demand_misses 611623 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1786309 # number of overall hits -system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles -system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses -system.l2c.overall_misses 611623 # number of overall misses -system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 396037 # number of replacements -system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use -system.l2c.total_refs 1966986 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119087 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr new file mode 100755 index 000000000..1a557daf8 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -0,0 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout new file mode 100755 index 000000000..f6f2f7d37 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:31:00 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1867358550500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt new file mode 100644 index 000000000..4860b3f1d --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -0,0 +1,674 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 6932487 # Number of BTB hits +global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups +global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted +global.BPredUnit.lookups 14559443 # Number of BP lookups +global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. +host_inst_rate 123231 # Simulator instruction rate (inst/s) +host_mem_usage 290820 # Number of bytes of host memory used +host_seconds 430.51 # Real time elapsed on the host +host_tick_rate 4337505567 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 53052618 # Number of instructions simulated +sim_seconds 1.867359 # Number of seconds simulated +sim_ticks 1867358550500 # Number of ticks simulated +system.cpu.commit.COM:branches 8455188 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 100543308 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 76317924 7590.55% + 1 10743540 1068.55% + 2 5987880 595.55% + 3 2987787 297.16% + 4 2072579 206.14% + 5 671161 66.75% + 6 395328 39.32% + 7 393271 39.11% + 8 973838 96.86% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 56244351 # Number of instructions committed +system.cpu.commit.COM:loads 9302477 # Number of loads committed +system.cpu.commit.COM:membars 227741 # Number of memory barriers committed +system.cpu.commit.COM:refs 15692393 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53052618 # Number of Instructions Simulated +system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated +system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 11726365 # number of overall hits +system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3763307 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1402096 # number of replacements +system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use +system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430429 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 1229941 # DTB accesses +system.cpu.dtb.acv 828 # DTB access violations +system.cpu.dtb.hits 16757791 # DTB hits +system.cpu.dtb.misses 44378 # DTB misses +system.cpu.dtb.read_accesses 908364 # DTB read accesses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_hits 10166755 # DTB read hits +system.cpu.dtb.read_misses 36227 # DTB read misses +system.cpu.dtb.write_accesses 321577 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6591036 # DTB write hits +system.cpu.dtb.write_misses 8151 # DTB write misses +system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched +system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 102189280 +system.cpu.fetch.rateDist.min_value 0 + 0 87752503 8587.25% + 1 1049427 102.69% + 2 2020193 197.69% + 3 968502 94.78% + 4 3001129 293.68% + 5 683878 66.92% + 6 831667 81.38% + 7 1217349 119.13% + 8 4664632 456.47% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 7948798 # number of overall hits +system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047360 # number of overall misses +system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 994691 # number of replacements +system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use +system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9157080 # Number of branches executed +system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate +system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6614103 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value +system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 26369407 # num instructions producing a value +system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle +system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 7284 0.01% # Type of FU issued + IntAlu 39585322 68.15% # Type of FU issued + IntMult 61995 0.11% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 25609 0.04% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 3636 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 10781907 18.56% # Type of FU issued + MemWrite 6666291 11.48% # Type of FU issued + IprAccess 953214 1.64% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 52004 11.98% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 278726 64.23% # attempts to use FU when none available + MemWrite 103217 23.79% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 73101546 7153.54% + 1 14613738 1430.07% + 2 6411296 627.39% + 3 3930297 384.61% + 4 2526857 247.27% + 5 1033193 101.11% + 6 443511 43.40% + 7 107158 10.49% + 8 21684 2.12% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate +system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1300570 # ITB accesses +system.cpu.itb.acv 941 # ITB acv +system.cpu.itb.hits 1261136 # ITB hits +system.cpu.itb.misses 39434 # ITB misses +system.cpu.kern.callpal 192636 # number of callpals executed +system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1741 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches +system.cpu.kern.mode_switch_user 1741 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.numCycles 136890724 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed +system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41685 # number of replacements +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 1.267378 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41512 # number of writebacks +system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1786309 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311028 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430429 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.demand_hits 1786309 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses +system.l2c.demand_misses 611623 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1786309 # number of overall hits +system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses +system.l2c.overall_misses 611623 # number of overall misses +system.l2c.overall_mshr_hits 1 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 396037 # number of replacements +system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use +system.l2c.total_refs 1966986 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119087 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr deleted file mode 100755 index 1a557daf8..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout deleted file mode 100755 index f6f2f7d37..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:31:00 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867358550500 because m5_exit instruction encountered diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 042194df8..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2390204 # Simulator instruction rate (inst/s) -host_mem_usage 328072 # Number of bytes of host memory used -host_seconds 102.01 # Real time elapsed on the host -host_tick_rate 1198022319 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215830000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 244431661 # number of cpu cycles simulated -system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..2fac0077c --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:56:43 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 122215830000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..042194df8 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2390204 # Simulator instruction rate (inst/s) +host_mem_usage 328072 # Number of bytes of host memory used +host_seconds 102.01 # Real time elapsed on the host +host_tick_rate 1198022319 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.122216 # Number of seconds simulated +sim_ticks 122215830000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 2fac0077c..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,32 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:56:43 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 122215830000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 8d551e127..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1337728 # Simulator instruction rate (inst/s) -host_mem_usage 335528 # Number of bytes of host memory used -host_seconds 182.28 # Real time elapsed on the host -host_tick_rate 2010386962 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.366446 # Number of seconds simulated -sim_ticks 366445521000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency -system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses -system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 104134565 # number of overall hits -system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses -system.cpu.dcache.overall_misses 987820 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 882 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244430745 # number of overall hits -system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 882 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use -system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 892653 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 47800 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 891 # number of replacements -system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use -system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 41 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 732891042 # number of cpu cycles simulated -system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..0d7d366fc --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:52:55 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 366445521000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..8d551e127 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1337728 # Simulator instruction rate (inst/s) +host_mem_usage 335528 # Number of bytes of host memory used +host_seconds 182.28 # Real time elapsed on the host +host_tick_rate 2010386962 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.366446 # Number of seconds simulated +sim_ticks 366445521000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency +system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses +system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 104134565 # number of overall hits +system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses +system.cpu.dcache.overall_misses 987820 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 935475 # number of replacements +system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 94875 # number of writebacks +system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency +system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_misses 882 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 244430745 # number of overall hits +system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_misses 882 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use +system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 892653 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47800 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 891 # number of replacements +system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 41 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 732891042 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 0d7d366fc..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,32 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:52:55 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 366445521000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index ee5db6e3c..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1935457 # Simulator instruction rate (inst/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 139.35 # Real time elapsed on the host -host_tick_rate 1189355805 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.165732 # Number of seconds simulated -sim_ticks 165731691000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331463383 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..195b58e3f --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:20:12 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 165731691000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..ee5db6e3c --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1935457 # Simulator instruction rate (inst/s) +host_mem_usage 329540 # Number of bytes of host memory used +host_seconds 139.35 # Real time elapsed on the host +host_tick_rate 1189355805 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269697303 # Number of instructions simulated +sim_seconds 0.165732 # Number of seconds simulated +sim_ticks 165731691000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 331463383 # number of cpu cycles simulated +system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.num_refs 124054655 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index 72ba90ece..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 195b58e3f..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,32 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:20:12 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 165731691000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 94a44a507..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1084581 # Simulator instruction rate (inst/s) -host_mem_usage 336400 # Number of bytes of host memory used -host_seconds 248.67 # Real time elapsed on the host -host_tick_rate 1992187591 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.495388 # Number of seconds simulated -sim_ticks 495387670000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency -system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 120039828 # number of overall hits -system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2179365 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2049944 # number of replacements -system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use -system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses 807 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331462528 # number of overall hits -system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses 807 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use -system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1862007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 192840 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 108885 # number of replacements -system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 70892 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990775340 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..a552023cf --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 13 2008 21:51:42 +M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 +M5 commit date Sun Nov 09 21:57:15 2008 -0800 +M5 started Nov 13 2008 21:51:43 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 495387670000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..94a44a507 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1084581 # Simulator instruction rate (inst/s) +host_mem_usage 336400 # Number of bytes of host memory used +host_seconds 248.67 # Real time elapsed on the host +host_tick_rate 1992187591 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269697303 # Number of instructions simulated +sim_seconds 0.495388 # Number of seconds simulated +sim_ticks 495387670000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency +system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 120039828 # number of overall hits +system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2179365 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2049944 # number of replacements +system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use +system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 229129 # number of writebacks +system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses 807 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 331462528 # number of overall hits +system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses 807 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use +system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1862007 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192840 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 108885 # number of replacements +system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 70892 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 990775340 # number of cpu cycles simulated +system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.num_refs 124054655 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr b/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index 72ba90ece..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index a552023cf..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,32 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 13 2008 21:51:42 -M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 -M5 commit date Sun Nov 09 21:57:15 2008 -0800 -M5 started Nov 13 2008 21:51:43 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 495387670000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 6c9e86c42..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1589069 # Simulator instruction rate (inst/s) -host_mem_usage 198676 # Number of bytes of host memory used -host_seconds 941.11 # Real time elapsed on the host -host_tick_rate 923042875 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492702 # Number of instructions simulated -sim_seconds 0.868687 # Number of seconds simulated -sim_ticks 868687490500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737374982 # number of cpu cycles simulated -system.cpu.num_insts 1495492702 # Number of instructions executed -system.cpu.num_refs 533549000 # Number of memory references -system.cpu.workload.PROG:num_syscalls 551 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..90786ddde --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:22:32 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 868687490500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..6c9e86c42 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1589069 # Simulator instruction rate (inst/s) +host_mem_usage 198676 # Number of bytes of host memory used +host_seconds 941.11 # Real time elapsed on the host +host_tick_rate 923042875 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1495492702 # Number of instructions simulated +sim_seconds 0.868687 # Number of seconds simulated +sim_ticks 868687490500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1737374982 # number of cpu cycles simulated +system.cpu.num_insts 1495492702 # Number of instructions executed +system.cpu.num_refs 533549000 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index eae22fffc..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 90786ddde..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,75 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:22:32 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - - Reading the dictionary files: ************************************************* - 58924 words stored in 3784810 bytes - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 868687490500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 803dc9bdb..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 588841 # Simulator instruction rate (inst/s) -host_mem_usage 206816 # Number of bytes of host memory used -host_seconds 2539.72 # Real time elapsed on the host -host_tick_rate 941590971 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492697 # Number of instructions simulated -sim_seconds 2.391380 # Number of seconds simulated -sim_ticks 2391380378000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069450 # number of overall hits -system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3192961 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2513875 # number of replacements -system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use -system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1737372102 # number of overall hits -system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses 2813 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use -system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1310104 # number of overall hits -system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1210680 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 663512 # number of replacements -system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 481430 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4782760756 # number of cpu cycles simulated -system.cpu.num_insts 1495492697 # Number of instructions executed -system.cpu.num_refs 533549000 # Number of memory references -system.cpu.workload.PROG:num_syscalls 551 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..f24226fff --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 9 2008 18:23:31 +M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e +M5 commit date Sat Nov 08 21:06:07 2008 -0800 +M5 started Nov 9 2008 18:34:37 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 2391380378000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..803dc9bdb --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 588841 # Simulator instruction rate (inst/s) +host_mem_usage 206816 # Number of bytes of host memory used +host_seconds 2539.72 # Real time elapsed on the host +host_tick_rate 941590971 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1495492697 # Number of instructions simulated +sim_seconds 2.391380 # Number of seconds simulated +sim_ticks 2391380378000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 530069450 # number of overall hits +system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3192961 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2513875 # number of replacements +system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1463913 # number of writebacks +system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1737372102 # number of overall hits +system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses 2813 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use +system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1310104 # number of overall hits +system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1210680 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 663512 # number of replacements +system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 481430 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4782760756 # number of cpu cycles simulated +system.cpu.num_insts 1495492697 # Number of instructions executed +system.cpu.num_refs 533549000 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stderr b/tests/long/20.parser/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index eae22fffc..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stdout b/tests/long/20.parser/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index f24226fff..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,75 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 9 2008 18:23:31 -M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e -M5 commit date Sat Nov 08 21:06:07 2008 -0800 -M5 started Nov 9 2008 18:34:37 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - - Reading the dictionary files: ************************************************* - 58924 words stored in 3784810 bytes - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 2391380378000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 704dd86aa..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38296034 # Number of BTB hits -global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted -global.BPredUnit.lookups 62209737 # Number of BP lookups -global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 151728 # Simulator instruction rate (inst/s) -host_mem_usage 209656 # Number of bytes of host memory used -host_seconds 2475.31 # Real time elapsed on the host -host_tick_rate 54537175 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134997 # Number of seconds simulated -sim_ticks 134996684500 # Number of ticks simulated -system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 254545672 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123085209 4835.49% - 1 50466868 1982.63% - 2 18758377 736.94% - 3 19955031 783.95% - 4 11844121 465.30% - 5 8478667 333.09% - 6 5819307 228.62% - 7 2974518 116.86% - 8 13163574 517.14% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 398664594 # Number of instructions committed -system.cpu.commit.COM:loads 100651995 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183397 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574819 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169002312 # number of overall hits -system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19726 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 782 # number of replacements -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use -system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 635 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 185115437 # DTB accesses -system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 185076670 # DTB hits -system.cpu.dtb.misses 38767 # DTB misses -system.cpu.dtb.read_accesses 104449499 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 104412186 # DTB read hits -system.cpu.dtb.read_misses 37313 # DTB read misses -system.cpu.dtb.write_accesses 80665938 # DTB write accesses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_hits 80664484 # DTB write hits -system.cpu.dtb.write_misses 1454 # DTB write misses -system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched -system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 269852647 -system.cpu.fetch.rateDist.min_value 0 - 0 164102333 6081.18% - 1 12367121 458.29% - 2 12410556 459.90% - 3 6615129 245.14% - 4 15923029 590.06% - 5 8709903 322.77% - 6 6580254 243.85% - 7 4007808 148.52% - 8 39136514 1450.29% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency -system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 63861348 # number of overall hits -system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 4841 # number of overall misses -system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use -system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50976851 # Number of branches executed -system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate -system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80676625 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value -system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200770520 # num instructions producing a value -system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle -system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 33581 0.01% # Type of FU issued - IntAlu 166319014 38.71% # Type of FU issued - IntMult 2152935 0.50% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 35077566 8.17% # Type of FU issued - FloatCmp 7830879 1.82% # Type of FU issued - FloatCvt 2898460 0.67% # Type of FU issued - FloatMult 16788316 3.91% # Type of FU issued - FloatDiv 1569716 0.37% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 113503270 26.42% # Type of FU issued - MemWrite 83426459 19.42% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 40640 0.39% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 76056 0.73% # attempts to use FU when none available - FloatCmp 13381 0.13% # attempts to use FU when none available - FloatCvt 12891 0.12% # attempts to use FU when none available - FloatMult 1723474 16.48% # attempts to use FU when none available - FloatDiv 1473560 14.09% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5907144 56.49% # attempts to use FU when none available - MemWrite 1209900 11.57% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99465935 3685.94% - 1 57766030 2140.65% - 2 39984554 1481.72% - 3 29664959 1099.30% - 4 23966120 888.12% - 5 10452563 387.34% - 6 5712016 211.67% - 7 2252970 83.49% - 8 587500 21.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate -system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 63866476 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 63866189 # ITB hits -system.cpu.itb.misses 287 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 655 # number of overall hits -system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7418 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use -system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 269993372 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..19732539d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,49 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +warn: Increasing stack size by one page. +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..2bc3bdeed --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Eon, Version 1.1 +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..704dd86aa --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 38296034 # Number of BTB hits +global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted +global.BPredUnit.lookups 62209737 # Number of BP lookups +global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. +host_inst_rate 151728 # Simulator instruction rate (inst/s) +host_mem_usage 209656 # Number of bytes of host memory used +host_seconds 2475.31 # Real time elapsed on the host +host_tick_rate 54537175 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 375574819 # Number of instructions simulated +sim_seconds 0.134997 # Number of seconds simulated +sim_ticks 134996684500 # Number of ticks simulated +system.cpu.commit.COM:branches 44587532 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 254545672 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 123085209 4835.49% + 1 50466868 1982.63% + 2 18758377 736.94% + 3 19955031 783.95% + 4 11844121 465.30% + 5 8478667 333.09% + 6 5819307 228.62% + 7 2974518 116.86% + 8 13163574 517.14% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 398664594 # Number of instructions committed +system.cpu.commit.COM:loads 100651995 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 174183397 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574819 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated +system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses +system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 169002312 # number of overall hits +system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses +system.cpu.dcache.overall_misses 19726 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 782 # number of replacements +system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use +system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 635 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 185115437 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 185076670 # DTB hits +system.cpu.dtb.misses 38767 # DTB misses +system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 104412186 # DTB read hits +system.cpu.dtb.read_misses 37313 # DTB read misses +system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80664484 # DTB write hits +system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched +system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 269852647 +system.cpu.fetch.rateDist.min_value 0 + 0 164102333 6081.18% + 1 12367121 458.29% + 2 12410556 459.90% + 3 6615129 245.14% + 4 15923029 590.06% + 5 8709903 322.77% + 6 6580254 243.85% + 7 4007808 148.52% + 8 39136514 1450.29% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 63861348 # number of overall hits +system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.overall_misses 4841 # number of overall misses +system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use +system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50976851 # Number of branches executed +system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate +system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80676625 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value +system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 200770520 # num instructions producing a value +system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle +system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 33581 0.01% # Type of FU issued + IntAlu 166319014 38.71% # Type of FU issued + IntMult 2152935 0.50% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 35077566 8.17% # Type of FU issued + FloatCmp 7830879 1.82% # Type of FU issued + FloatCvt 2898460 0.67% # Type of FU issued + FloatMult 16788316 3.91% # Type of FU issued + FloatDiv 1569716 0.37% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 113503270 26.42% # Type of FU issued + MemWrite 83426459 19.42% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 40640 0.39% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 76056 0.73% # attempts to use FU when none available + FloatCmp 13381 0.13% # attempts to use FU when none available + FloatCvt 12891 0.12% # attempts to use FU when none available + FloatMult 1723474 16.48% # attempts to use FU when none available + FloatDiv 1473560 14.09% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 5907144 56.49% # attempts to use FU when none available + MemWrite 1209900 11.57% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 99465935 3685.94% + 1 57766030 2140.65% + 2 39984554 1481.72% + 3 29664959 1099.30% + 4 23966120 888.12% + 5 10452563 387.34% + 6 5712016 211.67% + 7 2252970 83.49% + 8 587500 21.77% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate +system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63866476 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 63866189 # ITB hits +system.cpu.itb.misses 287 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 655 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7418 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 14 # number of replacements +system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use +system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 269993372 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed +system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index 19732539d..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,49 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -warn: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 2bc3bdeed..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Eon, Version 1.1 -OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 520bb514f..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3407773 # Simulator instruction rate (inst/s) -host_mem_usage 201328 # Number of bytes of host memory used -host_seconds 116.99 # Real time elapsed on the host -host_tick_rate 1703884563 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664595 # Number of instructions simulated -sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332411500 # Number of ticks simulated -system.cpu.dtb.accesses 168275274 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 168275218 # DTB hits -system.cpu.dtb.misses 56 # DTB misses -system.cpu.dtb.read_accesses 94754510 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 94754489 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.write_accesses 73520764 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 73520729 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 398664824 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 398664651 # ITB hits -system.cpu.itb.misses 173 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 398664824 # number of cpu cycles simulated -system.cpu.num_insts 398664595 # Number of instructions executed -system.cpu.num_refs 174183453 # Number of memory references -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..19732539d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,49 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +warn: Increasing stack size by one page. +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..bb141923e --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:02 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Eon, Version 1.1 +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..520bb514f --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3407773 # Simulator instruction rate (inst/s) +host_mem_usage 201328 # Number of bytes of host memory used +host_seconds 116.99 # Real time elapsed on the host +host_tick_rate 1703884563 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 398664595 # Number of instructions simulated +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332411500 # Number of ticks simulated +system.cpu.dtb.accesses 168275274 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 168275218 # DTB hits +system.cpu.dtb.misses 56 # DTB misses +system.cpu.dtb.read_accesses 94754510 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 94754489 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 73520764 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73520729 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 398664824 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 398664651 # ITB hits +system.cpu.itb.misses 173 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.num_insts 398664595 # Number of instructions executed +system.cpu.num_refs 174183453 # Number of memory references +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index 19732539d..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,49 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -warn: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index bb141923e..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:26:02 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Eon, Version 1.1 -OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 99f2593a9..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1526276 # Simulator instruction rate (inst/s) -host_mem_usage 208780 # Number of bytes of host memory used -host_seconds 261.20 # Real time elapsed on the host -host_tick_rate 2172088412 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567352 # Number of seconds simulated -sim_ticks 567351850000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4264 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.dtb.accesses 168275276 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 168275220 # DTB hits -system.cpu.dtb.misses 56 # DTB misses -system.cpu.dtb.read_accesses 94754511 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 94754490 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.write_accesses 73520765 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 73520730 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_misses 3673 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use -system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 398664839 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 398664666 # ITB hits -system.cpu.itb.misses 173 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 585 # number of overall hits -system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7240 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 15 # number of replacements -system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use -system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134703700 # number of cpu cycles simulated -system.cpu.num_insts 398664609 # Number of instructions executed -system.cpu.num_refs 174183455 # Number of memory references -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..19732539d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,49 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +warn: Increasing stack size by one page. +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..c8c05bf7d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:22:18 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Eon, Version 1.1 +OO-style eon Time= 0.566667 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..99f2593a9 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1526276 # Simulator instruction rate (inst/s) +host_mem_usage 208780 # Number of bytes of host memory used +host_seconds 261.20 # Real time elapsed on the host +host_tick_rate 2172088412 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 398664609 # Number of instructions simulated +sim_seconds 0.567352 # Number of seconds simulated +sim_ticks 567351850000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168270956 # number of overall hits +system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4264 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 625 # number of writebacks +system.cpu.dtb.accesses 168275276 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 168275220 # DTB hits +system.cpu.dtb.misses 56 # DTB misses +system.cpu.dtb.read_accesses 94754511 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 94754490 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 73520765 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73520730 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660993 # number of overall hits +system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_misses 3673 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1769 # number of replacements +system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use +system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 398664839 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 398664666 # ITB hits +system.cpu.itb.misses 173 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 585 # number of overall hits +system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7240 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use +system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1134703700 # number of cpu cycles simulated +system.cpu.num_insts 398664609 # Number of instructions executed +system.cpu.num_refs 174183455 # Number of memory references +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index 19732539d..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,49 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -warn: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index c8c05bf7d..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:22:18 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Eon, Version 1.1 -OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 2e0ae6799..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 240462096 # Number of BTB hits -global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups -global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -global.BPredUnit.lookups 349424731 # Number of BP lookups -global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. -host_inst_rate 157306 # Simulator instruction rate (inst/s) -host_mem_usage 209560 # Number of bytes of host memory used -host_seconds 11589.17 # Real time elapsed on the host -host_tick_rate 60846406 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1823043370 # Number of instructions simulated -sim_seconds 0.705159 # Number of seconds simulated -sim_ticks 705159454500 # Number of ticks simulated -system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1310002800 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 603585596 4607.51% - 1 273587005 2088.45% - 2 174037133 1328.52% - 3 65399708 499.23% - 4 48333001 368.95% - 5 34003110 259.57% - 6 18481318 141.08% - 7 23715685 181.04% - 8 68860244 525.65% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 2008987604 # Number of instructions committed -system.cpu.commit.COM:loads 511595302 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 722390433 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1823043370 # Number of Instructions Simulated -system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674038251 # number of overall hits -system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2493914 # number of overall misses -system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1526847 # number of replacements -system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use -system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 775959987 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 775335043 # DTB hits -system.cpu.dtb.misses 624944 # DTB misses -system.cpu.dtb.read_accesses 516992085 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 516404963 # DTB read hits -system.cpu.dtb.read_misses 587122 # DTB read misses -system.cpu.dtb.write_accesses 258967902 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258930080 # DTB write hits -system.cpu.dtb.write_misses 37822 # DTB write misses -system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched -system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1410161885 -system.cpu.fetch.rateDist.min_value 0 - 0 830588040 5890.02% - 1 53463106 379.13% - 2 39766072 282.00% - 3 63538024 450.57% - 4 121390719 860.83% - 5 35256321 250.02% - 6 38761682 274.87% - 7 6988644 49.56% - 8 220409277 1563.01% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency -system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 348437250 # number of overall hits -system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_misses 10649 # number of overall misses -system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8097 # number of replacements -system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use -system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274534145 # Number of branches executed -system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate -system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258968900 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value -system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136229268 # num instructions producing a value -system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle -system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2752 0.00% # Type of FU issued - IntAlu 1204412678 57.64% # Type of FU issued - IntMult 17591 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 27851349 1.33% # Type of FU issued - FloatCmp 8254694 0.40% # Type of FU issued - FloatCvt 7204646 0.34% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 557993260 26.70% # Type of FU issued - MemWrite 283770831 13.58% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 8291 0.02% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 28032977 75.57% # attempts to use FU when none available - MemWrite 9052278 24.40% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 537278436 3810.05% - 1 285217724 2022.59% - 2 273546804 1939.83% - 3 154810620 1097.82% - 4 63341841 449.18% - 5 51438515 364.77% - 6 32491109 230.41% - 7 9036668 64.08% - 8 3000168 21.28% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate -system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 348448092 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 348447899 # ITB hits -system.cpu.itb.misses 193 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28934 # number of overall hits -system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511777 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1474251 # number of replacements -system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use -system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66899 # number of writebacks -system.cpu.numCycles 1410318910 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed -system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..ac5607abe --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..7f7e7a869 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,1391 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. 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2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..2e0ae6799 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 240462096 # Number of BTB hits +global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups +global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted +global.BPredUnit.lookups 349424731 # Number of BP lookups +global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +host_inst_rate 157306 # Simulator instruction rate (inst/s) +host_mem_usage 209560 # Number of bytes of host memory used +host_seconds 11589.17 # Real time elapsed on the host +host_tick_rate 60846406 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1823043370 # Number of instructions simulated +sim_seconds 0.705159 # Number of seconds simulated +sim_ticks 705159454500 # Number of ticks simulated +system.cpu.commit.COM:branches 266706457 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1310002800 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 603585596 4607.51% + 1 273587005 2088.45% + 2 174037133 1328.52% + 3 65399708 499.23% + 4 48333001 368.95% + 5 34003110 259.57% + 6 18481318 141.08% + 7 23715685 181.04% + 8 68860244 525.65% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 2008987604 # Number of instructions committed +system.cpu.commit.COM:loads 511595302 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 722390433 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1823043370 # Number of Instructions Simulated +system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated +system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 674038251 # number of overall hits +system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2493914 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1526847 # number of replacements +system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use +system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 775959987 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 775335043 # DTB hits +system.cpu.dtb.misses 624944 # DTB misses +system.cpu.dtb.read_accesses 516992085 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 516404963 # DTB read hits +system.cpu.dtb.read_misses 587122 # DTB read misses +system.cpu.dtb.write_accesses 258967902 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 258930080 # DTB write hits +system.cpu.dtb.write_misses 37822 # DTB write misses +system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched +system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 1410161885 +system.cpu.fetch.rateDist.min_value 0 + 0 830588040 5890.02% + 1 53463106 379.13% + 2 39766072 282.00% + 3 63538024 450.57% + 4 121390719 860.83% + 5 35256321 250.02% + 6 38761682 274.87% + 7 6988644 49.56% + 8 220409277 1563.01% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses +system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 348437250 # number of overall hits +system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses +system.cpu.icache.overall_misses 10649 # number of overall misses +system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 8097 # number of replacements +system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use +system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 274534145 # Number of branches executed +system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate +system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258968900 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value +system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1136229268 # num instructions producing a value +system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle +system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 2752 0.00% # Type of FU issued + IntAlu 1204412678 57.64% # Type of FU issued + IntMult 17591 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 27851349 1.33% # Type of FU issued + FloatCmp 8254694 0.40% # Type of FU issued + FloatCvt 7204646 0.34% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 557993260 26.70% # Type of FU issued + MemWrite 283770831 13.58% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 8291 0.02% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 28032977 75.57% # attempts to use FU when none available + MemWrite 9052278 24.40% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 537278436 3810.05% + 1 285217724 2022.59% + 2 273546804 1939.83% + 3 154810620 1097.82% + 4 63341841 449.18% + 5 51438515 364.77% + 6 32491109 230.41% + 7 9036668 64.08% + 8 3000168 21.28% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate +system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 348448092 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 348447899 # ITB hits +system.cpu.itb.misses 193 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 28934 # number of overall hits +system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511777 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 1474251 # number of replacements +system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.numCycles 1410318910 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed +system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index ac5607abe..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 7f7e7a869..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,1391 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. 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-host_mem_usage 200500 # Number of bytes of host memory used -host_seconds 620.53 # Real time elapsed on the host -host_tick_rate 1619110797 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987605 # Number of instructions simulated -sim_seconds 1.004711 # Number of seconds simulated -sim_ticks 1004710587000 # Number of ticks simulated -system.cpu.dtb.accesses 722298387 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 721864922 # DTB hits -system.cpu.dtb.misses 433465 # DTB misses -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2009421175 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2009421070 # ITB hits -system.cpu.itb.misses 105 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2009421175 # number of cpu cycles simulated -system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722823898 # Number of memory references -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..ac5607abe --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..30786b895 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,1391 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:39 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. 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200500 # Number of bytes of host memory used +host_seconds 620.53 # Real time elapsed on the host +host_tick_rate 1619110797 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2008987605 # Number of instructions simulated +sim_seconds 1.004711 # Number of seconds simulated +sim_ticks 1004710587000 # Number of ticks simulated +system.cpu.dtb.accesses 722298387 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 721864922 # DTB hits +system.cpu.dtb.misses 433465 # DTB misses +system.cpu.dtb.read_accesses 511488910 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 511070026 # DTB read hits +system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.write_accesses 210809477 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 210794896 # DTB write hits +system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2009421175 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2009421070 # ITB hits +system.cpu.itb.misses 105 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2009421175 # number of cpu cycles simulated +system.cpu.num_insts 2008987605 # Number of instructions executed +system.cpu.num_refs 722823898 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index ac5607abe..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 30786b895..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,1391 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:26:39 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. 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-host_mem_usage 207960 # Number of bytes of host memory used -host_seconds 1427.47 # Real time elapsed on the host -host_tick_rate 1971983298 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.814951 # Number of seconds simulated -sim_ticks 2814951154000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency -system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 720331943 # number of overall hits -system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1532979 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.dtb.accesses 722298387 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 721864922 # DTB hits -system.cpu.dtb.misses 433465 # DTB misses -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses -system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency -system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2009410475 # number of overall hits -system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_misses 10596 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use -system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2009421176 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2009421071 # ITB hits -system.cpu.itb.misses 105 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 29320 # number of overall hits -system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511420 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1473608 # number of replacements -system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use -system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66899 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5629902308 # number of cpu cycles simulated -system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722823898 # Number of memory references -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..ac5607abe --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..5e421444e --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,1391 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 3428045644 +1332000: 2815822229 +1331000: 1093465585 +1330000: 3012217108 +1329000: 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+host_mem_usage 207960 # Number of bytes of host memory used +host_seconds 1427.47 # Real time elapsed on the host +host_tick_rate 1971983298 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2008987605 # Number of instructions simulated +sim_seconds 2.814951 # Number of seconds simulated +sim_ticks 2814951154000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 720331943 # number of overall hits +system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1532979 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1526048 # number of replacements +system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.dtb.accesses 722298387 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 721864922 # DTB hits +system.cpu.dtb.misses 433465 # DTB misses +system.cpu.dtb.read_accesses 511488910 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 511070026 # DTB read hits +system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.write_accesses 210809477 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 210794896 # DTB write hits +system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2009410475 # number of overall hits +system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_misses 10596 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 9046 # number of replacements +system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use +system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2009421176 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2009421071 # ITB hits +system.cpu.itb.misses 105 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 29320 # number of overall hits +system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511420 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 1473608 # number of replacements +system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5629902308 # number of cpu cycles simulated +system.cpu.num_insts 2008987605 # Number of instructions executed +system.cpu.num_refs 722823898 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index ac5607abe..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 5e421444e..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,1391 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. 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2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 36c3049e3..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8039250 # Number of BTB hits -global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted -global.BPredUnit.lookups 16249463 # Number of BP lookups -global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 155507 # Simulator instruction rate (inst/s) -host_mem_usage 212996 # Number of bytes of host memory used -host_seconds 511.82 # Real time elapsed on the host -host_tick_rate 53016132 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134794500 # Number of ticks simulated -system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51751168 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22506445 4348.97% - 1 11357579 2194.65% - 2 5114502 988.29% - 3 3560855 688.07% - 4 2552504 493.23% - 5 1532717 296.17% - 6 1008933 194.96% - 7 796739 153.96% - 8 3320894 641.70% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 88340672 # Number of instructions committed -system.cpu.commit.COM:loads 20379399 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 35224018 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit -system.cpu.committedInsts 79591756 # Number of Instructions Simulated -system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838925 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199965 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200933 # number of replacements -system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36599689 # DTB accesses -system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36425481 # DTB hits -system.cpu.dtb.misses 174208 # DTB misses -system.cpu.dtb.read_accesses 21541288 # DTB read accesses -system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383020 # DTB read hits -system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058401 # DTB write accesses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042461 # DTB write hits -system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53041270 -system.cpu.fetch.rateDist.min_value 0 - 0 33206277 6260.46% - 1 1871594 352.86% - 2 1529415 288.34% - 3 1809626 341.17% - 4 3985239 751.35% - 5 1867239 352.04% - 6 695846 131.19% - 7 1111736 209.60% - 8 6964298 1313.00% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297366 # number of overall hits -system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88706 # number of overall misses -system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83888 # number of replacements -system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use -system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745486 # Number of branches executed -system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate -system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291392 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value -system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396987 # num instructions producing a value -system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 47898565 56.12% # Type of FU issued - IntMult 42953 0.05% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 121655 0.14% # Type of FU issued - FloatCmp 88 0.00% # Type of FU issued - FloatCvt 122104 0.14% # Type of FU issued - FloatMult 53 0.00% # Type of FU issued - FloatDiv 38535 0.05% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 21753622 25.49% # Type of FU issued - MemWrite 15368770 18.01% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 97100 9.91% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 470602 48.04% # attempts to use FU when none available - MemWrite 411938 42.05% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17563410 3311.27% - 1 13937999 2627.76% - 2 8266125 1558.43% - 3 4784809 902.09% - 4 4627568 872.45% - 5 2066740 389.65% - 6 1112374 209.72% - 7 454507 85.69% - 8 227738 42.94% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13412237 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13386072 # ITB hits -system.cpu.itb.misses 26165 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102894 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188071 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 148779 # number of replacements -system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use -system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.numCycles 54269590 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed -system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..305b9e178 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..36c3049e3 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 8039250 # Number of BTB hits +global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +global.BPredUnit.lookups 16249463 # Number of BP lookups +global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +host_inst_rate 155507 # Simulator instruction rate (inst/s) +host_mem_usage 212996 # Number of bytes of host memory used +host_seconds 511.82 # Real time elapsed on the host +host_tick_rate 53016132 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 79591756 # Number of instructions simulated +sim_seconds 0.027135 # Number of seconds simulated +sim_ticks 27134794500 # Number of ticks simulated +system.cpu.commit.COM:branches 13754477 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 51751168 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 22506445 4348.97% + 1 11357579 2194.65% + 2 5114502 988.29% + 3 3560855 688.07% + 4 2552504 493.23% + 5 1532717 296.17% + 6 1008933 194.96% + 7 796739 153.96% + 8 3320894 641.70% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 88340672 # Number of instructions committed +system.cpu.commit.COM:loads 20379399 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 35224018 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit +system.cpu.committedInsts 79591756 # Number of Instructions Simulated +system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated +system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 33838925 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1199965 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 200933 # number of replacements +system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147760 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599689 # DTB accesses +system.cpu.dtb.acv 39 # DTB access violations +system.cpu.dtb.hits 36425481 # DTB hits +system.cpu.dtb.misses 174208 # DTB misses +system.cpu.dtb.read_accesses 21541288 # DTB read accesses +system.cpu.dtb.read_acv 37 # DTB read access violations +system.cpu.dtb.read_hits 21383020 # DTB read hits +system.cpu.dtb.read_misses 158268 # DTB read misses +system.cpu.dtb.write_accesses 15058401 # DTB write accesses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_hits 15042461 # DTB write hits +system.cpu.dtb.write_misses 15940 # DTB write misses +system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched +system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 53041270 +system.cpu.fetch.rateDist.min_value 0 + 0 33206277 6260.46% + 1 1871594 352.86% + 2 1529415 288.34% + 3 1809626 341.17% + 4 3985239 751.35% + 5 1867239 352.04% + 6 695846 131.19% + 7 1111736 209.60% + 8 6964298 1313.00% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses +system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 13297366 # number of overall hits +system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses +system.cpu.icache.overall_misses 88706 # number of overall misses +system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 83888 # number of replacements +system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use +system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745486 # Number of branches executed +system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate +system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291392 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value +system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 32396987 # num instructions producing a value +system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle +system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 47898565 56.12% # Type of FU issued + IntMult 42953 0.05% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 121655 0.14% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122104 0.14% # Type of FU issued + FloatMult 53 0.00% # Type of FU issued + FloatDiv 38535 0.05% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 21753622 25.49% # Type of FU issued + MemWrite 15368770 18.01% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 97100 9.91% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 470602 48.04% # attempts to use FU when none available + MemWrite 411938 42.05% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 17563410 3311.27% + 1 13937999 2627.76% + 2 8266125 1558.43% + 3 4784809 902.09% + 4 4627568 872.45% + 5 2066740 389.65% + 6 1112374 209.72% + 7 454507 85.69% + 8 227738 42.94% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate +system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13412237 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 13386072 # ITB hits +system.cpu.itb.misses 26165 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 102894 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188071 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 148779 # number of replacements +system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.numCycles 54269590 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed +system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 305b9e178..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:27:20 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 7b2d6e4f7..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3156054 # Simulator instruction rate (inst/s) -host_mem_usage 203904 # Number of bytes of host memory used -host_seconds 27.99 # Real time elapsed on the host -host_tick_rate 1579824710 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -system.cpu.dtb.accesses 34987415 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 34890015 # DTB hits -system.cpu.dtb.misses 97400 # DTB misses -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 88442007 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 88438073 # ITB hits -system.cpu.itb.misses 3934 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..f78544a3c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..7b2d6e4f7 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3156054 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 27.99 # Real time elapsed on the host +host_tick_rate 1579824710 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.044221 # Number of seconds simulated +sim_ticks 44221003000 # Number of ticks simulated +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442007 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438073 # ITB hits +system.cpu.itb.misses 3934 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index f78544a3c..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:24:43 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 4078e993e..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1655989 # Simulator instruction rate (inst/s) -host_mem_usage 211348 # Number of bytes of host memory used -host_seconds 53.35 # Real time elapsed on the host -host_tick_rate 2533794438 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.135169 # Number of seconds simulated -sim_ticks 135168766000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679456 # number of overall hits -system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210559 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147714 # number of writebacks -system.cpu.dtb.accesses 34987415 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 34890015 # DTB hits -system.cpu.dtb.misses 97400 # DTB misses -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency -system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_misses 76436 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use -system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 88442008 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 88438074 # ITB hits -system.cpu.itb.misses 3934 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186875 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147561 # number of replacements -system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use -system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120634 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270337532 # number of cpu cycles simulated -system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..7c7d8426c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:00 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..4078e993e --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1655989 # Simulator instruction rate (inst/s) +host_mem_usage 211348 # Number of bytes of host memory used +host_seconds 53.35 # Real time elapsed on the host +host_tick_rate 2533794438 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168766000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses +system.cpu.dcache.overall_misses 210559 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147714 # number of writebacks +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency +system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses +system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 88361638 # number of overall hits +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses +system.cpu.icache.overall_misses 76436 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 74391 # number of replacements +system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use +system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442008 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438074 # ITB hits +system.cpu.itb.misses 3934 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 93905 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use +system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 120634 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 270337532 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 7c7d8426c..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:00 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 25cbdfb32..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2431097 # Simulator instruction rate (inst/s) -host_mem_usage 204768 # Number of bytes of host memory used -host_seconds 56.00 # Real time elapsed on the host -host_tick_rate 1216955986 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148678500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 136297358 # number of cpu cycles simulated -system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..06afeeef2 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,564 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026527848, 4026528248, ...) +warn: ignoring syscall time(4026527400, 1375098, ...) +warn: ignoring syscall time(4026527312, 1, ...) +warn: ignoring syscall time(4026527048, 413, ...) +warn: ignoring syscall time(4026527048, 414, ...) +warn: ignoring syscall time(4026527288, 4026527688, ...) +warn: ignoring syscall time(4026526840, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526960, 409, ...) +warn: ignoring syscall time(4026527040, 409, ...) +warn: ignoring syscall time(4026527000, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526312, 19045, ...) +warn: ignoring syscall time(4026526832, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526936, 409, ...) +warn: ignoring syscall time(4026527008, 4026527408, ...) +warn: ignoring syscall time(4026526560, 1375098, ...) +warn: ignoring syscall time(4026527184, 18732, ...) +warn: ignoring syscall time(4026526632, 409, ...) +warn: ignoring syscall time(4026526736, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527744, 225, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026527096, 4026527496, ...) +warn: ignoring syscall time(4026526648, 1375098, ...) +warn: ignoring syscall time(4026526824, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527184, 1879089152, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall time(4026527472, 1595768, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026525968, 20500, ...) +warn: ignoring syscall time(4026525968, 4026526436, ...) +warn: ignoring syscall time(4026526056, 7004192, ...) +warn: ignoring syscall time(4026527512, 4, ...) +warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..b0eadd5ad --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:47 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..25cbdfb32 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2431097 # Simulator instruction rate (inst/s) +host_mem_usage 204768 # Number of bytes of host memory used +host_seconds 56.00 # Real time elapsed on the host +host_tick_rate 1216955986 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136139203 # Number of instructions simulated +sim_seconds 0.068149 # Number of seconds simulated +sim_ticks 68148678500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 136297358 # number of cpu cycles simulated +system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index 06afeeef2..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,564 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index b0eadd5ad..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:47 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 9b35ba579..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1344201 # Simulator instruction rate (inst/s) -host_mem_usage 212228 # Number of bytes of host memory used -host_seconds 101.28 # Real time elapsed on the host -host_tick_rate 2025263348 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.205117 # Number of seconds simulated -sim_ticks 205116920000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency -system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses -system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses -system.cpu.dcache.overall_misses 154904 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107271 # number of writebacks -system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses -system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses -system.cpu.icache.overall_misses 187024 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use -system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 144925 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 120486 # number of replacements -system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use -system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 87413 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 410233840 # number of cpu cycles simulated -system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..06afeeef2 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,564 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026527848, 4026528248, ...) +warn: ignoring syscall time(4026527400, 1375098, ...) +warn: ignoring syscall time(4026527312, 1, ...) +warn: ignoring syscall time(4026527048, 413, ...) +warn: ignoring syscall time(4026527048, 414, ...) +warn: ignoring syscall time(4026527288, 4026527688, ...) +warn: ignoring syscall time(4026526840, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526960, 409, ...) +warn: ignoring syscall time(4026527040, 409, ...) +warn: ignoring syscall time(4026527000, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526312, 19045, ...) +warn: ignoring syscall time(4026526832, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526936, 409, ...) +warn: ignoring syscall time(4026527008, 4026527408, ...) +warn: ignoring syscall time(4026526560, 1375098, ...) +warn: ignoring syscall time(4026527184, 18732, ...) +warn: ignoring syscall time(4026526632, 409, ...) +warn: ignoring syscall time(4026526736, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527744, 225, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026527096, 4026527496, ...) +warn: ignoring syscall time(4026526648, 1375098, ...) +warn: ignoring syscall time(4026526824, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527184, 1879089152, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall time(4026527472, 1595768, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026525968, 20500, ...) +warn: ignoring syscall time(4026525968, 4026526436, ...) +warn: ignoring syscall time(4026526056, 7004192, ...) +warn: ignoring syscall time(4026527512, 4, ...) +warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..2b1927ccc --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:57 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..9b35ba579 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1344201 # Simulator instruction rate (inst/s) +host_mem_usage 212228 # Number of bytes of host memory used +host_seconds 101.28 # Real time elapsed on the host +host_tick_rate 2025263348 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136139203 # Number of instructions simulated +sim_seconds 0.205117 # Number of seconds simulated +sim_ticks 205116920000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses +system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 57940701 # number of overall hits +system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses +system.cpu.dcache.overall_misses 154904 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 146582 # number of replacements +system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use +system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107271 # number of writebacks +system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency +system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses +system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 136106788 # number of overall hits +system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses +system.cpu.icache.overall_misses 187024 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 184976 # number of replacements +system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use +system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 192777 # number of overall hits +system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 144925 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 120486 # number of replacements +system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use +system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 87413 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 410233840 # number of cpu cycles simulated +system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index 06afeeef2..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,564 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 2b1927ccc..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:57 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 2cba4195f..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,457 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 312845737 # Number of BTB hits -global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups -global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted -global.BPredUnit.lookups 345502589 # Number of BP lookups -global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. -host_inst_rate 178472 # Simulator instruction rate (inst/s) -host_mem_usage 202004 # Number of bytes of host memory used -host_seconds 9727.25 # Real time elapsed on the host -host_tick_rate 76312348 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.742309 # Number of seconds simulated -sim_ticks 742309425500 # Number of ticks simulated -system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1379215338 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 736540830 5340.29% - 1 260049504 1885.49% - 2 126970462 920.60% - 3 77723426 563.53% - 4 51327439 372.15% - 5 27759546 201.27% - 6 26179568 189.81% - 7 9881978 71.65% - 8 62782585 455.21% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 1819780126 # Number of instructions committed -system.cpu.commit.COM:loads 445666361 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 606571343 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency -system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses -system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 668251814 # number of overall hits -system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses -system.cpu.dcache.overall_misses 15736652 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155775 # number of replacements -system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use -system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245449 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 768331639 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 752318838 # DTB hits -system.cpu.dtb.misses 16012801 # DTB misses -system.cpu.dtb.read_accesses 566617551 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 557381525 # DTB read hits -system.cpu.dtb.read_misses 9236026 # DTB read misses -system.cpu.dtb.write_accesses 201714088 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 194937313 # DTB write hits -system.cpu.dtb.write_misses 6776775 # DTB write misses -system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched -system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1472299541 -system.cpu.fetch.rateDist.min_value 0 - 0 907273323 6162.29% - 1 47886355 325.25% - 2 34613456 235.10% - 3 52095475 353.84% - 4 125971058 855.61% - 5 69335096 470.93% - 6 50458684 342.72% - 7 40993758 278.43% - 8 143672336 975.84% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency -system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355179284 # number of overall hits -system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 1234 # number of overall misses -system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use -system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 282186314 # Number of branches executed -system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate -system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 201925301 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value -system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243717865 # num instructions producing a value -system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle -system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1532920254 66.19% # Type of FU issued - IntMult 99 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 234 0.00% # Type of FU issued - FloatCmp 20 0.00% # Type of FU issued - FloatCvt 143 0.00% # Type of FU issued - FloatMult 16 0.00% # Type of FU issued - FloatDiv 24 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 577889733 24.95% # Type of FU issued - MemWrite 205034377 8.85% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2738956 19.03% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9224843 64.09% # attempts to use FU when none available - MemWrite 2429770 16.88% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 577695763 3923.77% - 1 271543756 1844.35% - 2 242868170 1649.58% - 3 139713874 948.95% - 4 122021082 828.78% - 5 69652698 473.09% - 6 39670196 269.44% - 7 8017828 54.46% - 8 1116174 7.58% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate -system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 355180552 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 355180518 # ITB hits -system.cpu.itb.misses 34 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5387454 # number of overall hits -system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3773319 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2759426 # number of replacements -system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1195718 # number of writebacks -system.cpu.numCycles 1484618852 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..fd3c8e17c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..46c21a733 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..2cba4195f --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,457 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 312845737 # Number of BTB hits +global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups +global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted +global.BPredUnit.lookups 345502589 # Number of BP lookups +global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. +host_inst_rate 178472 # Simulator instruction rate (inst/s) +host_mem_usage 202004 # Number of bytes of host memory used +host_seconds 9727.25 # Real time elapsed on the host +host_tick_rate 76312348 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1736043781 # Number of instructions simulated +sim_seconds 0.742309 # Number of seconds simulated +sim_ticks 742309425500 # Number of ticks simulated +system.cpu.commit.COM:branches 214632552 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1379215338 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 736540830 5340.29% + 1 260049504 1885.49% + 2 126970462 920.60% + 3 77723426 563.53% + 4 51327439 372.15% + 5 27759546 201.27% + 6 26179568 189.81% + 7 9881978 71.65% + 8 62782585 455.21% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 1819780126 # Number of instructions committed +system.cpu.commit.COM:loads 445666361 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 606571343 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated +system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses +system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 668251814 # number of overall hits +system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses +system.cpu.dcache.overall_misses 15736652 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 9155775 # number of replacements +system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use +system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245449 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 768331639 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 752318838 # DTB hits +system.cpu.dtb.misses 16012801 # DTB misses +system.cpu.dtb.read_accesses 566617551 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 557381525 # DTB read hits +system.cpu.dtb.read_misses 9236026 # DTB read misses +system.cpu.dtb.write_accesses 201714088 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 194937313 # DTB write hits +system.cpu.dtb.write_misses 6776775 # DTB write misses +system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched +system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 1472299541 +system.cpu.fetch.rateDist.min_value 0 + 0 907273323 6162.29% + 1 47886355 325.25% + 2 34613456 235.10% + 3 52095475 353.84% + 4 125971058 855.61% + 5 69335096 470.93% + 6 50458684 342.72% + 7 40993758 278.43% + 8 143672336 975.84% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency +system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 355179284 # number of overall hits +system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_misses 1234 # number of overall misses +system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use +system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 282186314 # Number of branches executed +system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate +system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 201925301 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value +system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1243717865 # num instructions producing a value +system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle +system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 1532920254 66.19% # Type of FU issued + IntMult 99 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 234 0.00% # Type of FU issued + FloatCmp 20 0.00% # Type of FU issued + FloatCvt 143 0.00% # Type of FU issued + FloatMult 16 0.00% # Type of FU issued + FloatDiv 24 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 577889733 24.95% # Type of FU issued + MemWrite 205034377 8.85% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 2738956 19.03% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 9224843 64.09% # attempts to use FU when none available + MemWrite 2429770 16.88% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 577695763 3923.77% + 1 271543756 1844.35% + 2 242868170 1649.58% + 3 139713874 948.95% + 4 122021082 828.78% + 5 69652698 473.09% + 6 39670196 269.44% + 7 8017828 54.46% + 8 1116174 7.58% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate +system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 355180552 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 355180518 # ITB hits +system.cpu.itb.misses 34 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5387454 # number of overall hits +system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3773319 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2759426 # number of replacements +system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1195718 # number of writebacks +system.cpu.numCycles 1484618852 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index fd3c8e17c..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 46c21a733..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index a74bbb7e5..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3337847 # Simulator instruction rate (inst/s) -host_mem_usage 193672 # Number of bytes of host memory used -host_seconds 545.20 # Real time elapsed on the host -host_tick_rate 1674974438 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1819780127 # Number of instructions simulated -sim_seconds 0.913189 # Number of seconds simulated -sim_ticks 913189263000 # Number of ticks simulated -system.cpu.dtb.accesses 611922547 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 605324165 # DTB hits -system.cpu.dtb.misses 6598382 # DTB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 1826378527 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1826378509 # ITB hits -system.cpu.itb.misses 18 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1826378527 # number of cpu cycles simulated -system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 613169725 # Number of memory references -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..fd3c8e17c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..6c0c37f87 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..a74bbb7e5 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3337847 # Simulator instruction rate (inst/s) +host_mem_usage 193672 # Number of bytes of host memory used +host_seconds 545.20 # Real time elapsed on the host +host_tick_rate 1674974438 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1819780127 # Number of instructions simulated +sim_seconds 0.913189 # Number of seconds simulated +sim_ticks 913189263000 # Number of ticks simulated +system.cpu.dtb.accesses 611922547 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 605324165 # DTB hits +system.cpu.dtb.misses 6598382 # DTB misses +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 1826378527 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1826378509 # ITB hits +system.cpu.itb.misses 18 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1826378527 # number of cpu cycles simulated +system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.num_refs 613169725 # Number of memory references +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index fd3c8e17c..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 6c0c37f87..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 027e53548..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1294592 # Simulator instruction rate (inst/s) -host_mem_usage 201124 # Number of bytes of host memory used -host_seconds 1405.68 # Real time elapsed on the host -host_tick_rate 1940692275 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.727991 # Number of seconds simulated -sim_ticks 2727990505000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470216 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244708 # number of writebacks -system.cpu.dtb.accesses 611922547 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 605324165 # DTB hits -system.cpu.dtb.misses 6598382 # DTB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 802 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 802 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 1826378528 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1826378510 # ITB hits -system.cpu.itb.misses 18 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3764493 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2751986 # number of replacements -system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1194738 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5455981010 # number of cpu cycles simulated -system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 613169725 # Number of memory references -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..fd3c8e17c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..15467090e --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..027e53548 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1294592 # Simulator instruction rate (inst/s) +host_mem_usage 201124 # Number of bytes of host memory used +host_seconds 1405.68 # Real time elapsed on the host +host_tick_rate 1940692275 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1819780127 # Number of instructions simulated +sim_seconds 2.727991 # Number of seconds simulated +sim_ticks 2727990505000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 595853949 # number of overall hits +system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470216 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 9107638 # number of replacements +system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use +system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244708 # number of writebacks +system.cpu.dtb.accesses 611922547 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 605324165 # DTB hits +system.cpu.dtb.misses 6598382 # DTB misses +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 802 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1826377708 # number of overall hits +system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 802 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use +system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 1826378528 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1826378510 # ITB hits +system.cpu.itb.misses 18 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5348043 # number of overall hits +system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3764493 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2751986 # number of replacements +system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1194738 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5455981010 # number of cpu cycles simulated +system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.num_refs 613169725 # Number of memory references +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index fd3c8e17c..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 15467090e..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index a2bce703e..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2012716 # Simulator instruction rate (inst/s) -host_mem_usage 194900 # Number of bytes of host memory used -host_seconds 2311.91 # Real time elapsed on the host -host_tick_rate 1226349708 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 2.835211 # Number of seconds simulated -sim_ticks 2835210954000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5670421909 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed -system.cpu.num_refs 1686313781 # Number of memory references -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..bedb92044 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:38:14 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2835210954000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..a2bce703e --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2012716 # Simulator instruction rate (inst/s) +host_mem_usage 194900 # Number of bytes of host memory used +host_seconds 2311.91 # Real time elapsed on the host +host_tick_rate 1226349708 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4653219791 # Number of instructions simulated +sim_seconds 2.835211 # Number of seconds simulated +sim_ticks 2835210954000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5670421909 # number of cpu cycles simulated +system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.num_refs 1686313781 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index eae22fffc..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index bedb92044..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,30 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:38:14 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2835210954000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 5c98d4cbd..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1139442 # Simulator instruction rate (inst/s) -host_mem_usage 201800 # Number of bytes of host memory used -host_seconds 4083.77 # Real time elapsed on the host -host_tick_rate 1872105757 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 7.645253 # Number of seconds simulated -sim_ticks 7645253019000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668242528 # number of overall hits -system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470550 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9108982 # number of replacements -system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 675 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5670421196 # number of overall hits -system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 675 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use -system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5328546 # number of overall hits -system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3785207 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2772128 # number of replacements -system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1199171 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15290506038 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed -system.cpu.num_refs 1686313781 # Number of memory references -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..eae22fffc --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..c5e3246b3 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 10:43:38 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 7645253019000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..5c98d4cbd --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1139442 # Simulator instruction rate (inst/s) +host_mem_usage 201800 # Number of bytes of host memory used +host_seconds 4083.77 # Real time elapsed on the host +host_tick_rate 1872105757 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4653219791 # Number of instructions simulated +sim_seconds 7.645253 # Number of seconds simulated +sim_ticks 7645253019000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1668242528 # number of overall hits +system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470550 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 9108982 # number of replacements +system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244013 # number of writebacks +system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 675 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5670421196 # number of overall hits +system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 675 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use +system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5328546 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785207 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2772128 # number of replacements +system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199171 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 15290506038 # number of cpu cycles simulated +system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.num_refs 1686313781 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index eae22fffc..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index c5e3246b3..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,30 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 10:43:38 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 7645253019000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index bf979a603..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,448 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13008791 # Number of BTB hits -global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -global.BPredUnit.lookups 19468548 # Number of BP lookups -global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 123995 # Simulator instruction rate (inst/s) -host_mem_usage 207276 # Number of bytes of host memory used -host_seconds 678.90 # Real time elapsed on the host -host_tick_rate 60124800 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040819 # Number of seconds simulated -sim_ticks 40818658500 # Number of ticks simulated -system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73457196 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36278941 4938.79% - 1 18156304 2471.68% - 2 7455517 1014.95% - 3 3880419 528.26% - 4 2046448 278.59% - 5 1301140 177.13% - 6 721823 98.26% - 7 760802 103.57% - 8 2855802 388.77% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 91903055 # Number of instructions committed -system.cpu.commit.COM:loads 20034413 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 26537108 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit -system.cpu.committedInsts 84179709 # Number of Instructions Simulated -system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9171 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use -system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 31911121 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 31454022 # DTB hits -system.cpu.dtb.misses 457099 # DTB misses -system.cpu.dtb.read_accesses 24718123 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24262026 # DTB read hits -system.cpu.dtb.read_misses 456097 # DTB read misses -system.cpu.dtb.write_accesses 7192998 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7191996 # DTB write hits -system.cpu.dtb.write_misses 1002 # DTB write misses -system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched -system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81528343 -system.cpu.fetch.rateDist.min_value 0 - 0 50560378 6201.57% - 1 3114212 381.98% - 2 2012618 246.86% - 3 3505366 429.96% - 4 4590613 563.07% - 5 1506961 184.84% - 6 2028359 248.79% - 7 1846743 226.52% - 8 12363093 1516.42% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19218965 # number of overall hits -system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_misses 11038 # number of overall misses -system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8143 # number of replacements -system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use -system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12812003 # Number of branches executed -system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate -system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7194632 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value -system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837672 # num instructions producing a value -system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle -system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 7 0.00% # Type of FU issued - IntAlu 64430040 61.93% # Type of FU issued - IntMult 475055 0.46% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2782164 2.67% # Type of FU issued - FloatCmp 115645 0.11% # Type of FU issued - FloatCvt 2377276 2.29% # Type of FU issued - FloatMult 305748 0.29% # Type of FU issued - FloatDiv 755245 0.73% # Type of FU issued - FloatSqrt 323 0.00% # Type of FU issued - MemRead 25462424 24.48% # Type of FU issued - MemWrite 7324714 7.04% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 274346 14.19% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 31 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 6547 0.34% # attempts to use FU when none available - FloatMult 2333 0.12% # attempts to use FU when none available - FloatDiv 832912 43.09% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 743147 38.44% # attempts to use FU when none available - MemWrite 73812 3.82% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35305774 4330.49% - 1 18904885 2318.81% - 2 11574997 1419.75% - 3 6762756 829.50% - 4 5075415 622.53% - 5 2394533 293.71% - 6 1208963 148.29% - 7 250769 30.76% - 8 50251 6.16% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate -system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 19230073 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 19230003 # ITB hits -system.cpu.itb.misses 70 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5110 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81637318 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed -system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..4aef79cf1 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:52 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..bf979a603 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,448 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 13008791 # Number of BTB hits +global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted +global.BPredUnit.lookups 19468548 # Number of BP lookups +global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. +host_inst_rate 123995 # Simulator instruction rate (inst/s) +host_mem_usage 207276 # Number of bytes of host memory used +host_seconds 678.90 # Real time elapsed on the host +host_tick_rate 60124800 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 84179709 # Number of instructions simulated +sim_seconds 0.040819 # Number of seconds simulated +sim_ticks 40818658500 # Number of ticks simulated +system.cpu.commit.COM:branches 10240685 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 73457196 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 36278941 4938.79% + 1 18156304 2471.68% + 2 7455517 1014.95% + 3 3880419 528.26% + 4 2046448 278.59% + 5 1301140 177.13% + 6 721823 98.26% + 7 760802 103.57% + 8 2855802 388.77% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 91903055 # Number of instructions committed +system.cpu.commit.COM:loads 20034413 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 26537108 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit +system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated +system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 29894354 # number of overall hits +system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9171 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use +system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 105 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31911121 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 31454022 # DTB hits +system.cpu.dtb.misses 457099 # DTB misses +system.cpu.dtb.read_accesses 24718123 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 24262026 # DTB read hits +system.cpu.dtb.read_misses 456097 # DTB read misses +system.cpu.dtb.write_accesses 7192998 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 7191996 # DTB write hits +system.cpu.dtb.write_misses 1002 # DTB write misses +system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched +system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 81528343 +system.cpu.fetch.rateDist.min_value 0 + 0 50560378 6201.57% + 1 3114212 381.98% + 2 2012618 246.86% + 3 3505366 429.96% + 4 4590613 563.07% + 5 1506961 184.84% + 6 2028359 248.79% + 7 1846743 226.52% + 8 12363093 1516.42% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses +system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 19218965 # number of overall hits +system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses +system.cpu.icache.overall_misses 11038 # number of overall misses +system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 8143 # number of replacements +system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use +system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12812003 # Number of branches executed +system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate +system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7194632 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value +system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 65837672 # num instructions producing a value +system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle +system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 7 0.00% # Type of FU issued + IntAlu 64430040 61.93% # Type of FU issued + IntMult 475055 0.46% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2782164 2.67% # Type of FU issued + FloatCmp 115645 0.11% # Type of FU issued + FloatCvt 2377276 2.29% # Type of FU issued + FloatMult 305748 0.29% # Type of FU issued + FloatDiv 755245 0.73% # Type of FU issued + FloatSqrt 323 0.00% # Type of FU issued + MemRead 25462424 24.48% # Type of FU issued + MemWrite 7324714 7.04% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 274346 14.19% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 31 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 6547 0.34% # attempts to use FU when none available + FloatMult 2333 0.12% # attempts to use FU when none available + FloatDiv 832912 43.09% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 743147 38.44% # attempts to use FU when none available + MemWrite 73812 3.82% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 35305774 4330.49% + 1 18904885 2318.81% + 2 11574997 1419.75% + 3 6762756 829.50% + 4 5075415 622.53% + 5 2394533 293.71% + 6 1208963 148.29% + 7 250769 30.76% + 8 50251 6.16% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate +system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19230073 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 19230003 # ITB hits +system.cpu.itb.misses 70 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 7186 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5110 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 81637318 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed +system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 4aef79cf1..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:52 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index fd63e8611..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2797283 # Simulator instruction rate (inst/s) -host_mem_usage 198592 # Number of bytes of host memory used -host_seconds 32.85 # Real time elapsed on the host -host_tick_rate 1398634763 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951567500 # Number of ticks simulated -system.cpu.dtb.accesses 26497334 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 26497301 # DTB hits -system.cpu.dtb.misses 33 # DTB misses -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 91903136 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 91903089 # ITB hits -system.cpu.itb.misses 47 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26537141 # Number of memory references -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..17a346373 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..fd63e8611 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2797283 # Simulator instruction rate (inst/s) +host_mem_usage 198592 # Number of bytes of host memory used +host_seconds 32.85 # Real time elapsed on the host +host_tick_rate 1398634763 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 91903056 # Number of instructions simulated +sim_seconds 0.045952 # Number of seconds simulated +sim_ticks 45951567500 # Number of ticks simulated +system.cpu.dtb.accesses 26497334 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 26497301 # DTB hits +system.cpu.dtb.misses 33 # DTB misses +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 91903136 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 91903089 # ITB hits +system.cpu.itb.misses 47 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.num_refs 26537141 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 17a346373..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 3b3e2ccb7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1637033 # Simulator instruction rate (inst/s) -host_mem_usage 206044 # Number of bytes of host memory used -host_seconds 56.14 # Real time elapsed on the host -host_tick_rate 2115189911 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118747 # Number of seconds simulated -sim_ticks 118747246000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2334 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 104 # number of writebacks -system.cpu.dtb.accesses 26497334 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 26497301 # DTB hits -system.cpu.dtb.misses 33 # DTB misses -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 91903137 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 91903090 # ITB hits -system.cpu.itb.misses 47 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4791 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237494492 # number of cpu cycles simulated -system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26537141 # Number of memory references -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..a43a9ad37 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:54 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..3b3e2ccb7 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1637033 # Simulator instruction rate (inst/s) +host_mem_usage 206044 # Number of bytes of host memory used +host_seconds 56.14 # Real time elapsed on the host +host_tick_rate 2115189911 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 91903056 # Number of instructions simulated +sim_seconds 0.118747 # Number of seconds simulated +sim_ticks 118747246000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 26494967 # number of overall hits +system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2334 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.dtb.accesses 26497334 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 26497301 # DTB hits +system.cpu.dtb.misses 33 # DTB misses +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 91894580 # number of overall hits +system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_misses 8510 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 6681 # number of replacements +system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use +system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 91903137 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 91903090 # ITB hits +system.cpu.itb.misses 47 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5942 # number of overall hits +system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4791 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 237494492 # number of cpu cycles simulated +system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.num_refs 26537141 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index a43a9ad37..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:54 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 0c05fead2..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2346541 # Simulator instruction rate (inst/s) -host_mem_usage 200408 # Number of bytes of host memory used -host_seconds 82.44 # Real time elapsed on the host -host_tick_rate 1173274177 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722951500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 193445904 # number of cpu cycles simulated -system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..997da0518 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:54:24 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 96722951500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..0c05fead2 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2346541 # Simulator instruction rate (inst/s) +host_mem_usage 200408 # Number of bytes of host memory used +host_seconds 82.44 # Real time elapsed on the host +host_tick_rate 1173274177 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722951500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 997da0518..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,31 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:54:24 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96722951500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 304bdc3f9..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1229412 # Simulator instruction rate (inst/s) -host_mem_usage 207888 # Number of bytes of host memory used -host_seconds 157.35 # Real time elapsed on the host -host_tick_rate 1719613407 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270579 # Number of seconds simulated -sim_ticks 270578573000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76709909 # number of overall hits -system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1599 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses -system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193433499 # number of overall hits -system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses -system.cpu.icache.overall_misses 12288 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use -system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5173 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541157146 # number of cpu cycles simulated -system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..e76e61d8a --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 17 2008 13:45:49 +M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f +M5 commit date Sat Nov 15 23:42:11 2008 -0500 +M5 started Nov 17 2008 13:46:11 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 270578573000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..304bdc3f9 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1229412 # Simulator instruction rate (inst/s) +host_mem_usage 207888 # Number of bytes of host memory used +host_seconds 157.35 # Real time elapsed on the host +host_tick_rate 1719613407 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.270579 # Number of seconds simulated +sim_ticks 270578573000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 76709909 # number of overall hits +system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1599 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2 # number of replacements +system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency +system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 193433499 # number of overall hits +system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_misses 12288 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 10362 # number of replacements +system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use +system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 8691 # number of overall hits +system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5173 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 541157146 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index e76e61d8a..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,29 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 17 2008 13:45:49 -M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f -M5 commit date Sat Nov 15 23:42:11 2008 -0500 -M5 started Nov 17 2008 13:46:11 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 270578573000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 2581f730b..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2311586 # Simulator instruction rate (inst/s) -host_mem_usage 202280 # Number of bytes of host memory used -host_seconds 94.57 # Real time elapsed on the host -host_tick_rate 1374811015 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated -sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009373500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018748 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed -system.cpu.num_refs 77165364 # Number of memory references -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..27f336eb4 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,6 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..1d99c3015 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 6 2008 00:16:46 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 130009373500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..2581f730b --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2311586 # Simulator instruction rate (inst/s) +host_mem_usage 202280 # Number of bytes of host memory used +host_seconds 94.57 # Real time elapsed on the host +host_tick_rate 1374811015 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218595322 # Number of instructions simulated +sim_seconds 0.130009 # Number of seconds simulated +sim_ticks 130009373500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 260018748 # number of cpu cycles simulated +system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.num_refs 77165364 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index 27f336eb4..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 1d99c3015..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,31 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:16:46 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009373500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 897f4bc38..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 937563 # Simulator instruction rate (inst/s) -host_mem_usage 210412 # Number of bytes of host memory used -host_seconds 233.15 # Real time elapsed on the host -host_tick_rate 1447418160 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated -sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469714000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency -system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 77163409 # number of overall hits -system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1920 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 27 # number of replacements -system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use -system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013903 # number of overall hits -system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 4693 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 2835 # number of replacements -system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use -system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1855 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4732 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939428 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed -system.cpu.num_refs 77165364 # Number of memory references -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..27f336eb4 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,6 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..764f17d51 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 9 2008 18:23:31 +M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e +M5 commit date Sat Nov 08 21:06:07 2008 -0800 +M5 started Nov 9 2008 18:29:22 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 337469714000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..897f4bc38 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 937563 # Simulator instruction rate (inst/s) +host_mem_usage 210412 # Number of bytes of host memory used +host_seconds 233.15 # Real time elapsed on the host +host_tick_rate 1447418160 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218595322 # Number of instructions simulated +sim_seconds 0.337470 # Number of seconds simulated +sim_ticks 337469714000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 77163409 # number of overall hits +system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1920 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 27 # number of replacements +system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use +system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 260013903 # number of overall hits +system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 4693 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 2835 # number of replacements +system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use +system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1855 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4732 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 674939428 # number of cpu cycles simulated +system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.num_refs 77165364 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr b/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index 27f336eb4..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout b/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index 764f17d51..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,31 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 9 2008 18:23:31 -M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e -M5 commit date Sat Nov 08 21:06:07 2008 -0800 -M5 started Nov 9 2008 18:29:22 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469714000 because target called exit() diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt deleted file mode 100644 index fb4170969..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ /dev/null @@ -1,19 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2656730 # Simulator instruction rate (inst/s) -host_mem_usage 499828 # Number of bytes of host memory used -host_seconds 839.06 # Real time elapsed on the host -host_tick_rate 2662232 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 2229160714 # Number of instructions simulated -sim_seconds 1.116889 # Number of seconds simulated -sim_ticks 2233777512 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2233777513 # number of cpu cycles simulated -system.cpu.num_insts 2229160714 # Number of instructions executed -system.cpu.num_refs 547951940 # Number of memory references - ----------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr new file mode 100755 index 000000000..6814dd775 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -0,0 +1,15 @@ +Warning: rounding error > tolerance + 0.002000 rounded to 0 +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: No kernel set for full system simulation. Assuming you know what you're doing... +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: Sockets disabled, not accepting terminal connections +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: Sockets disabled, not accepting gdb connections +warn: Ignoring write to SPARC ERROR regsiter +warn: Ignoring write to SPARC ERROR regsiter +warn: Don't know what interrupt to clear for console. +warn: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout new file mode 100755 index 000000000..2f6efdd10 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 15:59:58 +M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e +M5 commit date Wed Nov 05 15:30:49 2008 -0500 +M5 started Nov 5 2008 16:00:22 +M5 executing on zizzer +command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +Global frequency set at 2000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt new file mode 100644 index 000000000..fb4170969 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -0,0 +1,19 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2656730 # Simulator instruction rate (inst/s) +host_mem_usage 499828 # Number of bytes of host memory used +host_seconds 839.06 # Real time elapsed on the host +host_tick_rate 2662232 # Simulator tick rate (ticks/s) +sim_freq 2000000000 # Frequency of simulated ticks +sim_insts 2229160714 # Number of instructions simulated +sim_seconds 1.116889 # Number of seconds simulated +sim_ticks 2233777512 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2233777513 # number of cpu cycles simulated +system.cpu.num_insts 2229160714 # Number of instructions executed +system.cpu.num_refs 547951940 # Number of memory references + +---------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr deleted file mode 100755 index 6814dd775..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ /dev/null @@ -1,15 +0,0 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Warning: rounding error > tolerance - 0.002000 rounded to 0 -warn: No kernel set for full system simulation. Assuming you know what you're doing... -Warning: rounding error > tolerance - 0.002000 rounded to 0 -warn: Sockets disabled, not accepting terminal connections -Warning: rounding error > tolerance - 0.002000 rounded to 0 -warn: Sockets disabled, not accepting gdb connections -warn: Ignoring write to SPARC ERROR regsiter -warn: Ignoring write to SPARC ERROR regsiter -warn: Don't know what interrupt to clear for console. -warn: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout deleted file mode 100755 index 2f6efdd10..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 15:59:58 -M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e -M5 commit date Wed Nov 05 15:30:49 2008 -0500 -M5 started Nov 5 2008 16:00:22 -M5 executing on zizzer -command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -Global frequency set at 2000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt deleted file mode 100644 index 93747295c..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,444 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 806 # Number of BTB hits -global.BPredUnit.BTBLookups 1937 # Number of BTB lookups -global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -global.BPredUnit.lookups 2263 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 7058 # Simulator instruction rate (inst/s) -host_mem_usage 199016 # Number of bytes of host memory used -host_seconds 0.90 # Real time elapsed on the host -host_tick_rate 13784618 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6386 # Number of instructions simulated -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12474500 # Number of ticks simulated -system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12416 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 9513 7661.89% - 1 1627 1310.41% - 2 488 393.04% - 3 267 215.05% - 4 153 123.23% - 5 104 83.76% - 6 96 77.32% - 7 53 42.69% - 8 115 92.62% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 6403 # Number of instructions committed -system.cpu.commit.COM:loads 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit -system.cpu.committedInsts 6386 # Number of Instructions Simulated -system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses -system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2104 # number of overall hits -system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses -system.cpu.dcache.overall_misses 554 # number of overall misses -system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use -system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2951 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2890 # DTB hits -system.cpu.dtb.misses 61 # DTB misses -system.cpu.dtb.read_accesses 1876 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1840 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1075 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1050 # DTB write hits -system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 13314 -system.cpu.fetch.rateDist.min_value 0 - 0 10844 8144.81% - 1 252 189.27% - 2 238 178.76% - 3 230 172.75% - 4 272 204.30% - 5 162 121.68% - 6 232 174.25% - 7 129 96.89% - 8 955 717.29% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses -system.cpu.icache.demand_misses 424 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1378 # number of overall hits -system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses -system.cpu.icache.overall_misses 424 # number of overall misses -system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use -system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1450 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate -system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1077 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6020 # num instructions consuming a value -system.cpu.iew.WB:count 8734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4491 # num instructions producing a value -system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle -system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6254 66.92% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1986 21.25% # Type of FU issued - MemWrite 1100 11.77% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 14 13.33% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 56 53.33% # attempts to use FU when none available - MemWrite 35 33.33% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 13314 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 9113 6844.67% - 1 1716 1288.87% - 2 1071 804.42% - 3 725 544.54% - 4 355 266.64% - 5 172 129.19% - 6 115 86.38% - 7 34 25.54% - 8 13 9.76% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate -system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1838 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1802 # ITB hits -system.cpu.itb.misses 36 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 480 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 24950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..b502697af --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 12474500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt new file mode 100644 index 000000000..93747295c --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -0,0 +1,444 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 806 # Number of BTB hits +global.BPredUnit.BTBLookups 1937 # Number of BTB lookups +global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted +global.BPredUnit.lookups 2263 # Number of BP lookups +global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +host_inst_rate 7058 # Simulator instruction rate (inst/s) +host_mem_usage 199016 # Number of bytes of host memory used +host_seconds 0.90 # Real time elapsed on the host +host_tick_rate 13784618 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 6386 # Number of instructions simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12474500 # Number of ticks simulated +system.cpu.commit.COM:branches 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 12416 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 9513 7661.89% + 1 1627 1310.41% + 2 488 393.04% + 3 267 215.05% + 4 153 123.23% + 5 104 83.76% + 6 96 77.32% + 7 53 42.69% + 8 115 92.62% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 6403 # Number of instructions committed +system.cpu.commit.COM:loads 1185 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 2050 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedInsts_total 6386 # Number of Instructions Simulated +system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses +system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2104 # number of overall hits +system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses +system.cpu.dcache.overall_misses 554 # number of overall misses +system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use +system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 2951 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 2890 # DTB hits +system.cpu.dtb.misses 61 # DTB misses +system.cpu.dtb.read_accesses 1876 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 13314 +system.cpu.fetch.rateDist.min_value 0 + 0 10844 8144.81% + 1 252 189.27% + 2 238 178.76% + 3 230 172.75% + 4 272 204.30% + 5 162 121.68% + 6 232 174.25% + 7 129 96.89% + 8 955 717.29% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses +system.cpu.icache.demand_misses 424 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1378 # number of overall hits +system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses +system.cpu.icache.overall_misses 424 # number of overall misses +system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use +system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1450 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate +system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1077 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 6020 # num instructions consuming a value +system.cpu.iew.WB:count 8734 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4491 # num instructions producing a value +system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle +system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 2 0.02% # Type of FU issued + IntAlu 6254 66.92% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1986 21.25% # Type of FU issued + MemWrite 1100 11.77% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 14 13.33% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 56 53.33% # attempts to use FU when none available + MemWrite 35 33.33% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 13314 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 9113 6844.67% + 1 1716 1288.87% + 2 1071 804.42% + 3 725 544.54% + 4 355 266.64% + 5 172 129.19% + 6 115 86.38% + 7 34 25.54% + 8 13 9.76% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate +system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1838 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1802 # ITB hits +system.cpu.itb.misses 36 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 24950 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout deleted file mode 100755 index b502697af..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 12474500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 712fc898c..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 6758 # Simulator instruction rate (inst/s) -host_mem_usage 190848 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host -host_tick_rate 3391912 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 3215000 # Number of ticks simulated -system.cpu.dtb.accesses 2060 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2050 # DTB hits -system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 6431 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 6414 # ITB hits -system.cpu.itb.misses 17 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 6431 # number of cpu cycles simulated -system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout new file mode 100755 index 000000000..9a255c446 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..712fc898c --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 6758 # Simulator instruction rate (inst/s) +host_mem_usage 190848 # Number of bytes of host memory used +host_seconds 0.95 # Real time elapsed on the host +host_tick_rate 3391912 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 3215000 # Number of ticks simulated +system.cpu.dtb.accesses 2060 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 2050 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 6431 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 6414 # ITB hits +system.cpu.itb.misses 17 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout deleted file mode 100755 index 9a255c446..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt deleted file mode 100644 index f97f1c530..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,248 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 68165 # Simulator instruction rate (inst/s) -host_mem_usage 198212 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 358563073 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33777000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use -system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 2060 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2050 # DTB hits -system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses -system.cpu.icache.demand_misses 279 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6136 # number of overall hits -system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses -system.cpu.icache.overall_misses 279 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use -system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 6432 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 6415 # ITB hits -system.cpu.itb.misses 17 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 446 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67554 # number of cpu cycles simulated -system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout new file mode 100755 index 000000000..c3d847e3f --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 33777000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt new file mode 100644 index 000000000..f97f1c530 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -0,0 +1,248 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 68165 # Simulator instruction rate (inst/s) +host_mem_usage 198212 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 358563073 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33777000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses +system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1868 # number of overall hits +system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses +system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 2060 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 2050 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency +system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 6136 # number of overall hits +system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses +system.cpu.icache.overall_misses 279 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 6432 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 6415 # ITB hits +system.cpu.itb.misses 17 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 446 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout deleted file mode 100755 index c3d847e3f..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 33777000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 12af7d1b2..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,443 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 198 # Number of BTB hits -global.BPredUnit.BTBLookups 684 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 447 # Number of conditional branches predicted -global.BPredUnit.lookups 859 # Number of BP lookups -global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 31288 # Simulator instruction rate (inst/s) -host_mem_usage 198012 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 93885607 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7183000 # Number of ticks simulated -system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6196 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5239 8455.46% - 1 263 424.47% - 2 334 539.06% - 3 134 216.27% - 4 73 117.82% - 5 63 101.68% - 6 32 51.65% - 7 20 32.28% - 8 38 61.33% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 2576 # Number of instructions committed -system.cpu.commit.COM:loads 415 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 709 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit -system.cpu.committedInsts 2387 # Number of Instructions Simulated -system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674 # number of overall hits -system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 193 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use -system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 971 # DTB accesses -system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 946 # DTB hits -system.cpu.dtb.misses 25 # DTB misses -system.cpu.dtb.read_accesses 611 # DTB read accesses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 600 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 360 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 346 # DTB write hits -system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 859 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 747 # Number of cache lines fetched -system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6528 -system.cpu.fetch.rateDist.min_value 0 - 0 5595 8570.77% - 1 36 55.15% - 2 100 153.19% - 3 69 105.70% - 4 130 199.14% - 5 72 110.29% - 6 45 68.93% - 7 48 73.53% - 8 433 663.30% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.demand_hits 512 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses -system.cpu.icache.demand_misses 235 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 512 # number of overall hits -system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses -system.cpu.icache.overall_misses 235 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use -system.cpu.icache.total_refs 512 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 584 # Number of branches executed -system.cpu.iew.EXEC:nop 286 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate -system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 360 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1896 # num instructions consuming a value -system.cpu.iew.WB:count 3311 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1509 # num instructions producing a value -system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle -system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 2506 71.31% # Type of FU issued - IntMult 1 0.03% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 639 18.18% # Type of FU issued - MemWrite 368 10.47% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5051 7737.44% - 1 569 871.63% - 2 331 507.05% - 3 253 387.56% - 4 172 263.48% - 5 97 148.59% - 6 39 59.74% - 7 11 16.85% - 8 5 7.66% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate -system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 776 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 747 # ITB hits -system.cpu.itb.misses 29 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 266 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 14367 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..28251ddf8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..e4872d461 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:52 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..12af7d1b2 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,443 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 198 # Number of BTB hits +global.BPredUnit.BTBLookups 684 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 447 # Number of conditional branches predicted +global.BPredUnit.lookups 859 # Number of BP lookups +global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +host_inst_rate 31288 # Simulator instruction rate (inst/s) +host_mem_usage 198012 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 93885607 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2387 # Number of instructions simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7183000 # Number of ticks simulated +system.cpu.commit.COM:branches 396 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6196 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 5239 8455.46% + 1 263 424.47% + 2 334 539.06% + 3 134 216.27% + 4 73 117.82% + 5 63 101.68% + 6 32 51.65% + 7 20 32.28% + 8 38 61.33% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 2576 # Number of instructions committed +system.cpu.commit.COM:loads 415 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 709 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit +system.cpu.committedInsts 2387 # Number of Instructions Simulated +system.cpu.committedInsts_total 2387 # Number of Instructions Simulated +system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses +system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 674 # number of overall hits +system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses +system.cpu.dcache.overall_misses 193 # number of overall misses +system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use +system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 971 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 946 # DTB hits +system.cpu.dtb.misses 25 # DTB misses +system.cpu.dtb.read_accesses 611 # DTB read accesses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_hits 600 # DTB read hits +system.cpu.dtb.read_misses 11 # DTB read misses +system.cpu.dtb.write_accesses 360 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 346 # DTB write hits +system.cpu.dtb.write_misses 14 # DTB write misses +system.cpu.fetch.Branches 859 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 747 # Number of cache lines fetched +system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6528 +system.cpu.fetch.rateDist.min_value 0 + 0 5595 8570.77% + 1 36 55.15% + 2 100 153.19% + 3 69 105.70% + 4 130 199.14% + 5 72 110.29% + 6 45 68.93% + 7 48 73.53% + 8 433 663.30% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.demand_hits 512 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses +system.cpu.icache.demand_misses 235 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 512 # number of overall hits +system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses +system.cpu.icache.overall_misses 235 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use +system.cpu.icache.total_refs 512 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 584 # Number of branches executed +system.cpu.iew.EXEC:nop 286 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate +system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 360 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1896 # num instructions consuming a value +system.cpu.iew.WB:count 3311 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1509 # num instructions producing a value +system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle +system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 2506 71.31% # Type of FU issued + IntMult 1 0.03% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 0 0.00% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 639 18.18% # Type of FU issued + MemWrite 368 10.47% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 1 2.94% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 11 32.35% # attempts to use FU when none available + MemWrite 22 64.71% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 5051 7737.44% + 1 569 871.63% + 2 331 507.05% + 3 253 387.56% + 4 172 263.48% + 5 97 148.59% + 6 39 59.74% + 7 11 16.85% + 8 5 7.66% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate +system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 776 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 747 # ITB hits +system.cpu.itb.misses 29 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 266 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 14367 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index 28251ddf8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index e4872d461..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:52 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 051f6dec4..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 334328 # Simulator instruction rate (inst/s) -host_mem_usage 189900 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 162370166 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1297500 # Number of ticks simulated -system.cpu.dtb.accesses 717 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 709 # DTB hits -system.cpu.dtb.misses 8 # DTB misses -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2596 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2585 # ITB hits -system.cpu.itb.misses 11 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..28251ddf8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..55a4a98f7 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..051f6dec4 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 334328 # Simulator instruction rate (inst/s) +host_mem_usage 189900 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 162370166 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2577 # Number of instructions simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 1297500 # Number of ticks simulated +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2596 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2585 # ITB hits +system.cpu.itb.misses 11 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2596 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index 28251ddf8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 55a4a98f7..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:24:43 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index af7d3609f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,247 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 59950 # Simulator instruction rate (inst/s) -host_mem_usage 197352 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 402241104 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17374000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 93 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use -system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 717 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 709 # DTB hits -system.cpu.dtb.misses 8 # DTB misses -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses -system.cpu.icache.demand_misses 163 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses -system.cpu.icache.overall_misses 163 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use -system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2597 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2586 # ITB hits -system.cpu.itb.misses 11 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 245 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34748 # number of cpu cycles simulated -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..28251ddf8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..779993228 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..af7d3609f --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,247 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 59950 # Simulator instruction rate (inst/s) +host_mem_usage 197352 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 402241104 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2577 # Number of instructions simulated +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17374000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses +system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 616 # number of overall hits +system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses +system.cpu.dcache.overall_misses 93 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use +system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses +system.cpu.icache.demand_misses 163 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2423 # number of overall hits +system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses +system.cpu.icache.overall_misses 163 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use +system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2597 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2586 # ITB hits +system.cpu.itb.misses 11 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 245 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 34748 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index 28251ddf8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 779993228..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 6c370ab2d..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,54 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 10079 # Simulator instruction rate (inst/s) -host_mem_usage 192068 # Number of bytes of host memory used -host_seconds 0.56 # Real time elapsed on the host -host_tick_rate 5037819 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2828000 # Number of ticks simulated -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout new file mode 100755 index 000000000..77c8639ab --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:37:22 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:37:50 +M5 executing on zizzer +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World! +Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..6c370ab2d --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -0,0 +1,54 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 10079 # Simulator instruction rate (inst/s) +host_mem_usage 192068 # Number of bytes of host memory used +host_seconds 0.56 # Real time elapsed on the host +host_tick_rate 5037819 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5656 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2828000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5657 # number of cpu cycles simulated +system.cpu.num_insts 5656 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout deleted file mode 100755 index 77c8639ab..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:37:22 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:37:50 -M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World! -Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt deleted file mode 100644 index d5658e44c..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,268 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 334992 # Simulator instruction rate (inst/s) -host_mem_usage 199532 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1887416058 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32322000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses -system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses -system.cpu.dcache.overall_misses 146 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use -system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use -system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 64644 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr new file mode 100755 index 000000000..5ff857a03 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout new file mode 100755 index 000000000..17fb9f581 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:37:22 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:37:51 +M5 executing on zizzer +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World! +Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt new file mode 100644 index 000000000..d5658e44c --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -0,0 +1,268 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 334992 # Simulator instruction rate (inst/s) +host_mem_usage 199532 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1887416058 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5656 # Number of instructions simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32322000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses +system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1908 # number of overall hits +system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses +system.cpu.dcache.overall_misses 146 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use +system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency +system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses +system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5355 # number of overall hits +system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses +system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 13 # number of replacements +system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use +system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 64644 # number of cpu cycles simulated +system.cpu.num_insts 5656 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr deleted file mode 100755 index 5ff857a03..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout deleted file mode 100755 index 17fb9f581..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:37:22 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:37:51 -M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World! -Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 8a19f5ea4..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 371297 # Simulator instruction rate (inst/s) -host_mem_usage 191740 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 185101425 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2701000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5403 # number of cpu cycles simulated -system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..946edd9f0 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:47 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..8a19f5ea4 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 371297 # Simulator instruction rate (inst/s) +host_mem_usage 191740 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 185101425 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2701000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 946edd9f0..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:47 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 7d5ee5db9..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,232 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 419811 # Simulator instruction rate (inst/s) -host_mem_usage 199192 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2213741040 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29031000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses -system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses -system.cpu.dcache.overall_misses 150 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use -system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses -system.cpu.icache.demand_misses 257 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses -system.cpu.icache.overall_misses 257 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use -system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 389 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 58062 # number of cpu cycles simulated -system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..92edc3116 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:19 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..7d5ee5db9 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,232 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 419811 # Simulator instruction rate (inst/s) +host_mem_usage 199192 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2213741040 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses +system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1239 # number of overall hits +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses +system.cpu.dcache.overall_misses 150 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 58062 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 92edc3116..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:19 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 3c3c458ce..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 557395 # Simulator instruction rate (inst/s) -host_mem_usage 190704 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 320851262 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5518000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11037 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed -system.cpu.num_refs 2003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..7fa8be29e --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 6 2008 00:18:22 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 5518000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..3c3c458ce --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 557395 # Simulator instruction rate (inst/s) +host_mem_usage 190704 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 320851262 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9493 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5518000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 11037 # number of cpu cycles simulated +system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index 72ba90ece..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 7fa8be29e..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:18:22 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 5518000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index cb9de2cde..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,232 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 106773 # Simulator instruction rate (inst/s) -host_mem_usage 197592 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 379942758 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33851000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses -system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1835 # number of overall hits -system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses -system.cpu.dcache.overall_misses 152 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use -system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses -system.cpu.icache.demand_misses 228 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10779 # number of overall hits -system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses -system.cpu.icache.overall_misses 228 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use -system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 360 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67702 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed -system.cpu.num_refs 2003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..9c811f04f --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:19:20 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 33851000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..cb9de2cde --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,232 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 106773 # Simulator instruction rate (inst/s) +host_mem_usage 197592 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 379942758 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9493 # Number of instructions simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33851000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses +system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1835 # number of overall hits +system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses +system.cpu.dcache.overall_misses 152 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use +system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses +system.cpu.icache.demand_misses 228 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 10779 # number of overall hits +system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses +system.cpu.icache.overall_misses 228 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use +system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 360 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 67702 # number of cpu cycles simulated +system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr b/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index 72ba90ece..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout b/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index 9c811f04f..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,17 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:19:20 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Exiting @ tick 33851000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt deleted file mode 100644 index ecc7ae363..000000000 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,753 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 916 # Number of BTB hits -global.BPredUnit.BTBLookups 4733 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted -global.BPredUnit.lookups 5548 # Number of BP lookups -global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -host_inst_rate 85524 # Simulator instruction rate (inst/s) -host_mem_usage 199540 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 95322021 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 12773 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14251500 # Number of ticks simulated -system.cpu.commit.COM:branches 2102 # Number of branches committed -system.cpu.commit.COM:branches_0 1051 # Number of branches committed -system.cpu.commit.COM:branches_1 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 22837 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16880 7391.51% - 1 3016 1320.66% - 2 1386 606.91% - 3 576 252.22% - 4 326 142.75% - 5 268 117.35% - 6 170 74.44% - 7 93 40.72% - 8 122 53.42% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 12807 # Number of instructions committed -system.cpu.commit.COM:count_0 6403 # Number of instructions committed -system.cpu.commit.COM:count_1 6404 # Number of instructions committed -system.cpu.commit.COM:loads 2370 # Number of loads committed -system.cpu.commit.COM:loads_0 1185 # Number of loads committed -system.cpu.commit.COM:loads_1 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 4100 # Number of memory references committed -system.cpu.commit.COM:refs_0 2050 # Number of memory references committed -system.cpu.commit.COM:refs_1 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6386 # Number of Instructions Simulated -system.cpu.committedInsts_1 6387 # Number of Instructions Simulated -system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction -system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4550 # number of overall hits -system.cpu.dcache.overall_hits_0 4550 # number of overall hits -system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1105 # number of overall misses -system.cpu.dcache.overall_misses_0 1105 # number of overall misses -system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.replacements_0 0 # number of replacements -system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use -system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.writebacks_0 0 # number of writebacks -system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 6300 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 6155 # DTB hits -system.cpu.dtb.misses 145 # DTB misses -system.cpu.dtb.read_accesses 4144 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 4056 # DTB read hits -system.cpu.dtb.read_misses 88 # DTB read misses -system.cpu.dtb.write_accesses 2156 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2099 # DTB write hits -system.cpu.dtb.write_misses 57 # DTB write misses -system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched -system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 22904 -system.cpu.fetch.rateDist.min_value 0 - 0 17622 7693.85% - 1 416 181.63% - 2 353 154.12% - 3 477 208.26% - 4 425 185.56% - 5 349 152.38% - 6 442 192.98% - 7 261 113.95% - 8 2559 1117.27% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3272 # number of overall hits -system.cpu.icache.overall_hits_0 3272 # number of overall hits -system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 841 # number of overall misses -system.cpu.icache.overall_misses_0 841 # number of overall misses -system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements -system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use -system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.writebacks_0 0 # number of writebacks -system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3160 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed -system.cpu.iew.EXEC:nop 135 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate -system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2175 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11901 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value -system.cpu.iew.WB:count 18426 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 9240 # num instructions producing a value -system.cpu.iew.WB:producers_0 4646 # num instructions producing a value -system.cpu.iew.WB:producers_1 4594 # num instructions producing a value -system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle -system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed -system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations -system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6830 67.10% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2173 21.35% # Type of FU issued - MemWrite 1171 11.50% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6842 67.01% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2230 21.84% # Type of FU issued - MemWrite 1134 11.11% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued -system.cpu.iq.ISSUE:FU_type.start_dist - No_OpClass 4 0.02% # Type of FU issued - IntAlu 13672 67.05% # Type of FU issued - IntMult 2 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 4 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4403 21.59% # Type of FU issued - MemWrite 2305 11.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 13 7.56% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 96 55.81% # attempts to use FU when none available - MemWrite 63 36.63% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 22904 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 14156 6180.58% - 1 3289 1435.99% - 2 2351 1026.46% - 3 1373 599.46% - 4 854 372.86% - 5 535 233.58% - 6 261 113.95% - 7 57 24.89% - 8 28 12.22% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate -system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 4162 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 4113 # ITB hits -system.cpu.itb.misses 49 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits -system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 969 # number of overall misses -system.cpu.l2cache.overall_misses_0 969 # number of overall misses -system.cpu.l2cache.overall_misses_1 0 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.replacements_0 0 # number of replacements -system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.writebacks_0 0 # number of writebacks -system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 28504 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls -system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..fc5805f9e --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..958798ce3 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:54 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Hello world! +Exiting @ tick 14251500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt new file mode 100644 index 000000000..ecc7ae363 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -0,0 +1,753 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 916 # Number of BTB hits +global.BPredUnit.BTBLookups 4733 # Number of BTB lookups +global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted +global.BPredUnit.lookups 5548 # Number of BP lookups +global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. +host_inst_rate 85524 # Simulator instruction rate (inst/s) +host_mem_usage 199540 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 95322021 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 12773 # Number of instructions simulated +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14251500 # Number of ticks simulated +system.cpu.commit.COM:branches 2102 # Number of branches committed +system.cpu.commit.COM:branches_0 1051 # Number of branches committed +system.cpu.commit.COM:branches_1 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 22837 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 16880 7391.51% + 1 3016 1320.66% + 2 1386 606.91% + 3 576 252.22% + 4 326 142.75% + 5 268 117.35% + 6 170 74.44% + 7 93 40.72% + 8 122 53.42% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 12807 # Number of instructions committed +system.cpu.commit.COM:count_0 6403 # Number of instructions committed +system.cpu.commit.COM:count_1 6404 # Number of instructions committed +system.cpu.commit.COM:loads 2370 # Number of loads committed +system.cpu.commit.COM:loads_0 1185 # Number of loads committed +system.cpu.commit.COM:loads_1 1185 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 4100 # Number of memory references committed +system.cpu.commit.COM:refs_0 2050 # Number of memory references committed +system.cpu.commit.COM:refs_1 2050 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6386 # Number of Instructions Simulated +system.cpu.committedInsts_1 6387 # Number of Instructions Simulated +system.cpu.committedInsts_total 12773 # Number of Instructions Simulated +system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction +system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 4550 # number of overall hits +system.cpu.dcache.overall_hits_0 4550 # number of overall hits +system.cpu.dcache.overall_hits_1 0 # number of overall hits +system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1105 # number of overall misses +system.cpu.dcache.overall_misses_0 1105 # number of overall misses +system.cpu.dcache.overall_misses_1 0 # number of overall misses +system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.replacements_0 0 # number of replacements +system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use +system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks_0 0 # number of writebacks +system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 6300 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 6155 # DTB hits +system.cpu.dtb.misses 145 # DTB misses +system.cpu.dtb.read_accesses 4144 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 4056 # DTB read hits +system.cpu.dtb.read_misses 88 # DTB read misses +system.cpu.dtb.write_accesses 2156 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 2099 # DTB write hits +system.cpu.dtb.write_misses 57 # DTB write misses +system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched +system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 22904 +system.cpu.fetch.rateDist.min_value 0 + 0 17622 7693.85% + 1 416 181.63% + 2 353 154.12% + 3 477 208.26% + 4 425 185.56% + 5 349 152.38% + 6 442 192.98% + 7 261 113.95% + 8 2559 1117.27% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses +system.cpu.icache.demand_misses 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 3272 # number of overall hits +system.cpu.icache.overall_hits_0 3272 # number of overall hits +system.cpu.icache.overall_hits_1 0 # number of overall hits +system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.icache.overall_misses 841 # number of overall misses +system.cpu.icache.overall_misses_0 841 # number of overall misses +system.cpu.icache.overall_misses_1 0 # number of overall misses +system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 6 # number of replacements +system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use +system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.writebacks_0 0 # number of writebacks +system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3160 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed +system.cpu.iew.EXEC:nop 135 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate +system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2175 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed +system.cpu.iew.WB:consumers 11901 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value +system.cpu.iew.WB:count 18426 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 9240 # num instructions producing a value +system.cpu.iew.WB:producers_0 4646 # num instructions producing a value +system.cpu.iew.WB:producers_1 4594 # num instructions producing a value +system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle +system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed +system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 2 0.02% # Type of FU issued + IntAlu 6830 67.10% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 2173 21.35% # Type of FU issued + MemWrite 1171 11.50% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.start_dist + No_OpClass 2 0.02% # Type of FU issued + IntAlu 6842 67.01% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 2230 21.84% # Type of FU issued + MemWrite 1134 11.11% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.end_dist +system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued +system.cpu.iq.ISSUE:FU_type.start_dist + No_OpClass 4 0.02% # Type of FU issued + IntAlu 13672 67.05% # Type of FU issued + IntMult 2 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 4 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 4403 21.59% # Type of FU issued + MemWrite 2305 11.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 13 7.56% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 96 55.81% # attempts to use FU when none available + MemWrite 63 36.63% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 22904 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 14156 6180.58% + 1 3289 1435.99% + 2 2351 1026.46% + 3 1373 599.46% + 4 854 372.86% + 5 535 233.58% + 6 261 113.95% + 7 57 24.89% + 8 28 12.22% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate +system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 4162 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 4113 # ITB hits +system.cpu.itb.misses 49 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_hits_0 2 # number of overall hits +system.cpu.l2cache.overall_hits_1 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 969 # number of overall misses +system.cpu.l2cache.overall_misses_0 969 # number of overall misses +system.cpu.l2cache.overall_misses_1 0 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.replacements_0 0 # number of replacements +system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks_0 0 # number of writebacks +system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.numCycles 28504 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr deleted file mode 100755 index fc5805f9e..000000000 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout deleted file mode 100755 index 958798ce3..000000000 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ /dev/null @@ -1,18 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:54 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello world! -Hello world! -Exiting @ tick 14251500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt deleted file mode 100644 index d80957aed..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,427 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4398 # Number of BTB hits -global.BPredUnit.BTBLookups 9844 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted -global.BPredUnit.lookups 11413 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 55497 # Simulator instruction rate (inst/s) -host_mem_usage 199732 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -host_tick_rate 106451563 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 14449 # Number of instructions simulated -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27756500 # Number of ticks simulated -system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 42766 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 34594 8089.14% - 1 4804 1123.32% - 2 1741 407.10% - 3 720 168.36% - 4 413 96.57% - 5 144 33.67% - 6 196 45.83% - 7 51 11.93% - 8 103 24.08% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 15175 # Number of instructions committed -system.cpu.commit.COM:loads 2226 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3674 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit -system.cpu.committedInsts 14449 # Number of Instructions Simulated -system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses -system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4728 # number of overall hits -system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses -system.cpu.dcache.overall_misses 558 # number of overall misses -system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use -system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched -system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 47090 -system.cpu.fetch.rateDist.min_value 0 - 0 30448 6465.92% - 1 7532 1599.49% - 2 1217 258.44% - 3 1059 224.89% - 4 1060 225.10% - 5 1193 253.34% - 6 711 150.99% - 7 327 69.44% - 8 3543 752.39% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses -system.cpu.icache.demand_misses 535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6821 # number of overall hits -system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses -system.cpu.icache.overall_misses 535 # number of overall misses -system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use -system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4842 # Number of branches executed -system.cpu.iew.EXEC:nop 2091 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate -system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2454 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 13039 # num instructions consuming a value -system.cpu.iew.WB:count 23891 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10787 # num instructions producing a value -system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle -system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 21395 73.22% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4720 16.15% # Type of FU issued - MemWrite 3105 10.63% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 40 23.12% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 20 11.56% # attempts to use FU when none available - MemWrite 113 65.32% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 47090 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 34112 7244.00% - 1 5516 1171.37% - 2 3070 651.94% - 3 2146 455.72% - 4 997 211.72% - 5 653 138.67% - 6 342 72.63% - 7 211 44.81% - 8 43 9.13% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate -system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 503 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 55514 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed -system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout new file mode 100755 index 000000000..1f6eb4b07 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -0,0 +1,27 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:55 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 27756500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt new file mode 100644 index 000000000..d80957aed --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -0,0 +1,427 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 4398 # Number of BTB hits +global.BPredUnit.BTBLookups 9844 # Number of BTB lookups +global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted +global.BPredUnit.lookups 11413 # Number of BP lookups +global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +host_inst_rate 55497 # Simulator instruction rate (inst/s) +host_mem_usage 199732 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +host_tick_rate 106451563 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 14449 # Number of instructions simulated +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27756500 # Number of ticks simulated +system.cpu.commit.COM:branches 3359 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 42766 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 34594 8089.14% + 1 4804 1123.32% + 2 1741 407.10% + 3 720 168.36% + 4 413 96.57% + 5 144 33.67% + 6 196 45.83% + 7 51 11.93% + 8 103 24.08% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 15175 # Number of instructions committed +system.cpu.commit.COM:loads 2226 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 3674 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit +system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedInsts_total 14449 # Number of Instructions Simulated +system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses +system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 4728 # number of overall hits +system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses +system.cpu.dcache.overall_misses 558 # number of overall misses +system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use +system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched +system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 47090 +system.cpu.fetch.rateDist.min_value 0 + 0 30448 6465.92% + 1 7532 1599.49% + 2 1217 258.44% + 3 1059 224.89% + 4 1060 225.10% + 5 1193 253.34% + 6 711 150.99% + 7 327 69.44% + 8 3543 752.39% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses +system.cpu.icache.demand_misses 535 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 6821 # number of overall hits +system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses +system.cpu.icache.overall_misses 535 # number of overall misses +system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use +system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4842 # Number of branches executed +system.cpu.iew.EXEC:nop 2091 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate +system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2454 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 13039 # num instructions consuming a value +system.cpu.iew.WB:count 23891 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 10787 # num instructions producing a value +system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle +system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 21395 73.22% # Type of FU issued + IntMult 0 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 0 0.00% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 4720 16.15% # Type of FU issued + MemWrite 3105 10.63% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 40 23.12% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 20 11.56% # attempts to use FU when none available + MemWrite 113 65.32% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 47090 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 34112 7244.00% + 1 5516 1171.37% + 2 3070 651.94% + 3 2146 455.72% + 4 997 211.72% + 5 653 138.67% + 6 342 72.63% + 7 211 44.81% + 8 43 9.13% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate +system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 4 # number of overall hits +system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 503 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 55514 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed +system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout deleted file mode 100755 index 1f6eb4b07..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ /dev/null @@ -1,27 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:55 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Begining test of difficult SPARC instructions... -LDSTUB: Passed -SWAP: Passed -CAS FAIL: Passed -CAS WORK: Passed -CASX FAIL: Passed -CASX WORK: Passed -LDTX: Passed -LDTW: Passed -STTW: Passed -Done -Exiting @ tick 27756500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index fa5cbc97a..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 641188 # Simulator instruction rate (inst/s) -host_mem_usage 191520 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 319099476 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 15175 # Number of instructions simulated -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7618500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15238 # number of cpu cycles simulated -system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_refs 3684 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..7103e96c6 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,27 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:56 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..fa5cbc97a --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 641188 # Simulator instruction rate (inst/s) +host_mem_usage 191520 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 319099476 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 7103e96c6..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,27 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:56 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Begining test of difficult SPARC instructions... -LDSTUB: Passed -SWAP: Passed -CAS FAIL: Passed -CAS WORK: Passed -CASX FAIL: Passed -CASX WORK: Passed -LDTX: Passed -LDTW: Passed -STTW: Passed -Done -Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index f45ffd986..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 494848 # Simulator instruction rate (inst/s) -host_mem_usage 199068 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1383502218 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 15175 # Number of instructions simulated -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 42735000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses -system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3513 # number of overall hits -system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses -system.cpu.dcache.overall_misses 155 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use -system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses -system.cpu.icache.demand_misses 280 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 14941 # number of overall hits -system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses -system.cpu.icache.overall_misses 280 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use -system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 416 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 85470 # number of cpu cycles simulated -system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_refs 3684 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..796520389 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,27 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:56 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 42735000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..f45ffd986 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 494848 # Simulator instruction rate (inst/s) +host_mem_usage 199068 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 1383502218 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 42735000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses +system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 3513 # number of overall hits +system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses +system.cpu.dcache.overall_misses 155 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use +system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency +system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_misses 280 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 14941 # number of overall hits +system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_misses 280 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use +system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 416 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 85470 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 796520389..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,27 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:56 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Begining test of difficult SPARC instructions... -LDSTUB: Passed -SWAP: Passed -CAS FAIL: Passed -CAS WORK: Passed -CASX FAIL: Passed -CASX WORK: Passed -LDTX: Passed -LDTW: Passed -STTW: Passed -Done -Exiting @ tick 42735000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt deleted file mode 100644 index 1e6af66f7..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ /dev/null @@ -1,628 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3333474 # Simulator instruction rate (inst/s) -host_mem_usage 290708 # Number of bytes of host memory used -host_seconds 18.93 # Real time elapsed on the host -host_tick_rate 98784311223 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63113507 # Number of instructions simulated -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664298 # number of overall hits -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057375 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978967 # number of replacements -system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 396793 # number of writebacks -system.cpu0.dtb.accesses 698037 # DTB accesses -system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082911 # DTB hits -system.cpu0.dtb.misses 7805 # DTB misses -system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148351 # DTB read hits -system.cpu0.dtb.read_misses 7079 # DTB read misses -system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934560 # DTB write hits -system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56304737 # number of overall hits -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884868 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884272 # number of replacements -system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858857 # ITB accesses -system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855372 # ITB hits -system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183274 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed -system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1157 -system.cpu0.kern.mode_good_user 1158 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3762 # number of times the context was actually changed -system.cpu0.kern.syscall 226 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed -system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed -system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed -system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed -system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed -system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed -system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed -system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed -system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed -system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed -system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed -system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed -system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated -system.cpu0.num_insts 57181549 # Number of instructions executed -system.cpu0.num_refs 15322361 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses -system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses -system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses -system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812118 # number of overall hits -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72152 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 62338 # number of replacements -system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30848 # number of writebacks -system.cpu1.dtb.accesses 323622 # DTB accesses -system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1914885 # DTB hits -system.cpu1.dtb.misses 3692 # DTB misses -system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_hits 1163439 # DTB read hits -system.cpu1.dtb.read_misses 3277 # DTB read misses -system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_hits 751446 # DTB write hits -system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832136 # number of overall hits -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103630 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 103091 # number of replacements -system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.itb.accesses 1469938 # ITB accesses -system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1468399 # ITB hits -system.cpu1.itb.misses 1539 # ITB misses -system.cpu1.kern.callpal 32131 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed -system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed -system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed -system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 612 -system.cpu1.kern.mode_good_user 580 -system.cpu1.kern.mode_good_idle 32 -system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches -system.cpu1.kern.mode_switch_user 580 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.kern.syscall 100 # number of syscalls executed -system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed -system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed -system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed -system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed -system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed -system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed -system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed -system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed -system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed -system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed -system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed -system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed -system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed -system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed -system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed -system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated -system.cpu1.num_insts 5931958 # Number of instructions executed -system.cpu1.num_refs 1926645 # Number of memory references -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41727 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41727 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41695 # number of replacements -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.435437 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759609 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964534 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427641 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1759609 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270778 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1759609 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270778 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056800 # number of replacements -system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use -system.l2c.total_refs 1952731 # Total number of references to valid blocks. -system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123878 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr new file mode 100755 index 000000000..d445cb942 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -0,0 +1,5 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: 97861500: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout new file mode 100755 index 000000000..a9bd0ea3f --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:23 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt new file mode 100644 index 000000000..1e6af66f7 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -0,0 +1,628 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3333474 # Simulator instruction rate (inst/s) +host_mem_usage 290708 # Number of bytes of host memory used +host_seconds 18.93 # Real time elapsed on the host +host_tick_rate 98784311223 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63113507 # Number of instructions simulated +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335522500 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 12664298 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057375 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 1978967 # number of replacements +system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 396793 # number of writebacks +system.cpu0.dtb.accesses 698037 # DTB accesses +system.cpu0.dtb.acv 251 # DTB access violations +system.cpu0.dtb.hits 15082911 # DTB hits +system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.read_accesses 508987 # DTB read accesses +system.cpu0.dtb.read_acv 152 # DTB read access violations +system.cpu0.dtb.read_hits 9148351 # DTB read hits +system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.write_accesses 189050 # DTB write accesses +system.cpu0.dtb.write_acv 99 # DTB write access violations +system.cpu0.dtb.write_hits 5934560 # DTB write hits +system.cpu0.dtb.write_misses 726 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56304737 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884868 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 884272 # number of replacements +system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858857 # ITB accesses +system.cpu0.itb.acv 127 # ITB acv +system.cpu0.itb.hits 3855372 # ITB hits +system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.kern.callpal 183274 # number of callpals executed +system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1157 +system.cpu0.kern.mode_good_user 1158 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.syscall 226 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed +system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed +system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed +system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed +system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed +system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed +system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed +system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed +system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.num_insts 57181549 # Number of instructions executed +system.cpu0.num_refs 15322361 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses +system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses +system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1812118 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 72152 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 62338 # number of replacements +system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 30848 # number of writebacks +system.cpu1.dtb.accesses 323622 # DTB accesses +system.cpu1.dtb.acv 116 # DTB access violations +system.cpu1.dtb.hits 1914885 # DTB hits +system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.read_accesses 220342 # DTB read accesses +system.cpu1.dtb.read_acv 58 # DTB read access violations +system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.write_accesses 103280 # DTB write accesses +system.cpu1.dtb.write_acv 58 # DTB write access violations +system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_misses 415 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832136 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103630 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 103091 # number of replacements +system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses +system.cpu1.itb.acv 57 # ITB acv +system.cpu1.itb.hits 1468399 # ITB hits +system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.kern.callpal 32131 # number of callpals executed +system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed +system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed +system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 +system.cpu1.kern.mode_good_user 580 +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches +system.cpu1.kern.mode_switch_user 580 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed +system.cpu1.kern.syscall 100 # number of syscalls executed +system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed +system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed +system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed +system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed +system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed +system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed +system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed +system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed +system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed +system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed +system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed +system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed +system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed +system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed +system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed +system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.num_insts 5931958 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 175 # number of ReadReq misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41695 # number of replacements +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41520 # number of writebacks +system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759609 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 964534 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses +system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427641 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 1759609 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses +system.l2c.demand_misses 1270778 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 1759609 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses +system.l2c.overall_misses 1270778 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1056800 # number of replacements +system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use +system.l2c.total_refs 1952731 # Total number of references to valid blocks. +system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123878 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr deleted file mode 100755 index d445cb942..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ /dev/null @@ -1,5 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: 97861500: Trying to launch CPU number 1! -warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout deleted file mode 100755 index a9bd0ea3f..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:23 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt deleted file mode 100644 index 8c53afda6..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ /dev/null @@ -1,406 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2786128 # Simulator instruction rate (inst/s) -host_mem_usage 289464 # Number of bytes of host memory used -host_seconds 21.53 # Real time elapsed on the host -host_tick_rate 84905818409 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995351 # Number of instructions simulated -sim_seconds 1.828356 # Number of seconds simulated -sim_ticks 1828355695500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552138 # number of overall hits -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121104 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042676 # number of replacements -system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428892 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses -system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6349968 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087131 # number of overall hits -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920058 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919431 # number of replacements -system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use -system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979228 # ITB accesses -system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974222 # ITB hits -system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192140 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1909 -system.cpu.kern.mode_good_user 1738 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1738 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656711283 # number of cpu cycles simulated -system.cpu.num_insts 59995351 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 174 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41726 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41726 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41726 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41726 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41686 # number of replacements -system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226225 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696464 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428892 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1696464 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses -system.l2c.demand_misses 1266766 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1696464 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses -system.l2c.overall_misses 1266766 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050731 # number of replacements -system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use -system.l2c.total_refs 1866797 # Total number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119150 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr new file mode 100755 index 000000000..1a557daf8 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout new file mode 100755 index 000000000..6989105c7 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:01 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt new file mode 100644 index 000000000..8c53afda6 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -0,0 +1,406 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2786128 # Simulator instruction rate (inst/s) +host_mem_usage 289464 # Number of bytes of host memory used +host_seconds 21.53 # Real time elapsed on the host +host_tick_rate 84905818409 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 59995351 # Number of instructions simulated +sim_seconds 1.828356 # Number of seconds simulated +sim_ticks 1828355695500 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 13552138 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121104 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 2042676 # number of replacements +system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 428892 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087131 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920058 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 919431 # number of replacements +system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use +system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.983588 # Percentage of idle cycles +system.cpu.itb.accesses 4979228 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 4974222 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192140 # number of callpals executed +system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1909 +system.cpu.kern.mode_good_user 1738 +system.cpu.kern.mode_good_idle 171 +system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch_user 1738 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles +system.cpu.numCycles 3656711283 # number of cpu cycles simulated +system.cpu.num_insts 59995351 # Number of instructions executed +system.cpu.num_refs 16302128 # Number of memory references +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 174 # number of ReadReq misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41726 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41726 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41726 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41726 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41686 # number of replacements +system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 1.226225 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41512 # number of writebacks +system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696464 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428892 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 1696464 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses +system.l2c.demand_misses 1266766 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 1696464 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses +system.l2c.overall_misses 1266766 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1050731 # number of replacements +system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use +system.l2c.total_refs 1866797 # Total number of references to valid blocks. +system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119150 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr deleted file mode 100755 index 1a557daf8..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout deleted file mode 100755 index 6989105c7..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:01 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt deleted file mode 100644 index 39aa94315..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ /dev/null @@ -1,735 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1388930 # Simulator instruction rate (inst/s) -host_mem_usage 287800 # Number of bytes of host memory used -host_seconds 42.75 # Real time elapsed on the host -host_tick_rate 46129218174 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59379829 # Number of instructions simulated -sim_seconds 1.972135 # Number of seconds simulated -sim_ticks 1972135479000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12909668 # number of overall hits -system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1417993 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1338626 # number of replacements -system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403562 # number of writebacks -system.cpu0.dtb.accesses 719860 # DTB accesses -system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 14696400 # DTB hits -system.cpu0.dtb.misses 8485 # DTB misses -system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8658591 # DTB read hits -system.cpu0.dtb.read_misses 7687 # DTB read misses -system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6037809 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency -system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses -system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 53208030 # number of overall hits -system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses -system.cpu0.icache.overall_misses 916222 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 915582 # number of replacements -system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles -system.cpu0.itb.accesses 3953623 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3949782 # ITB hits -system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187998 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed -system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed -system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1232 -system.cpu0.kern.mode_good_user 1233 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3869 # number of times the context was actually changed -system.cpu0.kern.syscall 224 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles -system.cpu0.numCycles 3944270958 # number of cpu cycles simulated -system.cpu0.num_insts 54115477 # Number of instructions executed -system.cpu0.num_refs 14937789 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1608374 # number of overall hits -system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 62122 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 53749 # number of replacements -system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26833 # number of writebacks -system.cpu1.dtb.accesses 302878 # DTB accesses -system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1693796 # DTB hits -system.cpu1.dtb.misses 3106 # DTB misses -system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1029675 # DTB read hits -system.cpu1.dtb.read_misses 2750 # DTB read misses -system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 664121 # DTB write hits -system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses -system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5180112 # number of overall hits -system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses -system.cpu1.icache.overall_misses 87430 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 86890 # number of replacements -system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use -system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles -system.cpu1.itb.accesses 1397499 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1396253 # ITB hits -system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29501 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed -system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed -system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 532 -system.cpu1.kern.mode_good_user 516 -system.cpu1.kern.mode_good_idle 16 -system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches -system.cpu1.kern.mode_switch_user 516 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.kern.syscall 102 # number of syscalls executed -system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles -system.cpu1.numCycles 3943367734 # number of cpu cycles simulated -system.cpu1.num_insts 5264352 # Number of instructions executed -system.cpu1.num_refs 1703685 # Number of memory references -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 178 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41730 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41730 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41730 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41730 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41698 # number of replacements -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.582076 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782800 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307447 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430395 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency -system.l2c.demand_hits 1782800 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses -system.l2c.demand_misses 614243 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782800 # number of overall hits -system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses -system.l2c.overall_misses 614243 # number of overall misses -system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 399043 # number of replacements -system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use -system.l2c.total_refs 1963771 # Total number of references to valid blocks. -system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123178 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr new file mode 100755 index 000000000..dad1cad88 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -0,0 +1,5 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: 591544000: Trying to launch CPU number 1! +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout new file mode 100755 index 000000000..06723d964 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:38:12 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt new file mode 100644 index 000000000..39aa94315 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -0,0 +1,735 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1388930 # Simulator instruction rate (inst/s) +host_mem_usage 287800 # Number of bytes of host memory used +host_seconds 42.75 # Real time elapsed on the host +host_tick_rate 46129218174 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 59379829 # Number of instructions simulated +sim_seconds 1.972135 # Number of seconds simulated +sim_ticks 1972135479000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 12909668 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417993 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 1338626 # number of replacements +system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 403562 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses +system.cpu0.dtb.acv 289 # DTB access violations +system.cpu0.dtb.hits 14696400 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 8658591 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_hits 6037809 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 53208030 # number of overall hits +system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916222 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 915582 # number of replacements +system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use +system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles +system.cpu0.itb.accesses 3953623 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 3949782 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187998 # number of callpals executed +system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1232 +system.cpu0.kern.mode_good_user 1233 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 3869 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270958 # number of cpu cycles simulated +system.cpu0.num_insts 54115477 # Number of instructions executed +system.cpu0.num_refs 14937789 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1608374 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62122 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 53749 # number of replacements +system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26833 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses +system.cpu1.dtb.acv 84 # DTB access violations +system.cpu1.dtb.hits 1693796 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 1029675 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_hits 664121 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5180112 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87430 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 86890 # number of replacements +system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.itb.accesses 1397499 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 1396253 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29501 # number of callpals executed +system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed +system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed +system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 532 +system.cpu1.kern.mode_good_user 516 +system.cpu1.kern.mode_good_idle 16 +system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches +system.cpu1.kern.mode_switch_user 516 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed +system.cpu1.kern.syscall 102 # number of syscalls executed +system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles +system.cpu1.numCycles 3943367734 # number of cpu cycles simulated +system.cpu1.num_insts 5264352 # Number of instructions executed +system.cpu1.num_refs 1703685 # Number of memory references +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41730 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41730 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41698 # number of replacements +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.582076 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41520 # number of writebacks +system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1782800 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307447 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430395 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.demand_hits 1782800 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses +system.l2c.demand_misses 614243 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1782800 # number of overall hits +system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses +system.l2c.overall_misses 614243 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 399043 # number of replacements +system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use +system.l2c.total_refs 1963771 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123178 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr deleted file mode 100755 index dad1cad88..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ /dev/null @@ -1,5 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: 591544000: Trying to launch CPU number 1! -warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout deleted file mode 100755 index 06723d964..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:12 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt deleted file mode 100644 index bcad4cd62..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ /dev/null @@ -1,474 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1283720 # Simulator instruction rate (inst/s) -host_mem_usage 286560 # Number of bytes of host memory used -host_seconds 43.75 # Real time elapsed on the host -host_tick_rate 44115985890 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56165112 # Number of instructions simulated -sim_seconds 1.930166 # Number of seconds simulated -sim_ticks 1930165791000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13569826 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1471004 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1391586 # number of replacements -system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use -system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430461 # number of writebacks -system.cpu.dtb.accesses 1020784 # DTB accesses -system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 15421361 # DTB hits -system.cpu.dtb.misses 11466 # DTB misses -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9063577 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6357784 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency -system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses -system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 55246023 # number of overall hits -system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses -system.cpu.icache.overall_misses 930923 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 930251 # number of replacements -system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use -system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929251 # Percentage of idle cycles -system.cpu.itb.accesses 4982832 # ITB accesses -system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4977822 # ITB hits -system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193204 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1910 -system.cpu.kern.mode_good_user 1743 -system.cpu.kern.mode_good_idle 167 -system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches -system.cpu.kern.mode_switch_user 1743 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4172 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles -system.cpu.numCycles 3860331582 # number of cpu cycles simulated -system.cpu.num_insts 56165112 # Number of instructions executed -system.cpu.num_refs 15669461 # Number of memory references -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41725 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41725 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41685 # number of replacements -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353410 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1710772 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307605 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430461 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency -system.l2c.demand_hits 1710772 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses -system.l2c.demand_misses 612230 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1710772 # number of overall hits -system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses -system.l2c.overall_misses 612230 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 394925 # number of replacements -system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use -system.l2c.total_refs 1889516 # Total number of references to valid blocks. -system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119047 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr new file mode 100755 index 000000000..1a557daf8 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr @@ -0,0 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout new file mode 100755 index 000000000..b4ba00cf0 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:37:43 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt new file mode 100644 index 000000000..bcad4cd62 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -0,0 +1,474 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1283720 # Simulator instruction rate (inst/s) +host_mem_usage 286560 # Number of bytes of host memory used +host_seconds 43.75 # Real time elapsed on the host +host_tick_rate 44115985890 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 56165112 # Number of instructions simulated +sim_seconds 1.930166 # Number of seconds simulated +sim_ticks 1930165791000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 13569826 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471004 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 1391586 # number of replacements +system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430461 # number of writebacks +system.cpu.dtb.accesses 1020784 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 15421361 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 9063577 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6357784 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses +system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 55246023 # number of overall hits +system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses +system.cpu.icache.overall_misses 930923 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 930251 # number of replacements +system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use +system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.929251 # Percentage of idle cycles +system.cpu.itb.accesses 4982832 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 4977822 # ITB hits +system.cpu.itb.misses 5010 # ITB misses +system.cpu.kern.callpal 193204 # number of callpals executed +system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed +system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1743 +system.cpu.kern.mode_good_idle 167 +system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches +system.cpu.kern.mode_switch_user 1743 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4172 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles +system.cpu.numCycles 3860331582 # number of cpu cycles simulated +system.cpu.num_insts 56165112 # Number of instructions executed +system.cpu.num_refs 15669461 # Number of memory references +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.iocache.replacements 41685 # number of replacements +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 1.353410 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41512 # number of writebacks +system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1710772 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307605 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430461 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.demand_hits 1710772 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses +system.l2c.demand_misses 612230 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1710772 # number of overall hits +system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses +system.l2c.overall_misses 612230 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 394925 # number of replacements +system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use +system.l2c.total_refs 1889516 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119047 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr deleted file mode 100755 index 1a557daf8..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout deleted file mode 100755 index b4ba00cf0..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:43 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt deleted file mode 100644 index 119cc8e9d..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt +++ /dev/null @@ -1,1774 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 47245 # Number of BTB hits -global.BPredUnit.BTBLookups 62226 # Number of BTB lookups -global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted -global.BPredUnit.lookups 72853 # Number of BP lookups -global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target. -host_inst_rate 90438 # Simulator instruction rate (inst/s) -host_mem_usage 148172 # Number of bytes of host memory used -host_seconds 5.53 # Real time elapsed on the host -host_tick_rate 35958 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500002 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 198813 # Number of ticks simulated -system.cpu.commit.COM:branches 61160 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 189916 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 37455 1972.19% - 1 50343 2650.80% - 2 29014 1527.73% - 3 12786 673.25% - 4 19808 1042.99% - 5 2516 132.48% - 6 10075 530.50% - 7 3395 178.76% - 8 24524 1291.31% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 518948 # Number of instructions committed -system.cpu.commit.COM:loads 131376 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 189772 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit -system.cpu.committedInsts 500002 # Number of Instructions Simulated -system.cpu.committedInsts_total 500002 # Number of Instructions Simulated -system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads -system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched -system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 198814 -system.cpu.fetch.rateDist.min_value 0 - 0 85330 4291.95% - 1 3737 187.96% - 2 9626 484.17% - 3 11018 554.19% - 4 8626 433.87% - 5 19021 956.72% - 6 27490 1382.70% - 7 6216 312.65% - 8 27750 1395.78% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.iew.EXEC:branches 65998 # Number of branches executed -system.cpu.iew.EXEC:insts 534582 # Number of executed instructions -system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed -system.cpu.iew.EXEC:nop 21827 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate -system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 60185 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 413743 # num instructions consuming a value -system.cpu.iew.WB:count 532886 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 308589 # num instructions producing a value -system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle -system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 336144 62.06% # Type of FU issued - IntMult 10 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 13 0.00% # Type of FU issued - FloatCmp 3 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 2 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 144008 26.59% # Type of FU issued - MemWrite 61441 11.34% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 6229 59.96% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 2497 24.04% # attempts to use FU when none available - MemWrite 1663 16.01% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 198814 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27333 1374.80% - 1 36906 1856.31% - 2 35716 1796.45% - 3 28916 1454.42% - 4 31868 1602.91% - 5 13027 655.24% - 6 21677 1090.32% - 7 3102 156.03% - 8 269 13.53% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate -system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.numCycles 198814 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed -system.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr new file mode 100644 index 000000000..7ded22db8 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr @@ -0,0 +1,4 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout new file mode 100644 index 000000000..ee0eb672e --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout @@ -0,0 +1,14 @@ +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 27 2006 17:25:03 +M5 started Thu Jul 27 17:25:11 2006 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed +Exiting @ tick 198813 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt new file mode 100644 index 000000000..119cc8e9d --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt @@ -0,0 +1,1774 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 47245 # Number of BTB hits +global.BPredUnit.BTBLookups 62226 # Number of BTB lookups +global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted +global.BPredUnit.lookups 72853 # Number of BP lookups +global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target. +host_inst_rate 90438 # Simulator instruction rate (inst/s) +host_mem_usage 148172 # Number of bytes of host memory used +host_seconds 5.53 # Real time elapsed on the host +host_tick_rate 35958 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500002 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 198813 # Number of ticks simulated +system.cpu.commit.COM:branches 61160 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 189916 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 37455 1972.19% + 1 50343 2650.80% + 2 29014 1527.73% + 3 12786 673.25% + 4 19808 1042.99% + 5 2516 132.48% + 6 10075 530.50% + 7 3395 178.76% + 8 24524 1291.31% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 518948 # Number of instructions committed +system.cpu.commit.COM:loads 131376 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 189772 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit +system.cpu.committedInsts 500002 # Number of Instructions Simulated +system.cpu.committedInsts_total 500002 # Number of Instructions Simulated +system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads +system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched +system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 198814 +system.cpu.fetch.rateDist.min_value 0 + 0 85330 4291.95% + 1 3737 187.96% + 2 9626 484.17% + 3 11018 554.19% + 4 8626 433.87% + 5 19021 956.72% + 6 27490 1382.70% + 7 6216 312.65% + 8 27750 1395.78% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.iew.EXEC:branches 65998 # Number of branches executed +system.cpu.iew.EXEC:insts 534582 # Number of executed instructions +system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed +system.cpu.iew.EXEC:nop 21827 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate +system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 60185 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 413743 # num instructions consuming a value +system.cpu.iew.WB:count 532886 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 308589 # num instructions producing a value +system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle +system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 0 0.00% # Type of FU issued + IntAlu 336144 62.06% # Type of FU issued + IntMult 10 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 13 0.00% # Type of FU issued + FloatCmp 3 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 2 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 144008 26.59% # Type of FU issued + MemWrite 61441 11.34% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 6229 59.96% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 2497 24.04% # attempts to use FU when none available + MemWrite 1663 16.01% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 198814 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 27333 1374.80% + 1 36906 1856.31% + 2 35716 1796.45% + 3 28916 1454.42% + 4 31868 1602.91% + 5 13027 655.24% + 6 21677 1090.32% + 7 3102 156.03% + 8 269 13.53% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate +system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.numCycles 198814 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed +system.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr deleted file mode 100644 index 7ded22db8..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 - -gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout deleted file mode 100644 index ee0eb672e..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout +++ /dev/null @@ -1,14 +0,0 @@ -main dictionary has 1245 entries -49508 bytes wasted ->M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Jul 27 2006 17:25:03 -M5 started Thu Jul 27 17:25:11 2006 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed -Exiting @ tick 198813 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt deleted file mode 100644 index 51d5de7dc..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 4911987 # Simulator instruction rate (inst/s) -host_mem_usage 189996 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 2448419888 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -system.cpu.dtb.accesses 180793 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 180775 # DTB hits -system.cpu.dtb.misses 18 # DTB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 500032 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 500019 # ITB hits -system.cpu.itb.misses 13 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 182222 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr new file mode 100755 index 000000000..a1d152694 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout new file mode 100755 index 000000000..539afef68 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt new file mode 100644 index 000000000..51d5de7dc --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 4911987 # Simulator instruction rate (inst/s) +host_mem_usage 189996 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 2448419888 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500001 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu.dtb.accesses 180793 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 180775 # DTB hits +system.cpu.dtb.misses 18 # DTB misses +system.cpu.dtb.read_accesses 124443 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 124435 # DTB read hits +system.cpu.dtb.read_misses 8 # DTB read misses +system.cpu.dtb.write_accesses 56350 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 56340 # DTB write hits +system.cpu.dtb.write_misses 10 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 500032 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 500019 # ITB hits +system.cpu.itb.misses 13 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 500032 # number of cpu cycles simulated +system.cpu.num_insts 500001 # Number of instructions executed +system.cpu.num_refs 182222 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr deleted file mode 100755 index a1d152694..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here - -gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout deleted file mode 100755 index 539afef68..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ /dev/null @@ -1,18 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:27:20 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt deleted file mode 100644 index 041421492..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ /dev/null @@ -1,247 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 883179 # Simulator instruction rate (inst/s) -host_mem_usage 197372 # Number of bytes of host memory used -host_seconds 0.57 # Real time elapsed on the host -host_tick_rate 1301859777 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000737 # Number of seconds simulated -sim_ticks 737389000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses -system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180149 # number of overall hits -system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses -system.cpu.dcache.overall_misses 626 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use -system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 180793 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 180775 # DTB hits -system.cpu.dtb.misses 18 # DTB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses -system.cpu.icache.demand_misses 403 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 499617 # number of overall hits -system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses -system.cpu.icache.overall_misses 403 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use -system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 500033 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 500020 # ITB hits -system.cpu.itb.misses 13 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 857 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1474778 # number of cpu cycles simulated -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 182222 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr new file mode 100755 index 000000000..a1d152694 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout new file mode 100755 index 000000000..337a3a052 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 737389000 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt new file mode 100644 index 000000000..041421492 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -0,0 +1,247 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 883179 # Simulator instruction rate (inst/s) +host_mem_usage 197372 # Number of bytes of host memory used +host_seconds 0.57 # Real time elapsed on the host +host_tick_rate 1301859777 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500001 # Number of instructions simulated +sim_seconds 0.000737 # Number of seconds simulated +sim_ticks 737389000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses +system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 180149 # number of overall hits +system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses +system.cpu.dcache.overall_misses 626 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use +system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 180793 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 180775 # DTB hits +system.cpu.dtb.misses 18 # DTB misses +system.cpu.dtb.read_accesses 124443 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 124435 # DTB read hits +system.cpu.dtb.read_misses 8 # DTB read misses +system.cpu.dtb.write_accesses 56350 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 56340 # DTB write hits +system.cpu.dtb.write_misses 10 # DTB write misses +system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses +system.cpu.icache.demand_misses 403 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 499617 # number of overall hits +system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses +system.cpu.icache.overall_misses 403 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use +system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 500033 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 500020 # ITB hits +system.cpu.itb.misses 13 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 857 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1474778 # number of cpu cycles simulated +system.cpu.num_insts 500001 # Number of instructions executed +system.cpu.num_refs 182222 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr deleted file mode 100755 index a1d152694..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here - -gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout deleted file mode 100755 index 337a3a052..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ /dev/null @@ -1,18 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 737389000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt deleted file mode 100644 index 12655b8fd..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt +++ /dev/null @@ -1,628 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2958551 # Simulator instruction rate (inst/s) -host_mem_usage 1121980 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host -host_tick_rate 369689554 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2000004 # Number of instructions simulated -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180140 # number of overall hits -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 635 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.accesses 180793 # DTB accesses -system.cpu0.dtb.acv 0 # DTB access violations -system.cpu0.dtb.hits 180775 # DTB hits -system.cpu0.dtb.misses 18 # DTB misses -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 499556 # number of overall hits -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_misses 463 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.itb.accesses 500032 # ITB accesses -system.cpu0.itb.acv 0 # ITB acv -system.cpu0.itb.hits 500019 # ITB hits -system.cpu0.itb.misses 13 # ITB misses -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 500032 # number of cpu cycles simulated -system.cpu0.num_insts 500001 # Number of instructions executed -system.cpu0.num_refs 182222 # Number of memory references -system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180140 # number of overall hits -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 635 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.accesses 180793 # DTB accesses -system.cpu1.dtb.acv 0 # DTB access violations -system.cpu1.dtb.hits 180775 # DTB hits -system.cpu1.dtb.misses 18 # DTB misses -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.write_accesses 56350 # DTB write accesses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_hits 56340 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499556 # number of overall hits -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_misses 463 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.itb.accesses 500032 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 500019 # ITB hits -system.cpu1.itb.misses 13 # ITB misses -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.numCycles 500032 # number of cpu cycles simulated -system.cpu1.num_insts 500001 # Number of instructions executed -system.cpu1.num_refs 182222 # Number of memory references -system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180140 # number of overall hits -system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 635 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.accesses 180793 # DTB accesses -system.cpu2.dtb.acv 0 # DTB access violations -system.cpu2.dtb.hits 180775 # DTB hits -system.cpu2.dtb.misses 18 # DTB misses -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.write_accesses 56350 # DTB write accesses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_hits 56340 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499556 # number of overall hits -system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_misses 463 # number of overall misses -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.itb.accesses 500032 # ITB accesses -system.cpu2.itb.acv 0 # ITB acv -system.cpu2.itb.hits 500019 # ITB hits -system.cpu2.itb.misses 13 # ITB misses -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 500032 # number of cpu cycles simulated -system.cpu2.num_insts 500001 # Number of instructions executed -system.cpu2.num_refs 182222 # Number of memory references -system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180140 # number of overall hits -system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 635 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.accesses 180793 # DTB accesses -system.cpu3.dtb.acv 0 # DTB access violations -system.cpu3.dtb.hits 180775 # DTB hits -system.cpu3.dtb.misses 18 # DTB misses -system.cpu3.dtb.read_accesses 124443 # DTB read accesses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124435 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.write_accesses 56350 # DTB write accesses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_hits 56340 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499556 # number of overall hits -system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_misses 463 # number of overall misses -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.itb.accesses 500032 # ITB accesses -system.cpu3.itb.acv 0 # ITB acv -system.cpu3.itb.hits 500019 # ITB hits -system.cpu3.itb.misses 13 # ITB misses -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.numCycles 500032 # number of cpu cycles simulated -system.cpu3.num_insts 500001 # Number of instructions executed -system.cpu3.num_refs 182222 # Number of memory references -system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 556 # number of ReadExReq misses -system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 276 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 2872 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses -system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 116 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 276 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses -system.l2c.demand_misses 3428 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 276 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses -system.l2c.overall_misses 3428 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use -system.l2c.total_refs 276 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr new file mode 100755 index 000000000..496a7244f --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -0,0 +1,10 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout new file mode 100755 index 000000000..b1dd747a5 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt new file mode 100644 index 000000000..12655b8fd --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -0,0 +1,628 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2958551 # Simulator instruction rate (inst/s) +host_mem_usage 1121980 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 369689554 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2000004 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180793 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180775 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124435 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56340 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499556 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500032 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500019 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 182222 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180140 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180793 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180775 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124435 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56350 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56340 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499556 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500032 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 500019 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.num_insts 500001 # Number of instructions executed +system.cpu1.num_refs 182222 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499556 # number of overall hits +system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500032 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500019 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180140 # number of overall hits +system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180793 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180775 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124443 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124435 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56350 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56340 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499556 # number of overall hits +system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500032 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500019 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.num_insts 500001 # Number of instructions executed +system.cpu3.num_refs 182222 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr deleted file mode 100755 index 496a7244f..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr +++ /dev/null @@ -1,10 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout deleted file mode 100755 index b1dd747a5..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout +++ /dev/null @@ -1,24 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt deleted file mode 100644 index 5dc3a25b6..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt +++ /dev/null @@ -1,718 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1370296 # Simulator instruction rate (inst/s) -host_mem_usage 204468 # Number of bytes of host memory used -host_seconds 1.46 # Real time elapsed on the host -host_tick_rate 505820394 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1999941 # Number of instructions simulated -sim_seconds 0.000738 # Number of seconds simulated -sim_ticks 738387000 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180136 # number of overall hits -system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 635 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.accesses 180789 # DTB accesses -system.cpu0.dtb.acv 0 # DTB access violations -system.cpu0.dtb.hits 180771 # DTB hits -system.cpu0.dtb.misses 18 # DTB misses -system.cpu0.dtb.read_accesses 124440 # DTB read accesses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_hits 124432 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.write_accesses 56349 # DTB write accesses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_hits 56339 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency -system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 499537 # number of overall hits -system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_misses 463 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use -system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.itb.accesses 500013 # ITB accesses -system.cpu0.itb.acv 0 # ITB acv -system.cpu0.itb.hits 500000 # ITB hits -system.cpu0.itb.misses 13 # ITB misses -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 1476774 # number of cpu cycles simulated -system.cpu0.num_insts 499981 # Number of instructions executed -system.cpu0.num_refs 182218 # Number of memory references -system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180133 # number of overall hits -system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 635 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.accesses 180786 # DTB accesses -system.cpu1.dtb.acv 0 # DTB access violations -system.cpu1.dtb.hits 180768 # DTB hits -system.cpu1.dtb.misses 18 # DTB misses -system.cpu1.dtb.read_accesses 124437 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124429 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.write_accesses 56349 # DTB write accesses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_hits 56339 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency -system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499531 # number of overall hits -system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_misses 463 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use -system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.itb.accesses 500007 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 499994 # ITB hits -system.cpu1.itb.misses 13 # ITB misses -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.numCycles 1476774 # number of cpu cycles simulated -system.cpu1.num_insts 499975 # Number of instructions executed -system.cpu1.num_refs 182214 # Number of memory references -system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180140 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 635 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.accesses 180793 # DTB accesses -system.cpu2.dtb.acv 0 # DTB access violations -system.cpu2.dtb.hits 180775 # DTB hits -system.cpu2.dtb.misses 18 # DTB misses -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.write_accesses 56350 # DTB write accesses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_hits 56340 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency -system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499557 # number of overall hits -system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_misses 463 # number of overall misses -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use -system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.itb.accesses 500033 # ITB accesses -system.cpu2.itb.acv 0 # ITB acv -system.cpu2.itb.hits 500020 # ITB hits -system.cpu2.itb.misses 13 # ITB misses -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 1476774 # number of cpu cycles simulated -system.cpu2.num_insts 500001 # Number of instructions executed -system.cpu2.num_refs 182222 # Number of memory references -system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180137 # number of overall hits -system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 635 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.accesses 180790 # DTB accesses -system.cpu3.dtb.acv 0 # DTB access violations -system.cpu3.dtb.hits 180772 # DTB hits -system.cpu3.dtb.misses 18 # DTB misses -system.cpu3.dtb.read_accesses 124441 # DTB read accesses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124433 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.write_accesses 56349 # DTB write accesses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_hits 56339 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency -system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499540 # number of overall hits -system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_misses 463 # number of overall misses -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use -system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.itb.accesses 500016 # ITB accesses -system.cpu3.itb.acv 0 # ITB acv -system.cpu3.itb.hits 500003 # ITB hits -system.cpu3.itb.misses 13 # ITB misses -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.numCycles 1476774 # number of cpu cycles simulated -system.cpu3.num_insts 499984 # Number of instructions executed -system.cpu3.num_refs 182219 # Number of memory references -system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 556 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 276 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 2872 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 116 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency -system.l2c.demand_hits 276 # number of demand (read+write) hits -system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses -system.l2c.demand_misses 3428 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 276 # number of overall hits -system.l2c.overall_miss_latency 178284000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses -system.l2c.overall_misses 3428 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use -system.l2c.total_refs 276 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr new file mode 100755 index 000000000..496a7244f --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -0,0 +1,10 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout new file mode 100755 index 000000000..edbace7b2 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:30:50 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 738387000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt new file mode 100644 index 000000000..5dc3a25b6 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -0,0 +1,718 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1370296 # Simulator instruction rate (inst/s) +host_mem_usage 204468 # Number of bytes of host memory used +host_seconds 1.46 # Real time elapsed on the host +host_tick_rate 505820394 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1999941 # Number of instructions simulated +sim_seconds 0.000738 # Number of seconds simulated +sim_ticks 738387000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180136 # number of overall hits +system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180789 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180771 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124440 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124432 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56349 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56339 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499537 # number of overall hits +system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use +system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500013 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500000 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 1476774 # number of cpu cycles simulated +system.cpu0.num_insts 499981 # Number of instructions executed +system.cpu0.num_refs 182218 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180133 # number of overall hits +system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180786 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180768 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124437 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124429 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56349 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56339 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499531 # number of overall hits +system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use +system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500007 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 499994 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 1476774 # number of cpu cycles simulated +system.cpu1.num_insts 499975 # Number of instructions executed +system.cpu1.num_refs 182214 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499557 # number of overall hits +system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500033 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500020 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 1476774 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180137 # number of overall hits +system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180790 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180772 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124441 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124433 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56349 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56339 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499540 # number of overall hits +system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use +system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500016 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500003 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 1476774 # number of cpu cycles simulated +system.cpu3.num_insts 499984 # Number of instructions executed +system.cpu3.num_refs 182219 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 178284000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr deleted file mode 100755 index 496a7244f..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr +++ /dev/null @@ -1,10 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout deleted file mode 100755 index edbace7b2..000000000 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout +++ /dev/null @@ -1,24 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:30:50 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 738387000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt deleted file mode 100644 index 07a437af0..000000000 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ /dev/null @@ -1,731 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_mem_usage 324480 # Number of bytes of host memory used -host_seconds 257.27 # Real time elapsed on the host -host_tick_rate 1045249 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268915439 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked -system.cpu0.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked -system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses -system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses -system.cpu0.l1c.fast_writes 0 # number of fast writes performed -system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8674 # number of overall hits -system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60767 # number of overall misses -system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 28158 # number of replacements -system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. -system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. -system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11054 # number of writebacks -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99578 # number of read accesses completed -system.cpu0.num_writes 53795 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked -system.cpu1.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked -system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses -system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses -system.cpu1.l1c.fast_writes 0 # number of fast writes performed -system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8551 # number of overall hits -system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60450 # number of overall misses -system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27563 # number of replacements -system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. -system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. -system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10923 # number of writebacks -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99680 # number of read accesses completed -system.cpu1.num_writes 54175 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked -system.cpu2.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked -system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses -system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses -system.cpu2.l1c.fast_writes 0 # number of fast writes performed -system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8437 # number of overall hits -system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60562 # number of overall misses -system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27725 # number of replacements -system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. -system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. -system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10868 # number of writebacks -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99153 # number of read accesses completed -system.cpu2.num_writes 52976 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked -system.cpu3.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked -system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses -system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses -system.cpu3.l1c.fast_writes 0 # number of fast writes performed -system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8535 # number of overall hits -system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60533 # number of overall misses -system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 27562 # number of replacements -system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. -system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. -system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10850 # number of writebacks -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99282 # number of read accesses completed -system.cpu3.num_writes 53764 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked -system.cpu4.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked -system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses -system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses -system.cpu4.l1c.fast_writes 0 # number of fast writes performed -system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8435 # number of overall hits -system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60418 # number of overall misses -system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 27721 # number of replacements -system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. -system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. -system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10846 # number of writebacks -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99301 # number of read accesses completed -system.cpu4.num_writes 53586 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked -system.cpu5.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked -system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses -system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses -system.cpu5.l1c.fast_writes 0 # number of fast writes performed -system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8362 # number of overall hits -system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60470 # number of overall misses -system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 27632 # number of replacements -system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. -system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. -system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10950 # number of writebacks -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99024 # number of read accesses completed -system.cpu5.num_writes 53903 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked -system.cpu6.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked -system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses -system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses -system.cpu6.l1c.fast_writes 0 # number of fast writes performed -system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8396 # number of overall hits -system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60973 # number of overall misses -system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 28139 # number of replacements -system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. -system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. -system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11130 # number of writebacks -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 54239 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked -system.cpu7.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked -system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses -system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses -system.cpu7.l1c.fast_writes 0 # number of fast writes performed -system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8481 # number of overall hits -system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60440 # number of overall misses -system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27627 # number of replacements -system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. -system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. -system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10984 # number of writebacks -system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99634 # number of read accesses completed -system.cpu7.num_writes 53744 # number of write accesses completed -system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 89906 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 48016 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 86929 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 213064 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency -system.l2c.demand_hits 89906 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses -system.l2c.demand_misses 123158 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 213064 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 89906 # number of overall hits -system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles -system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses -system.l2c.overall_misses 123158 # number of overall misses -system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 73303 # number of replacements -system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.737828 # Cycle average of tags in use -system.l2c.total_refs 148204 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 47216 # number of writebacks - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr new file mode 100755 index 000000000..507652626 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -0,0 +1,74 @@ +system.cpu3: completed 10000 read accesses @26226880 +system.cpu6: completed 10000 read accesses @26416342 +system.cpu2: completed 10000 read accesses @26427251 +system.cpu5: completed 10000 read accesses @26798889 +system.cpu0: completed 10000 read accesses @26886521 +system.cpu7: completed 10000 read accesses @27109446 +system.cpu1: completed 10000 read accesses @27197408 +system.cpu4: completed 10000 read accesses @27318359 +system.cpu3: completed 20000 read accesses @53279230 +system.cpu6: completed 20000 read accesses @53417084 +system.cpu2: completed 20000 read accesses @53757092 +system.cpu0: completed 20000 read accesses @53888320 +system.cpu5: completed 20000 read accesses @53947132 +system.cpu4: completed 20000 read accesses @54390092 +system.cpu1: completed 20000 read accesses @54397720 +system.cpu7: completed 20000 read accesses @54632966 +system.cpu6: completed 30000 read accesses @80144176 +system.cpu3: completed 30000 read accesses @80518264 +system.cpu0: completed 30000 read accesses @80638600 +system.cpu5: completed 30000 read accesses @80869702 +system.cpu1: completed 30000 read accesses @81289158 +system.cpu2: completed 30000 read accesses @81358716 +system.cpu7: completed 30000 read accesses @81981296 +system.cpu4: completed 30000 read accesses @82043104 +system.cpu6: completed 40000 read accesses @107087547 +system.cpu0: completed 40000 read accesses @107662142 +system.cpu3: completed 40000 read accesses @107722516 +system.cpu5: completed 40000 read accesses @107884124 +system.cpu1: completed 40000 read accesses @107981413 +system.cpu7: completed 40000 read accesses @108415286 +system.cpu2: completed 40000 read accesses @108655120 +system.cpu4: completed 40000 read accesses @109427858 +system.cpu6: completed 50000 read accesses @133583246 +system.cpu0: completed 50000 read accesses @133832383 +system.cpu5: completed 50000 read accesses @134755386 +system.cpu1: completed 50000 read accesses @134792594 +system.cpu7: completed 50000 read accesses @134914312 +system.cpu3: completed 50000 read accesses @134993978 +system.cpu2: completed 50000 read accesses @135362549 +system.cpu4: completed 50000 read accesses @135394370 +system.cpu0: completed 60000 read accesses @160410176 +system.cpu6: completed 60000 read accesses @160667590 +system.cpu7: completed 60000 read accesses @161466346 +system.cpu1: completed 60000 read accesses @161592434 +system.cpu5: completed 60000 read accesses @161656374 +system.cpu4: completed 60000 read accesses @161882626 +system.cpu2: completed 60000 read accesses @162062631 +system.cpu3: completed 60000 read accesses @162154299 +system.cpu6: completed 70000 read accesses @187592265 +system.cpu1: completed 70000 read accesses @188138542 +system.cpu7: completed 70000 read accesses @188373105 +system.cpu0: completed 70000 read accesses @188690782 +system.cpu3: completed 70000 read accesses @189309687 +system.cpu2: completed 70000 read accesses @189360790 +system.cpu4: completed 70000 read accesses @189391126 +system.cpu5: completed 70000 read accesses @189902895 +system.cpu6: completed 80000 read accesses @214739574 +system.cpu1: completed 80000 read accesses @215665444 +system.cpu0: completed 80000 read accesses @216021457 +system.cpu7: completed 80000 read accesses @216394344 +system.cpu3: completed 80000 read accesses @216537382 +system.cpu4: completed 80000 read accesses @216775798 +system.cpu2: completed 80000 read accesses @216868662 +system.cpu5: completed 80000 read accesses @217401619 +system.cpu6: completed 90000 read accesses @241415090 +system.cpu1: completed 90000 read accesses @242558992 +system.cpu0: completed 90000 read accesses @242897388 +system.cpu7: completed 90000 read accesses @243372191 +system.cpu3: completed 90000 read accesses @243630762 +system.cpu5: completed 90000 read accesses @243633950 +system.cpu4: completed 90000 read accesses @243710816 +system.cpu2: completed 90000 read accesses @243974160 +system.cpu6: completed 100000 read accesses @268915439 +warn: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout new file mode 100755 index 000000000..a9b5dbd1a --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt new file mode 100644 index 000000000..07a437af0 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -0,0 +1,731 @@ + +---------- Begin Simulation Statistics ---------- +host_mem_usage 324480 # Number of bytes of host memory used +host_seconds 257.27 # Real time elapsed on the host +host_tick_rate 1045249 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_seconds 0.000269 # Number of seconds simulated +sim_ticks 268915439 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked +system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.cache_copies 0 # number of cache copies performed +system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses +system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses +system.cpu0.l1c.fast_writes 0 # number of fast writes performed +system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.l1c.overall_hits 8674 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60767 # number of overall misses +system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l1c.replacements 28158 # number of replacements +system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. +system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. +system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.writebacks 11054 # number of writebacks +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.num_reads 99578 # number of read accesses completed +system.cpu0.num_writes 53795 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked +system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.cache_copies 0 # number of cache copies performed +system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses +system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses +system.cpu1.l1c.fast_writes 0 # number of fast writes performed +system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.l1c.overall_hits 8551 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60450 # number of overall misses +system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l1c.replacements 27563 # number of replacements +system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. +system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. +system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.writebacks 10923 # number of writebacks +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99680 # number of read accesses completed +system.cpu1.num_writes 54175 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked +system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.cache_copies 0 # number of cache copies performed +system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses +system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses +system.cpu2.l1c.fast_writes 0 # number of fast writes performed +system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu2.l1c.overall_hits 8437 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60562 # number of overall misses +system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.l1c.replacements 27725 # number of replacements +system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. +system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. +system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.writebacks 10868 # number of writebacks +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99153 # number of read accesses completed +system.cpu2.num_writes 52976 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked +system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.cache_copies 0 # number of cache copies performed +system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses +system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses +system.cpu3.l1c.fast_writes 0 # number of fast writes performed +system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu3.l1c.overall_hits 8535 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60533 # number of overall misses +system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.l1c.replacements 27562 # number of replacements +system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. +system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. +system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.writebacks 10850 # number of writebacks +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99282 # number of read accesses completed +system.cpu3.num_writes 53764 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked +system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.cache_copies 0 # number of cache copies performed +system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses +system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses +system.cpu4.l1c.fast_writes 0 # number of fast writes performed +system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu4.l1c.overall_hits 8435 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60418 # number of overall misses +system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu4.l1c.replacements 27721 # number of replacements +system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. +system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. +system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.writebacks 10846 # number of writebacks +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99301 # number of read accesses completed +system.cpu4.num_writes 53586 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked +system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.cache_copies 0 # number of cache copies performed +system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses +system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses +system.cpu5.l1c.fast_writes 0 # number of fast writes performed +system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu5.l1c.overall_hits 8362 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60470 # number of overall misses +system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu5.l1c.replacements 27632 # number of replacements +system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. +system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. +system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.writebacks 10950 # number of writebacks +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99024 # number of read accesses completed +system.cpu5.num_writes 53903 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked +system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.cache_copies 0 # number of cache copies performed +system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses +system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses +system.cpu6.l1c.fast_writes 0 # number of fast writes performed +system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu6.l1c.overall_hits 8396 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60973 # number of overall misses +system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu6.l1c.replacements 28139 # number of replacements +system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. +system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. +system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.writebacks 11130 # number of writebacks +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 54239 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked +system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.cache_copies 0 # number of cache copies performed +system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses +system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses +system.cpu7.l1c.fast_writes 0 # number of fast writes performed +system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu7.l1c.overall_hits 8481 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60440 # number of overall misses +system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu7.l1c.replacements 27627 # number of replacements +system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. +system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. +system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.writebacks 10984 # number of writebacks +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99634 # number of read accesses completed +system.cpu7.num_writes 53744 # number of write accesses completed +system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 89906 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 48016 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 86929 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 213064 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.demand_hits 89906 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses +system.l2c.demand_misses 123158 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 213064 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 89906 # number of overall hits +system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles +system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses +system.l2c.overall_misses 123158 # number of overall misses +system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 73303 # number of replacements +system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 633.737828 # Cycle average of tags in use +system.l2c.total_refs 148204 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 47216 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr deleted file mode 100755 index 507652626..000000000 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ /dev/null @@ -1,74 +0,0 @@ -system.cpu3: completed 10000 read accesses @26226880 -system.cpu6: completed 10000 read accesses @26416342 -system.cpu2: completed 10000 read accesses @26427251 -system.cpu5: completed 10000 read accesses @26798889 -system.cpu0: completed 10000 read accesses @26886521 -system.cpu7: completed 10000 read accesses @27109446 -system.cpu1: completed 10000 read accesses @27197408 -system.cpu4: completed 10000 read accesses @27318359 -system.cpu3: completed 20000 read accesses @53279230 -system.cpu6: completed 20000 read accesses @53417084 -system.cpu2: completed 20000 read accesses @53757092 -system.cpu0: completed 20000 read accesses @53888320 -system.cpu5: completed 20000 read accesses @53947132 -system.cpu4: completed 20000 read accesses @54390092 -system.cpu1: completed 20000 read accesses @54397720 -system.cpu7: completed 20000 read accesses @54632966 -system.cpu6: completed 30000 read accesses @80144176 -system.cpu3: completed 30000 read accesses @80518264 -system.cpu0: completed 30000 read accesses @80638600 -system.cpu5: completed 30000 read accesses @80869702 -system.cpu1: completed 30000 read accesses @81289158 -system.cpu2: completed 30000 read accesses @81358716 -system.cpu7: completed 30000 read accesses @81981296 -system.cpu4: completed 30000 read accesses @82043104 -system.cpu6: completed 40000 read accesses @107087547 -system.cpu0: completed 40000 read accesses @107662142 -system.cpu3: completed 40000 read accesses @107722516 -system.cpu5: completed 40000 read accesses @107884124 -system.cpu1: completed 40000 read accesses @107981413 -system.cpu7: completed 40000 read accesses @108415286 -system.cpu2: completed 40000 read accesses @108655120 -system.cpu4: completed 40000 read accesses @109427858 -system.cpu6: completed 50000 read accesses @133583246 -system.cpu0: completed 50000 read accesses @133832383 -system.cpu5: completed 50000 read accesses @134755386 -system.cpu1: completed 50000 read accesses @134792594 -system.cpu7: completed 50000 read accesses @134914312 -system.cpu3: completed 50000 read accesses @134993978 -system.cpu2: completed 50000 read accesses @135362549 -system.cpu4: completed 50000 read accesses @135394370 -system.cpu0: completed 60000 read accesses @160410176 -system.cpu6: completed 60000 read accesses @160667590 -system.cpu7: completed 60000 read accesses @161466346 -system.cpu1: completed 60000 read accesses @161592434 -system.cpu5: completed 60000 read accesses @161656374 -system.cpu4: completed 60000 read accesses @161882626 -system.cpu2: completed 60000 read accesses @162062631 -system.cpu3: completed 60000 read accesses @162154299 -system.cpu6: completed 70000 read accesses @187592265 -system.cpu1: completed 70000 read accesses @188138542 -system.cpu7: completed 70000 read accesses @188373105 -system.cpu0: completed 70000 read accesses @188690782 -system.cpu3: completed 70000 read accesses @189309687 -system.cpu2: completed 70000 read accesses @189360790 -system.cpu4: completed 70000 read accesses @189391126 -system.cpu5: completed 70000 read accesses @189902895 -system.cpu6: completed 80000 read accesses @214739574 -system.cpu1: completed 80000 read accesses @215665444 -system.cpu0: completed 80000 read accesses @216021457 -system.cpu7: completed 80000 read accesses @216394344 -system.cpu3: completed 80000 read accesses @216537382 -system.cpu4: completed 80000 read accesses @216775798 -system.cpu2: completed 80000 read accesses @216868662 -system.cpu5: completed 80000 read accesses @217401619 -system.cpu6: completed 90000 read accesses @241415090 -system.cpu1: completed 90000 read accesses @242558992 -system.cpu0: completed 90000 read accesses @242897388 -system.cpu7: completed 90000 read accesses @243372191 -system.cpu3: completed 90000 read accesses @243630762 -system.cpu5: completed 90000 read accesses @243633950 -system.cpu4: completed 90000 read accesses @243710816 -system.cpu2: completed 90000 read accesses @243974160 -system.cpu6: completed 100000 read accesses @268915439 -warn: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout deleted file mode 100755 index a9b5dbd1a..000000000 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt deleted file mode 100644 index 3a06809c5..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ /dev/null @@ -1,474 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -drivesys.cpu.dtb.accesses 401302 # DTB accesses -drivesys.cpu.dtb.acv 40 # DTB access violations -drivesys.cpu.dtb.hits 624235 # DTB hits -drivesys.cpu.dtb.misses 569 # DTB misses -drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses -drivesys.cpu.dtb.read_acv 30 # DTB read access violations -drivesys.cpu.dtb.read_hits 393500 # DTB read hits -drivesys.cpu.dtb.read_misses 487 # DTB read misses -drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses -drivesys.cpu.dtb.write_acv 10 # DTB write access violations -drivesys.cpu.dtb.write_hits 230735 # DTB write hits -drivesys.cpu.dtb.write_misses 82 # DTB write misses -drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles -drivesys.cpu.itb.accesses 1337980 # ITB accesses -drivesys.cpu.itb.acv 22 # ITB acv -drivesys.cpu.itb.hits 1337786 # ITB hits -drivesys.cpu.itb.misses 194 # ITB misses -drivesys.cpu.kern.callpal 4443 # number of callpals executed -drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed -drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed -drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed -drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed -drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed -drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed -drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed -drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed -drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed -drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed -drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.mode_good_kernel 110 -drivesys.cpu.kern.mode_good_user 107 -drivesys.cpu.kern.mode_good_idle 3 -drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches -drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches -drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode -drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed -drivesys.cpu.kern.syscall 22 # number of syscalls executed -drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed -drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed -drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed -drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed -drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed -drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed -drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed -drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed -drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed -drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed -drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed -drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed -drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated -drivesys.cpu.num_insts 1958129 # Number of instructions executed -drivesys.cpu.num_refs 626223 # Number of memory references -drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. -drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA -drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA -drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU -drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s) -drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received -drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device -drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) -drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received -drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device -drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) -drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes -drivesys.tsunami.ethernet.totPackets 13 # Total Packets -drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR -drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR -drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) -drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted -drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device -drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) -drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted -drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device -drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 200792296 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used -host_seconds 1.36 # Real time elapsed on the host -host_tick_rate 146922204609 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated -sim_seconds 0.200001 # Number of seconds simulated -sim_ticks 200000789468 # Number of ticks simulated -testsys.cpu.dtb.accesses 335402 # DTB accesses -testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163288 # DTB hits -testsys.cpu.dtb.misses 3815 # DTB misses -testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658435 # DTB read hits -testsys.cpu.dtb.read_misses 3287 # DTB read misses -testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504853 # DTB write hits -testsys.cpu.dtb.write_misses 528 # DTB write misses -testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249822 # ITB accesses -testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248325 # ITB hits -testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13122 # number of callpals executed -testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed -testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed -testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed -testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed -testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed -testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed -testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed -testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed -testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 -testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 438 # number of times the context was actually changed -testsys.cpu.kern.syscall 83 # number of syscalls executed -testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed -testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed -testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed -testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed -testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed -testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed -testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed -testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed -testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed -testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed -testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed -testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed -testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed -testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed -testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed -testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed -testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed -testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed -testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed -testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed -testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed -testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated -testsys.cpu.num_insts 3560411 # Number of instructions executed -testsys.cpu.num_refs 1173571 # Number of memory references -testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. -testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. -testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA -testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA -testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU -testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU -testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU -testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s) -testsys.tsunami.ethernet.rxBytes 798 # Bytes Received -testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device -testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) -testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received -testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device -testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) -testsys.tsunami.ethernet.totBytes 1758 # Total Bytes -testsys.tsunami.ethernet.totPackets 13 # Total Packets -testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR -testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR -testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) -testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted -testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device -testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) -testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted -testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device -testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device - ----------- End Simulation Statistics ---------- - ----------- Begin Simulation Statistics ---------- -drivesys.cpu.dtb.accesses 0 # DTB accesses -drivesys.cpu.dtb.acv 0 # DTB access violations -drivesys.cpu.dtb.hits 0 # DTB hits -drivesys.cpu.dtb.misses 0 # DTB misses -drivesys.cpu.dtb.read_accesses 0 # DTB read accesses -drivesys.cpu.dtb.read_acv 0 # DTB read access violations -drivesys.cpu.dtb.read_hits 0 # DTB read hits -drivesys.cpu.dtb.read_misses 0 # DTB read misses -drivesys.cpu.dtb.write_accesses 0 # DTB write accesses -drivesys.cpu.dtb.write_acv 0 # DTB write access violations -drivesys.cpu.dtb.write_hits 0 # DTB write hits -drivesys.cpu.dtb.write_misses 0 # DTB write misses -drivesys.cpu.idle_fraction 1 # Percentage of idle cycles -drivesys.cpu.itb.accesses 0 # ITB accesses -drivesys.cpu.itb.acv 0 # ITB acv -drivesys.cpu.itb.hits 0 # ITB hits -drivesys.cpu.itb.misses 0 # ITB misses -drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed -drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -drivesys.cpu.kern.mode_good_kernel 0 -drivesys.cpu.kern.mode_good_user 0 -drivesys.cpu.kern.mode_good_idle 0 -drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode -drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles -drivesys.cpu.numCycles 0 # number of cpu cycles simulated -drivesys.cpu.num_insts 0 # Number of instructions executed -drivesys.cpu.num_refs 0 # Number of memory references -drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. -drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -drivesys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 214516622449 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 582637509 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 785978 # Number of ticks simulated -testsys.cpu.dtb.accesses 0 # DTB accesses -testsys.cpu.dtb.acv 0 # DTB access violations -testsys.cpu.dtb.hits 0 # DTB hits -testsys.cpu.dtb.misses 0 # DTB misses -testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.read_acv 0 # DTB read access violations -testsys.cpu.dtb.read_hits 0 # DTB read hits -testsys.cpu.dtb.read_misses 0 # DTB read misses -testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.write_acv 0 # DTB write access violations -testsys.cpu.dtb.write_hits 0 # DTB write hits -testsys.cpu.dtb.write_misses 0 # DTB write misses -testsys.cpu.idle_fraction 1 # Percentage of idle cycles -testsys.cpu.itb.accesses 0 # ITB accesses -testsys.cpu.itb.acv 0 # ITB acv -testsys.cpu.itb.hits 0 # ITB hits -testsys.cpu.itb.misses 0 # ITB misses -testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -testsys.cpu.kern.mode_good_kernel 0 -testsys.cpu.kern.mode_good_user 0 -testsys.cpu.kern.mode_good_idle 0 -testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_good # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles -testsys.cpu.numCycles 0 # number of cpu cycles simulated -testsys.cpu.num_insts 0 # Number of instructions executed -testsys.cpu.num_refs 0 # Number of memory references -testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. -testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. -testsys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -testsys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr new file mode 100755 index 000000000..73103c03f --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -0,0 +1,6 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting terminal connections +warn: kernel located at: /dist/m5/system/binaries/vmlinux +warn: Sockets disabled, not accepting gdb connections +warn: Obsolete M5 ivlb instruction encountered. +warn: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout new file mode 100755 index 000000000..b7a61e7b4 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:38:27 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt new file mode 100644 index 000000000..3a06809c5 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -0,0 +1,474 @@ + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 401302 # DTB accesses +drivesys.cpu.dtb.acv 40 # DTB access violations +drivesys.cpu.dtb.hits 624235 # DTB hits +drivesys.cpu.dtb.misses 569 # DTB misses +drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses +drivesys.cpu.dtb.read_acv 30 # DTB read access violations +drivesys.cpu.dtb.read_hits 393500 # DTB read hits +drivesys.cpu.dtb.read_misses 487 # DTB read misses +drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses +drivesys.cpu.dtb.write_acv 10 # DTB write access violations +drivesys.cpu.dtb.write_hits 230735 # DTB write hits +drivesys.cpu.dtb.write_misses 82 # DTB write misses +drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles +drivesys.cpu.itb.accesses 1337980 # ITB accesses +drivesys.cpu.itb.acv 22 # ITB acv +drivesys.cpu.itb.hits 1337786 # ITB hits +drivesys.cpu.itb.misses 194 # ITB misses +drivesys.cpu.kern.callpal 4443 # number of callpals executed +drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed +drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed +drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed +drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed +drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed +drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed +drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed +drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed +drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.mode_good_kernel 110 +drivesys.cpu.kern.mode_good_user 107 +drivesys.cpu.kern.mode_good_idle 3 +drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed +drivesys.cpu.kern.syscall 22 # number of syscalls executed +drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed +drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed +drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed +drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed +drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed +drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed +drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed +drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed +drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed +drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed +drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed +drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles +drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated +drivesys.cpu.num_insts 1958129 # Number of instructions executed +drivesys.cpu.num_refs 626223 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s) +drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received +drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device +drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) +drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received +drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device +drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes +drivesys.tsunami.ethernet.totPackets 13 # Total Packets +drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) +drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted +drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) +drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted +drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +host_inst_rate 200792296 # Simulator instruction rate (inst/s) +host_mem_usage 476644 # Number of bytes of host memory used +host_seconds 1.36 # Real time elapsed on the host +host_tick_rate 146922204609 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 273294177 # Number of instructions simulated +sim_seconds 0.200001 # Number of seconds simulated +sim_ticks 200000789468 # Number of ticks simulated +testsys.cpu.dtb.accesses 335402 # DTB accesses +testsys.cpu.dtb.acv 161 # DTB access violations +testsys.cpu.dtb.hits 1163288 # DTB hits +testsys.cpu.dtb.misses 3815 # DTB misses +testsys.cpu.dtb.read_accesses 225414 # DTB read accesses +testsys.cpu.dtb.read_acv 80 # DTB read access violations +testsys.cpu.dtb.read_hits 658435 # DTB read hits +testsys.cpu.dtb.read_misses 3287 # DTB read misses +testsys.cpu.dtb.write_accesses 109988 # DTB write accesses +testsys.cpu.dtb.write_acv 81 # DTB write access violations +testsys.cpu.dtb.write_hits 504853 # DTB write hits +testsys.cpu.dtb.write_misses 528 # DTB write misses +testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles +testsys.cpu.itb.accesses 1249822 # ITB accesses +testsys.cpu.itb.acv 69 # ITB acv +testsys.cpu.itb.hits 1248325 # ITB hits +testsys.cpu.itb.misses 1497 # ITB misses +testsys.cpu.kern.callpal 13122 # number of callpals executed +testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed +testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed +testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed +testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed +testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed +testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed +testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 654 +testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.mode_good_idle 5 +testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 438 # number of times the context was actually changed +testsys.cpu.kern.syscall 83 # number of syscalls executed +testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed +testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed +testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed +testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed +testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed +testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed +testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed +testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed +testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed +testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed +testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed +testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed +testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed +testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed +testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed +testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed +testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed +testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed +testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed +testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed +testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed +testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles +testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated +testsys.cpu.num_insts 3560411 # Number of instructions executed +testsys.cpu.num_refs 1173571 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s) +testsys.tsunami.ethernet.rxBytes 798 # Bytes Received +testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device +testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) +testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received +testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device +testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +testsys.tsunami.ethernet.totBytes 1758 # Total Bytes +testsys.tsunami.ethernet.totPackets 13 # Total Packets +testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) +testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted +testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) +testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted +testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device + +---------- End Simulation Statistics ---------- + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 0 # DTB accesses +drivesys.cpu.dtb.acv 0 # DTB access violations +drivesys.cpu.dtb.hits 0 # DTB hits +drivesys.cpu.dtb.misses 0 # DTB misses +drivesys.cpu.dtb.read_accesses 0 # DTB read accesses +drivesys.cpu.dtb.read_acv 0 # DTB read access violations +drivesys.cpu.dtb.read_hits 0 # DTB read hits +drivesys.cpu.dtb.read_misses 0 # DTB read misses +drivesys.cpu.dtb.write_accesses 0 # DTB write accesses +drivesys.cpu.dtb.write_acv 0 # DTB write access violations +drivesys.cpu.dtb.write_hits 0 # DTB write hits +drivesys.cpu.dtb.write_misses 0 # DTB write misses +drivesys.cpu.idle_fraction 1 # Percentage of idle cycles +drivesys.cpu.itb.accesses 0 # ITB accesses +drivesys.cpu.itb.acv 0 # ITB acv +drivesys.cpu.itb.hits 0 # ITB hits +drivesys.cpu.itb.misses 0 # ITB misses +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +drivesys.cpu.kern.mode_good_kernel 0 +drivesys.cpu.kern.mode_good_user 0 +drivesys.cpu.kern.mode_good_idle 0 +drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed +drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +drivesys.cpu.numCycles 0 # number of cpu cycles simulated +drivesys.cpu.num_insts 0 # Number of instructions executed +drivesys.cpu.num_refs 0 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +host_inst_rate 214516622449 # Simulator instruction rate (inst/s) +host_mem_usage 476644 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 582637509 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 273294177 # Number of instructions simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 785978 # Number of ticks simulated +testsys.cpu.dtb.accesses 0 # DTB accesses +testsys.cpu.dtb.acv 0 # DTB access violations +testsys.cpu.dtb.hits 0 # DTB hits +testsys.cpu.dtb.misses 0 # DTB misses +testsys.cpu.dtb.read_accesses 0 # DTB read accesses +testsys.cpu.dtb.read_acv 0 # DTB read access violations +testsys.cpu.dtb.read_hits 0 # DTB read hits +testsys.cpu.dtb.read_misses 0 # DTB read misses +testsys.cpu.dtb.write_accesses 0 # DTB write accesses +testsys.cpu.dtb.write_acv 0 # DTB write access violations +testsys.cpu.dtb.write_hits 0 # DTB write hits +testsys.cpu.dtb.write_misses 0 # DTB write misses +testsys.cpu.idle_fraction 1 # Percentage of idle cycles +testsys.cpu.itb.accesses 0 # ITB accesses +testsys.cpu.itb.acv 0 # ITB acv +testsys.cpu.itb.hits 0 # ITB hits +testsys.cpu.itb.misses 0 # ITB misses +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +testsys.cpu.kern.mode_good_kernel 0 +testsys.cpu.kern.mode_good_user 0 +testsys.cpu.kern.mode_good_idle 0 +testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_good # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 0 # number of times the context was actually changed +testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +testsys.cpu.numCycles 0 # number of cpu cycles simulated +testsys.cpu.num_insts 0 # Number of instructions executed +testsys.cpu.num_refs 0 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr deleted file mode 100755 index 73103c03f..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ /dev/null @@ -1,6 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting terminal connections -warn: kernel located at: /dist/m5/system/binaries/vmlinux -warn: Sockets disabled, not accepting gdb connections -warn: Obsolete M5 ivlb instruction encountered. -warn: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout deleted file mode 100755 index b7a61e7b4..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:27 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4300236804024 because checkpoint -- cgit v1.2.3 From ab5eeb4b62e14528beaf41d21305dfda075c5133 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 15 Dec 2008 00:47:15 -0800 Subject: Update the stats for the fixes to the PCI device class. --- .../ref/alpha/linux/tsunami-o3-dual/simout | 14 +- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 1394 ++++++++++---------- .../alpha/linux/tsunami-o3-dual/system.terminal | 2 + .../ref/alpha/linux/tsunami-o3/simout | 14 +- .../ref/alpha/linux/tsunami-o3/stats.txt | 772 +++++------ .../ref/alpha/linux/tsunami-o3/system.terminal | 2 + .../alpha/linux/tsunami-simple-atomic-dual/simout | 12 +- .../linux/tsunami-simple-atomic-dual/stats.txt | 206 +-- .../tsunami-simple-atomic-dual/system.terminal | 2 + .../ref/alpha/linux/tsunami-simple-atomic/simout | 14 +- .../alpha/linux/tsunami-simple-atomic/stats.txt | 228 ++-- .../linux/tsunami-simple-atomic/system.terminal | 2 + .../alpha/linux/tsunami-simple-timing-dual/simout | 14 +- .../linux/tsunami-simple-timing-dual/stats.txt | 686 +++++----- .../tsunami-simple-timing-dual/system.terminal | 2 + .../ref/alpha/linux/tsunami-simple-timing/simout | 14 +- .../alpha/linux/tsunami-simple-timing/stats.txt | 430 +++--- .../linux/tsunami-simple-timing/system.terminal | 2 + .../linux/twosys-tsunami-simple-atomic/config.ini | 4 +- .../twosys-tsunami-simple-atomic/drivesys.terminal | 2 + .../linux/twosys-tsunami-simple-atomic/simout | 12 +- .../linux/twosys-tsunami-simple-atomic/stats.txt | 18 +- .../twosys-tsunami-simple-atomic/testsys.terminal | 2 + 23 files changed, 1932 insertions(+), 1916 deletions(-) (limited to 'tests') diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index bace1f0ca..cd7d66c16 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:35:52 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:53 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705350500 because m5_exit instruction encountered +Exiting @ tick 1907705384500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index cbdec272c..6cd8fa945 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -2,149 +2,149 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4974822 # Number of BTB hits -global.BPredUnit.BTBHits 2263931 # Number of BTB hits -global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups -global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups -global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions. -global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect -global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted -global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted -global.BPredUnit.lookups 10092697 # Number of BP lookups -global.BPredUnit.lookups 5530798 # Number of BP lookups -global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. -global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 121094 # Simulator instruction rate (inst/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 463.72 # Real time elapsed on the host -host_tick_rate 4113887240 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 4976196 # Number of BTB hits +global.BPredUnit.BTBHits 2271370 # Number of BTB hits +global.BPredUnit.BTBLookups 9270308 # Number of BTB lookups +global.BPredUnit.BTBLookups 5052293 # Number of BTB lookups +global.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. +global.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect +global.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted +global.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted +global.BPredUnit.lookups 10093436 # Number of BP lookups +global.BPredUnit.lookups 5538388 # Number of BP lookups +global.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. +global.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. +host_inst_rate 132487 # Simulator instruction rate (inst/s) +host_mem_usage 294244 # Number of bytes of host memory used +host_seconds 424.12 # Real time elapsed on the host +host_tick_rate 4498020766 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 2050532 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 906322 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1832540 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 817104 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56154063 # Number of instructions simulated +sim_insts 56190549 # Number of instructions simulated sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705350500 # Number of ticks simulated -system.cpu0.commit.COM:branches 5979955 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached +sim_ticks 1907705384500 # Number of ticks simulated +system.cpu0.commit.COM:branches 5979895 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 670394 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 69429521 +system.cpu0.commit.COM:committed_per_cycle.samples 69432721 system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 52132882 7508.75% - 1 7659816 1103.25% - 2 4444319 640.12% - 3 2023012 291.38% - 4 1474688 212.40% - 5 453462 65.31% - 6 276660 39.85% - 7 294053 42.35% - 8 670629 96.59% + 0 52134013 7508.57% + 1 7662361 1103.57% + 2 4443978 640.04% + 3 2023859 291.48% + 4 1473823 212.27% + 5 453847 65.37% + 6 276435 39.81% + 7 294011 42.34% + 8 670394 96.55% system.cpu0.commit.COM:committed_per_cycle.max_value 8 system.cpu0.commit.COM:committed_per_cycle.end_dist -system.cpu0.commit.COM:count 39866915 # Number of instructions committed -system.cpu0.commit.COM:loads 6404567 # Number of loads committed -system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831807 # Number of memory references committed +system.cpu0.commit.COM:count 39866260 # Number of instructions committed +system.cpu0.commit.COM:loads 6404474 # Number of loads committed +system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed +system.cpu0.commit.COM:refs 10831640 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37661300 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated -system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency +system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6218747 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 37660679 # Number of Instructions Simulated +system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated +system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses 147686 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 135219 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.084416 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 12467 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 6414696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 5468142 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27426760000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147560 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946554 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250845 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19978224000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108455 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 156551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 140528 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 875945000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.102350 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 16023 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4258061 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_hits 2612712 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 80387760774 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.386408 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 1645349 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269940236 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050786497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.072518 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 9.224260 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 116343 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082812738 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 10672757 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080854 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107814520774 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242852 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2591903 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613053 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35248164236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 10672757 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 8080450 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2592009 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_hits 8080854 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107814520774 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242852 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2591903 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613053 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35248164236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -155,105 +155,105 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 922698 # number of replacements -system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 922726 # number of replacements +system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8515127 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297324 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking -system.cpu0.dtb.accesses 812630 # DTB accesses -system.cpu0.dtb.acv 800 # DTB access violations -system.cpu0.dtb.hits 11624529 # DTB hits -system.cpu0.dtb.misses 28502 # DTB misses -system.cpu0.dtb.read_accesses 605275 # DTB read accesses +system.cpu0.dcache.writebacks 297339 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33638498 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 401379 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50930127 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25726100 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9143957 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1094068 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking +system.cpu0.dtb.accesses 812672 # DTB accesses +system.cpu0.dtb.acv 801 # DTB access violations +system.cpu0.dtb.hits 11625470 # DTB hits +system.cpu0.dtb.misses 28525 # DTB misses +system.cpu0.dtb.read_accesses 605265 # DTB read accesses system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7062851 # DTB read hits -system.cpu0.dtb.read_misses 24043 # DTB read misses -system.cpu0.dtb.write_accesses 207355 # DTB write accesses -system.cpu0.dtb.write_acv 204 # DTB write access violations -system.cpu0.dtb.write_hits 4561678 # DTB write hits -system.cpu0.dtb.write_misses 4459 # DTB write misses -system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle +system.cpu0.dtb.read_hits 7063685 # DTB read hits +system.cpu0.dtb.read_misses 24056 # DTB read misses +system.cpu0.dtb.write_accesses 207407 # DTB write accesses +system.cpu0.dtb.write_acv 205 # DTB write access violations +system.cpu0.dtb.write_hits 4561785 # DTB write hits +system.cpu0.dtb.write_misses 4469 # DTB write misses +system.cpu0.fetch.Branches 10093436 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456939 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16710993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292607 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 52006564 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660338 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6456939 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5666570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 70522996 +system.cpu0.fetch.rateDist.samples 70526789 system.cpu0.fetch.rateDist.min_value 0 - 0 60301622 8550.63% - 1 760699 107.87% - 2 1434176 203.36% - 3 635243 90.08% - 4 2330465 330.45% - 5 474381 67.27% - 6 552250 78.31% - 7 815542 115.64% - 8 3218618 456.39% + 0 60303520 8550.44% + 1 761818 108.02% + 2 1433854 203.31% + 3 636079 90.19% + 4 2329702 330.33% + 5 474692 67.31% + 6 552513 78.34% + 7 815433 115.62% + 8 3219178 456.45% system.cpu0.fetch.rateDist.max_value 8 system.cpu0.fetch.rateDist.end_dist -system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_accesses 6456939 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.131269 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.657762 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806696 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9879877499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.100705 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 650243 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 7526067999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked +system.cpu0.icache.avg_refs 9.361637 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 34 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 401499 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency -system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses -system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 6456939 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806696 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9879877499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_misses 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 7526067999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 6456939 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 5806036 # number of overall hits -system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses -system.cpu0.icache.overall_misses 650298 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses +system.cpu0.icache.overall_hits 5806696 # number of overall hits +system.cpu0.icache.overall_miss_latency 9879877499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_misses 650243 # number of overall misses +system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 7526067999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -265,80 +265,80 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 619824 # number of replacements -system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 619753 # number of replacements +system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use +system.cpu0.icache.total_refs 5806696 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate -system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed +system.cpu0.idleCycles 30375232 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436271 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512861 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402649 # Inst execution rate +system.cpu0.iew.EXEC:refs 11740634 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575971 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value -system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back +system.cpu0.iew.WB:consumers 24161361 # num instructions consuming a value +system.cpu0.iew.WB:count 40226140 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18821888 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle -system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 18823101 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398665 # insts written-back per cycle +system.cpu0.iew.WB:sent 40293974 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7178022 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7553751 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 4835994 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46191067 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7164663 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359395 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40628051 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33755 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1094068 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453365 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 34084 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12238 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1149277 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408828 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 34084 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0 40987446 # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3324 0.01% # Type of FU issued - IntAlu 28266314 68.97% # Type of FU issued - IntMult 42210 0.10% # Type of FU issued + No_OpClass 3326 0.01% # Type of FU issued + IntAlu 28267902 68.97% # Type of FU issued + IntMult 42211 0.10% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 12073 0.03% # Type of FU issued + FloatAdd 12076 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued - FloatDiv 1656 0.00% # Type of FU issued + FloatDiv 1657 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 7397265 18.05% # Type of FU issued - MemWrite 4611960 11.25% # Type of FU issued - IprAccess 650122 1.59% # Type of FU issued + MemRead 7398183 18.05% # Type of FU issued + MemWrite 4612040 11.25% # Type of FU issued + IprAccess 650051 1.59% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.end_dist -system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_busy_cnt 290461 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 33477 11.53% # attempts to use FU when none available + IntAlu 33502 11.53% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -347,39 +347,39 @@ system.cpu0.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 185557 63.91% # attempts to use FU when none available - MemWrite 71326 24.56% # attempts to use FU when none available + MemRead 185625 63.91% # attempts to use FU when none available + MemWrite 71334 24.56% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full.end_dist system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996 +system.cpu0.iq.ISSUE:issued_per_cycle.samples 70526789 system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49763845 7056.40% - 1 10504305 1489.49% - 2 4625788 655.93% - 3 2839071 402.57% - 4 1729907 245.30% - 5 663571 94.09% - 6 315326 44.71% - 7 67073 9.51% - 8 14110 2.00% + 0 49764698 7056.14% + 1 10507711 1489.89% + 2 4625293 655.82% + 3 2839060 402.55% + 4 1729945 245.29% + 5 663621 94.09% + 6 315226 44.70% + 7 67152 9.52% + 8 14083 2.00% system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu0.iq.ISSUE:issued_per_cycle.end_dist -system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.itb.accesses 875611 # ITB accesses -system.cpu0.itb.acv 895 # ITB acv -system.cpu0.itb.hits 845707 # ITB hits -system.cpu0.itb.misses 29904 # ITB misses -system.cpu0.kern.callpal 129595 # number of callpals executed +system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate +system.cpu0.iq.iqInstsAdded 42280485 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40987446 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5737873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3058467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.itb.accesses 875811 # ITB accesses +system.cpu0.itb.acv 900 # ITB acv +system.cpu0.itb.hits 845925 # ITB hits +system.cpu0.itb.misses 29886 # ITB misses +system.cpu0.kern.callpal 129578 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed @@ -388,53 +388,53 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # nu system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed +system.cpu0.kern.callpal_swpipl 116005 89.53% 91.51% # number of callpals executed system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.42% # number of callpals executed system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 122308 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 47763 39.05% 39.05% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1931 1.58% 40.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 72358 59.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 96397 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good_31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1907288793500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871606924500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 101495000 0.01% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397995000 0.02% 98.16% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_31 35173048000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.986391 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1284 -system.cpu0.kern.mode_good_user 1284 +system.cpu0.kern.ipl_used_31 0.650889 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1283 +system.cpu0.kern.mode_good_user 1283 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1283 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.217679 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2121516000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2411 # number of times the context was actually changed system.cpu0.kern.syscall 222 # number of syscalls executed @@ -467,138 +467,138 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.numCycles 100900932 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.commit.COM:branches 2941268 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached +system.cpu0.numCycles 100902021 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10627682 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742849 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930411 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 58880309 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48158423 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32535865 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9104795 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1094068 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612727 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5197954 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19157104 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8536821 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed +system.cpu0.timesIdled 904725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.commit.COM:branches 2947825 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37417436 +system.cpu1.commit.COM:committed_per_cycle.samples 37477455 system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29372797 7850.03% - 1 3570649 954.27% - 2 1730450 462.47% - 3 1048421 280.20% - 4 705992 188.68% - 5 261184 69.80% - 6 182468 48.77% - 7 141194 37.73% - 8 404281 108.05% + 0 29419466 7849.91% + 1 3577484 954.57% + 2 1728132 461.11% + 3 1049888 280.14% + 4 708571 189.07% + 5 265965 70.97% + 6 180885 48.27% + 7 145538 38.83% + 8 401526 107.14% system.cpu1.commit.COM:committed_per_cycle.max_value 8 system.cpu1.commit.COM:committed_per_cycle.end_dist -system.cpu1.commit.COM:count 19624114 # Number of instructions committed -system.cpu1.commit.COM:loads 3545101 # Number of loads committed -system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5853378 # Number of memory references committed +system.cpu1.commit.COM:count 19663805 # Number of instructions committed +system.cpu1.commit.COM:loads 3551077 # Number of loads committed +system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5861573 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18492763 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated -system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency +system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3736987 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 18529870 # Number of Instructions Simulated +system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated +system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses 72126 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14445.783133 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 59842 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.170313 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 12284 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 3589521 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15546.334532 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11998.783257 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 2947311 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9984011500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.178912 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 642210 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 5172303500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298579500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 68169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 51420 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.245698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 16749 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 2234886 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 49366.448141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.795546 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_hits 1540754 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 34266831381 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.310589 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 694132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 7735952636 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 8.879315 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 31364 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 438908636 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 5824407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4488065 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44250842881 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229438 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 12908256136 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098495 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 5824407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 4480566 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 1336410 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_hits 4488065 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44250842881 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229438 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 1336342 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 12908256136 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -609,105 +609,105 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 531824 # number of replacements -system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 531784 # number of replacements +system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4726424 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158256 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked +system.cpu1.dcache.writebacks 158239 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 17789626 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking -system.cpu1.dtb.accesses 434054 # DTB accesses -system.cpu1.dtb.acv 76 # DTB access violations -system.cpu1.dtb.hits 6272530 # DTB hits -system.cpu1.dtb.misses 17149 # DTB misses -system.cpu1.dtb.read_accesses 314239 # DTB read accesses +system.cpu1.decode.DECODE:BranchResolved 246498 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26253438 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14731458 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4724229 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641522 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking +system.cpu1.dtb.accesses 433929 # DTB accesses +system.cpu1.dtb.acv 77 # DTB access violations +system.cpu1.dtb.hits 6280849 # DTB hits +system.cpu1.dtb.misses 17153 # DTB misses +system.cpu1.dtb.read_accesses 314117 # DTB read accesses system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3866975 # DTB read hits -system.cpu1.dtb.read_misses 13433 # DTB read misses -system.cpu1.dtb.write_accesses 119815 # DTB write accesses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_hits 2405555 # DTB write hits -system.cpu1.dtb.write_misses 3716 # DTB write misses -system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle +system.cpu1.dtb.read_hits 3872885 # DTB read hits +system.cpu1.dtb.read_misses 13436 # DTB read misses +system.cpu1.dtb.write_accesses 119812 # DTB write accesses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_hits 2407964 # DTB write hits +system.cpu1.dtb.write_misses 3717 # DTB write misses +system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched +system.cpu1.fetch.Cycles 8137043 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26826541 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 373513 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.626136 # Number of inst fetches per cycle system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38058467 +system.cpu1.fetch.rateDist.samples 38118977 system.cpu1.fetch.rateDist.min_value 0 - 0 33027824 8678.18% - 1 336540 88.43% - 2 683303 179.54% - 3 398795 104.78% - 4 792602 208.26% - 5 252574 66.36% - 6 340311 89.42% - 7 403731 106.08% - 8 1822787 478.94% + 0 33077956 8677.56% + 1 338219 88.73% + 2 684572 179.59% + 3 401330 105.28% + 4 792380 207.87% + 5 254419 66.74% + 6 341251 89.52% + 7 404733 106.18% + 8 1824117 478.53% system.cpu1.fetch.rateDist.max_value 8 system.cpu1.fetch.rateDist.end_dist -system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 3089103 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14554.963245 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.753460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 2620972 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6813629499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 468131 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5189286000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency -system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses -system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.demand_hits 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6813629499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_misses 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5189286000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 3089103 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 2613676 # number of overall hits -system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses -system.cpu1.icache.overall_misses 468089 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses +system.cpu1.icache.overall_hits 2620972 # number of overall hits +system.cpu1.icache.overall_miss_latency 6813629499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_misses 468131 # number of overall misses +system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5189286000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -719,63 +719,63 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 446548 # number of replacements -system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 446606 # number of replacements +system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use -system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use +system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed -system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate -system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed +system.cpu1.idleCycles 4725605 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3215748 # Number of branches executed +system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.474711 # Inst execution rate +system.cpu1.iew.EXEC:refs 6453696 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2419389 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value -system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back +system.cpu1.iew.WB:consumers 12378269 # num instructions consuming a value +system.cpu1.iew.WB:count 20082329 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731659 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9033918 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle -system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 9056670 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468725 # insts written-back per cycle +system.cpu1.iew.WB:sent 20124761 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2501198 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4247428 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2557361 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23476813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4034307 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 224585 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20338799 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 641522 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 18288 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7650 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 696351 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246865 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18288 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0 20563386 # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.start_dist No_OpClass 3984 0.02% # Type of FU issued - IntAlu 13446211 65.50% # Type of FU issued - IntMult 28837 0.14% # Type of FU issued + IntAlu 13476321 65.54% # Type of FU issued + IntMult 28965 0.14% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 13702 0.07% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued @@ -783,16 +783,16 @@ system.cpu1.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 1986 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4170434 20.32% # Type of FU issued - MemWrite 2440876 11.89% # Type of FU issued - IprAccess 421203 2.05% # Type of FU issued + MemRead 4173926 20.30% # Type of FU issued + MemWrite 2443261 11.88% # Type of FU issued + IprAccess 421241 2.05% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.end_dist -system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_busy_cnt 221052 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010750 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 16051 7.28% # attempts to use FU when none available + IntAlu 16139 7.30% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -801,39 +801,39 @@ system.cpu1.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 131548 59.63% # attempts to use FU when none available - MemWrite 73016 33.10% # attempts to use FU when none available + MemRead 131915 59.68% # attempts to use FU when none available + MemWrite 72998 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full.end_dist system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467 +system.cpu1.iq.ISSUE:issued_per_cycle.samples 38118977 system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28368882 7454.03% - 1 4650018 1221.81% - 2 1988549 522.50% - 3 1356758 356.49% - 4 973103 255.69% - 5 468416 123.08% - 6 186236 48.93% - 7 54105 14.22% - 8 12400 3.26% + 0 28405823 7451.88% + 1 4664380 1223.64% + 2 1989669 521.96% + 3 1362790 357.51% + 4 979073 256.85% + 5 465618 122.15% + 6 186895 49.03% + 7 52286 13.72% + 8 12443 3.26% system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu1.iq.ISSUE:issued_per_cycle.end_dist -system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.itb.accesses 525300 # ITB accesses -system.cpu1.itb.acv 103 # ITB acv -system.cpu1.itb.hits 518475 # ITB hits -system.cpu1.itb.misses 6825 # ITB misses -system.cpu1.kern.callpal 87347 # number of callpals executed +system.cpu1.iq.ISSUE:rate 0.479953 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21283894 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20563386 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3483485 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16725 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1773520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.itb.accesses 525294 # ITB accesses +system.cpu1.itb.acv 109 # ITB acv +system.cpu1.itb.hits 518481 # ITB hits +system.cpu1.itb.misses 6813 # ITB misses +system.cpu1.kern.callpal 87355 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed @@ -841,7 +841,7 @@ system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # nu system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed +system.cpu1.kern.callpal_swpipl 79684 91.22% 93.36% # number of callpals executed system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed @@ -851,40 +851,40 @@ system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # nu system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 84915 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 34143 40.21% 40.21% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 48748 57.41% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 68760 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good_31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1907704531000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1871986899500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 352080000 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 40004500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35325547000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.978707 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.683515 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 521 system.cpu1.kern.mode_good_user 463 system.cpu1.kern.mode_good_idle 58 -system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 2305 # number of protection mode switches system.cpu1.kern.mode_switch_user 463 # number of protection mode switches system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 1.254532 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.226030 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1015923000 0.05% 2.50% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1839 # number of times the context was actually changed system.cpu1.kern.syscall 104 # number of syscalls executed system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed @@ -900,25 +900,25 @@ system.cpu1.kern.syscall_59 1 0.96% 57.69% # nu system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.numCycles 42759649 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.numCycles 42844582 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3655834 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 15199760 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 29419469 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24525114 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16182590 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4333684 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641522 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2990936 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12476165 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed +system.cpu1.timesIdled 480520 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -932,55 +932,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6165.982406 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64483844 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -997,80 +997,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41697 # number of replacements system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387818 # Cycle average of tags in use +system.iocache.tagsinuse 0.387817 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 317502 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52375.567080 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.034620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629347299 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 317502 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12770893938 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2204255 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52067.361570 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.445360 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1893933 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 310350 # number of ReadReq misses +system.l2c.ReadReq_hits 1893900 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16159366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.140798 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310355 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12421727000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310338 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 141949 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 51066.182164 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.287026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 141949 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5691202000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 455580 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1423764498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 455578 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.836093 # Average number of references to valid blocks. +system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency -system.l2c.demand_hits 1893933 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses -system.l2c.demand_misses 627845 # number of demand (read+write) misses +system.l2c.demand_accesses 2521757 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.demand_hits 1893900 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32788713299 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.248976 # miss rate for demand accesses +system.l2c.demand_misses 627857 # number of demand (read+write) misses system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 25192620938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.248969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 627840 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.overall_accesses 2521757 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1893933 # number of overall hits -system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles -system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses -system.l2c.overall_misses 627845 # number of overall misses +system.l2c.overall_hits 1893900 # number of overall hits +system.l2c.overall_miss_latency 32788713299 # number of overall miss cycles +system.l2c.overall_miss_rate 0.248976 # miss rate for overall accesses +system.l2c.overall_misses 627857 # number of overall misses system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 25192620938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.248969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -1081,13 +1081,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 402113 # number of replacements -system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. +system.l2c.replacements 402142 # number of replacements +system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use -system.l2c.total_refs 2097138 # Total number of references to valid blocks. +system.l2c.tagsinuse 31163.178814 # Cycle average of tags in use +system.l2c.total_refs 2096699 # Total number of references to valid blocks. system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124275 # number of writebacks +system.l2c.writebacks 124293 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index d5c08c61f..6c5842787 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -61,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -72,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f6f2f7d37..c0c3673fc 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:31:00 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:52 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867358550500 because m5_exit instruction encountered +Exiting @ tick 1867363148500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 4860b3f1d..d70f58b89 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 6932487 # Number of BTB hits -global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted -global.BPredUnit.lookups 14559443 # Number of BP lookups -global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 123231 # Simulator instruction rate (inst/s) -host_mem_usage 290820 # Number of bytes of host memory used -host_seconds 430.51 # Real time elapsed on the host -host_tick_rate 4337505567 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 6937900 # Number of BTB hits +global.BPredUnit.BTBLookups 13339861 # Number of BTB lookups +global.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted +global.BPredUnit.lookups 14570242 # Number of BP lookups +global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. +host_inst_rate 133323 # Simulator instruction rate (inst/s) +host_mem_usage 292856 # Number of bytes of host memory used +host_seconds 398.21 # Real time elapsed on the host +host_tick_rate 4689394624 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53052618 # Number of instructions simulated -sim_seconds 1.867359 # Number of seconds simulated -sim_ticks 1867358550500 # Number of ticks simulated -system.cpu.commit.COM:branches 8455188 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached +sim_insts 53090630 # Number of instructions simulated +sim_seconds 1.867363 # Number of seconds simulated +sim_ticks 1867363148500 # Number of ticks simulated +system.cpu.commit.COM:branches 8461943 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 100543308 +system.cpu.commit.COM:committed_per_cycle.samples 100617513 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 76317924 7590.55% - 1 10743540 1068.55% - 2 5987880 595.55% - 3 2987787 297.16% - 4 2072579 206.14% - 5 671161 66.75% - 6 395328 39.32% - 7 393271 39.11% - 8 973838 96.86% + 0 76371867 7590.32% + 1 10755813 1068.98% + 2 5991818 595.50% + 3 2987930 296.96% + 4 2074332 206.16% + 5 671621 66.75% + 6 397219 39.48% + 7 392307 38.99% + 8 974606 96.86% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 56244351 # Number of instructions committed -system.cpu.commit.COM:loads 9302477 # Number of loads committed -system.cpu.commit.COM:membars 227741 # Number of memory barriers committed -system.cpu.commit.COM:refs 15692393 # Number of memory references committed +system.cpu.commit.COM:count 56284983 # Number of instructions committed +system.cpu.commit.COM:loads 9308629 # Number of loads committed +system.cpu.commit.COM:membars 228003 # Number of memory barriers committed +system.cpu.commit.COM:refs 15700868 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53052618 # Number of Instructions Simulated -system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated -system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency +system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53090630 # Number of Instructions Simulated +system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated +system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency -system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 11726365 # number of overall hits -system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3763307 # number of overall misses +system.cpu.dcache.overall_hits 11736507 # number of overall hits +system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3763211 # number of overall misses system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -143,105 +143,105 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1402096 # number of replacements -system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401991 # number of replacements +system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use -system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430429 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 1229941 # DTB accesses -system.cpu.dtb.acv 828 # DTB access violations -system.cpu.dtb.hits 16757791 # DTB hits -system.cpu.dtb.misses 44378 # DTB misses -system.cpu.dtb.read_accesses 908364 # DTB read accesses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_hits 10166755 # DTB read hits -system.cpu.dtb.read_misses 36227 # DTB read misses -system.cpu.dtb.write_accesses 321577 # DTB write accesses -system.cpu.dtb.write_acv 241 # DTB write access violations -system.cpu.dtb.write_hits 6591036 # DTB write hits -system.cpu.dtb.write_misses 8151 # DTB write misses -system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched -system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 430428 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 1236420 # DTB accesses +system.cpu.dtb.acv 825 # DTB access violations +system.cpu.dtb.hits 16772347 # DTB hits +system.cpu.dtb.misses 44495 # DTB misses +system.cpu.dtb.read_accesses 910052 # DTB read accesses +system.cpu.dtb.read_acv 586 # DTB read access violations +system.cpu.dtb.read_hits 10174508 # DTB read hits +system.cpu.dtb.read_misses 36219 # DTB read misses +system.cpu.dtb.write_accesses 326368 # DTB write accesses +system.cpu.dtb.write_acv 239 # DTB write access violations +system.cpu.dtb.write_hits 6597839 # DTB write hits +system.cpu.dtb.write_misses 8276 # DTB write misses +system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched +system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 102189280 +system.cpu.fetch.rateDist.samples 102267931 system.cpu.fetch.rateDist.min_value 0 - 0 87752503 8587.25% - 1 1049427 102.69% - 2 2020193 197.69% - 3 968502 94.78% - 4 3001129 293.68% - 5 683878 66.92% - 6 831667 81.38% - 7 1217349 119.13% - 8 4664632 456.47% + 0 87815810 8586.84% + 1 1050742 102.74% + 2 2021882 197.70% + 3 969421 94.79% + 4 3003437 293.68% + 5 686434 67.12% + 6 832579 81.41% + 7 1218388 119.14% + 8 4669238 456.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency -system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses -system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency +system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7948798 # number of overall hits -system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses -system.cpu.icache.overall_misses 1047360 # number of overall misses -system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses +system.cpu.icache.overall_hits 7960337 # number of overall hits +system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047504 # number of overall misses +system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -253,63 +253,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 994691 # number of replacements -system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. +system.cpu.icache.replacements 994847 # number of replacements +system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use -system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use +system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9157080 # Number of branches executed -system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate -system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6614103 # Number of stores executed +system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9164699 # Number of branches executed +system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate +system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6621040 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value -system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back +system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value +system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26369407 # num instructions producing a value -system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle -system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26394693 # num instructions producing a value +system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle +system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7284 0.01% # Type of FU issued - IntAlu 39585322 68.15% # Type of FU issued - IntMult 61995 0.11% # Type of FU issued + IntAlu 39619390 68.15% # Type of FU issued + IntMult 62115 0.11% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 25609 0.04% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued @@ -317,16 +317,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 3636 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 10781907 18.56% # Type of FU issued - MemWrite 6666291 11.48% # Type of FU issued - IprAccess 953214 1.64% # Type of FU issued + MemRead 10789898 18.56% # Type of FU issued + MemWrite 6674141 11.48% # Type of FU issued + IprAccess 953288 1.64% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 52004 11.98% # attempts to use FU when none available + IntAlu 52045 11.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -335,39 +335,39 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 278726 64.23% # attempts to use FU when none available - MemWrite 103217 23.79% # attempts to use FU when none available + MemRead 278817 64.17% # attempts to use FU when none available + MemWrite 103619 23.85% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 +system.cpu.iq.ISSUE:issued_per_cycle.samples 102267931 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 73101546 7153.54% - 1 14613738 1430.07% - 2 6411296 627.39% - 3 3930297 384.61% - 4 2526857 247.27% - 5 1033193 101.11% - 6 443511 43.40% - 7 107158 10.49% - 8 21684 2.12% + 0 73151138 7152.89% + 1 14628619 1430.42% + 2 6419666 627.73% + 3 3934330 384.71% + 4 2528894 247.28% + 5 1032607 100.97% + 6 444582 43.47% + 7 106443 10.41% + 8 21652 2.12% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate -system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1300570 # ITB accesses -system.cpu.itb.acv 941 # ITB acv -system.cpu.itb.hits 1261136 # ITB hits -system.cpu.itb.misses 39434 # ITB misses -system.cpu.kern.callpal 192636 # number of callpals executed +system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate +system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1303895 # ITB accesses +system.cpu.itb.acv 943 # ITB acv +system.cpu.itb.hits 1264480 # ITB hits +system.cpu.itb.misses 39415 # ITB misses +system.cpu.kern.callpal 192656 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -375,7 +375,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -385,40 +385,40 @@ system.cpu.kern.callpal_rti 5221 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1911 system.cpu.kern.mode_good_user 1741 system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches system.cpu.kern.mode_switch_user 1741 # number of protection mode switches system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -451,25 +451,25 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.numCycles 136890724 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed -system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 136996939 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed +system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -483,55 +483,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -548,80 +548,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267378 # Cycle average of tags in use +system.iocache.tagsinuse 1.267414 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1786309 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 311028 # number of ReadReq misses +system.l2c.ReadReq_hits 1786374 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311021 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430429 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430428 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. +system.l2c.avg_refs 4.596635 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency -system.l2c.demand_hits 1786309 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses -system.l2c.demand_misses 611623 # number of demand (read+write) misses +system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency +system.l2c.demand_hits 1786374 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses +system.l2c.demand_misses 611609 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1786309 # number of overall hits -system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles -system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses -system.l2c.overall_misses 611623 # number of overall misses +system.l2c.overall_hits 1786374 # number of overall hits +system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses +system.l2c.overall_misses 611609 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -632,13 +632,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 396037 # number of replacements -system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. +system.l2c.replacements 396031 # number of replacements +system.l2c.sampled_refs 427707 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use -system.l2c.total_refs 1966986 # Total number of references to valid blocks. +system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use +system.l2c.total_refs 1966013 # Total number of references to valid blocks. system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119087 # number of writebacks +system.l2c.writebacks 119091 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index 8a13d1a5e..1b4012ef1 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -56,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -67,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index a9bd0ea3f..2e7c9e61b 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:23 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:48:26 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 1e6af66f7..55ea1f24a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3333474 # Simulator instruction rate (inst/s) -host_mem_usage 290708 # Number of bytes of host memory used -host_seconds 18.93 # Real time elapsed on the host -host_tick_rate 98784311223 # Simulator tick rate (ticks/s) +host_inst_rate 1560779 # Simulator instruction rate (inst/s) +host_mem_usage 292076 # Number of bytes of host memory used +host_seconds 40.46 # Real time elapsed on the host +host_tick_rate 46222973494 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63113507 # Number of instructions simulated +sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated sim_ticks 1870335522500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664298 # number of overall hits +system.cpu0.dcache.overall_hits 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057375 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057371 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978967 # number of replacements -system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978962 # number of replacements +system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082911 # DTB hits +system.cpu0.dtb.hits 15091429 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148351 # DTB read hits +system.cpu0.dtb.read_hits 9154530 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934560 # DTB write hits +system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56304737 # number of overall hits +system.cpu0.icache.overall_hits 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884868 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_misses 885000 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,28 +137,28 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884272 # number of replacements -system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884404 # number of replacements +system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858857 # ITB accesses +system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.itb.accesses 3859041 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855372 # ITB hits +system.cpu0.itb.hits 3855556 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183274 # number of callpals executed +system.cpu0.kern.callpal 183291 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168035 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,45 +168,45 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 101705 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684617 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1157 system.cpu0.kern.mode_good_user 1158 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7091 # number of protection mode switches system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -238,10 +238,10 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.numCycles 3740670933 # number of cpu cycles simulated -system.cpu0.num_insts 57181549 # Number of instructions executed -system.cpu0.num_refs 15322361 # Number of memory references +system.cpu0.num_insts 57222076 # Number of instructions executed +system.cpu0.num_refs 15330887 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -306,7 +306,7 @@ system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu1.dcache.replacements 62338 # number of replacements system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 30848 # number of writebacks @@ -529,33 +529,33 @@ system.iocache.tagsinuse 0.435437 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759609 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964534 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759731 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 964536 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 427641 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. +system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1759609 # number of demand (read+write) hits +system.l2c.demand_hits 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270778 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses +system.l2c.demand_misses 1270783 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1759609 # number of overall hits +system.l2c.overall_hits 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270778 # number of overall misses +system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses +system.l2c.overall_misses 1270783 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056800 # number of replacements -system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. +system.l2c.replacements 1056803 # number of replacements +system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use -system.l2c.total_refs 1952731 # Total number of references to valid blocks. +system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use +system.l2c.total_refs 1952499 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123878 # number of writebacks +system.l2c.writebacks 123882 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal index c2aeea3f1..6129834bd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal @@ -60,6 +60,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -71,6 +72,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 6989105c7..2ea90534e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:01 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:54 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1828355695500 because m5_exit instruction encountered +Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8c53afda6..19b0c43d9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2786128 # Simulator instruction rate (inst/s) -host_mem_usage 289464 # Number of bytes of host memory used -host_seconds 21.53 # Real time elapsed on the host -host_tick_rate 84905818409 # Simulator tick rate (ticks/s) +host_inst_rate 1610025 # Simulator instruction rate (inst/s) +host_mem_usage 290828 # Number of bytes of host memory used +host_seconds 37.29 # Real time elapsed on the host +host_tick_rate 49056237387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995351 # Number of instructions simulated -sim_seconds 1.828356 # Number of seconds simulated -sim_ticks 1828355695500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses +sim_insts 60038305 # Number of instructions simulated +sim_seconds 1.829332 # Number of seconds simulated +sim_ticks 1829332258000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses +system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552138 # number of overall hits +system.cpu.dcache.overall_hits 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121104 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042676 # number of replacements -system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428892 # number of writebacks +system.cpu.dcache.writebacks 428893 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16062925 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087131 # number of overall hits +system.cpu.icache.overall_hits 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920058 # number of overall misses +system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_misses 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919431 # number of replacements -system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919594 # number of replacements +system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use -system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use +system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979228 # ITB accesses +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.itb.accesses 4979654 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974222 # ITB hits +system.cpu.itb.hits 4974648 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192140 # number of callpals executed +system.cpu.kern.callpal 192180 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -157,50 +157,50 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1866 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149035 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80238000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.695521 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1909 system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5949 # number of protection mode switches system.cpu.kern.mode_switch_user 1738 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -233,10 +233,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656711283 # number of cpu cycles simulated -system.cpu.num_insts 59995351 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.num_insts 60038305 # Number of instructions executed +system.cpu.num_refs 16311238 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226225 # Cycle average of tags in use +system.iocache.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696464 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses +system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428892 # number of Writeback hits +system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428893 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. +system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency -system.l2c.demand_hits 1696464 # number of demand (read+write) hits +system.l2c.demand_hits 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses -system.l2c.demand_misses 1266766 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses +system.l2c.demand_misses 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.l2c.overall_hits 1696464 # number of overall hits +system.l2c.overall_hits 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses -system.l2c.overall_misses 1266766 # number of overall misses +system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses +system.l2c.overall_misses 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050731 # number of replacements -system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. +system.l2c.replacements 1050724 # number of replacements +system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use -system.l2c.total_refs 1866797 # Total number of references to valid blocks. +system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use +system.l2c.total_refs 1867269 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119150 # number of writebacks +system.l2c.writebacks 119147 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal index 7930e9e46..f17158b67 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 06723d964..9f8bf8070 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:12 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:52 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1972135479000 because m5_exit instruction encountered +Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 39aa94315..2f2449fdc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1388930 # Simulator instruction rate (inst/s) -host_mem_usage 287800 # Number of bytes of host memory used -host_seconds 42.75 # Real time elapsed on the host -host_tick_rate 46129218174 # Simulator tick rate (ticks/s) +host_inst_rate 741695 # Simulator instruction rate (inst/s) +host_mem_usage 289172 # Number of bytes of host memory used +host_seconds 80.11 # Real time elapsed on the host +host_tick_rate 24616375840 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59379829 # Number of instructions simulated +sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated -sim_ticks 1972135479000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses +sim_ticks 1972135461000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12909668 # number of overall hits -system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1417993 # number of overall misses +system.cpu0.dcache.overall_hits 12917865 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417958 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1338626 # number of replacements -system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1338610 # number of replacements +system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 503.609177 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403562 # number of writebacks +system.cpu0.dcache.writebacks 403520 # number of writebacks system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 14696400 # DTB hits +system.cpu0.dtb.hits 14704826 # DTB hits system.cpu0.dtb.misses 8485 # DTB misses system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8658591 # DTB read hits +system.cpu0.dtb.read_hits 8664724 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6037809 # DTB write hits +system.cpu0.dtb.write_hits 6040102 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_accesses 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016917 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency -system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses -system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916324 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 53208030 # number of overall hits -system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses -system.cpu0.icache.overall_misses 916222 # number of overall misses +system.cpu0.icache.overall_hits 53248092 # number of overall hits +system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916324 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,19 +171,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 915582 # number of replacements -system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 915684 # number of replacements +system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 508.642782 # Cycle average of tags in use +system.cpu0.icache.total_refs 53248092 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles -system.cpu0.itb.accesses 3953623 # ITB accesses +system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles +system.cpu0.itb.accesses 3953747 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3949782 # ITB hits +system.cpu0.itb.hits 3949906 # ITB hits system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187998 # number of callpals executed +system.cpu0.kern.callpal 188012 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed @@ -191,8 +191,8 @@ system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # nu system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.13% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172068 91.52% 93.65% # number of callpals executed system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed @@ -202,43 +202,43 @@ system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # nu system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178906 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72641 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 104141 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134703000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96186500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576952000 0.03% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981154 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1232 -system.cpu0.kern.mode_good_user 1233 +system.cpu0.kern.ipl_used_31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1231 +system.cpu0.kern.mode_good_user 1232 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1232 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170098 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804198000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3869 # number of times the context was actually changed system.cpu0.kern.syscall 224 # number of syscalls executed @@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles -system.cpu0.numCycles 3944270958 # number of cpu cycles simulated -system.cpu0.num_insts 54115477 # Number of instructions executed -system.cpu0.num_refs 14937789 # Number of memory references +system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270922 # number of cpu cycles simulated +system.cpu0.num_insts 54155641 # Number of instructions executed +system.cpu0.num_refs 14946215 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.083347 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_hits 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035021 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency +system.cpu1.dcache.StoreCondReq_accesses 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1608374 # number of overall hits -system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 62122 # number of overall misses +system.cpu1.dcache.overall_hits 1608459 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62092 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 53749 # number of replacements -system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 53724 # number of replacements +system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26833 # number of writebacks +system.cpu1.dcache.tagsinuse 388.878897 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26831 # number of writebacks system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1693796 # DTB hits +system.cpu1.dtb.hits 1693851 # DTB hits system.cpu1.dtb.misses 3106 # DTB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1029675 # DTB read hits +system.cpu1.dtb.read_hits 1029710 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 664121 # DTB write hits +system.cpu1.dtb.write_hits 664141 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016597 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses -system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87436 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5180112 # number of overall hits -system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses -system.cpu1.icache.overall_misses 87430 # number of overall misses +system.cpu1.icache.overall_hits 5180706 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87436 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -439,19 +439,19 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 86890 # number of replacements -system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 86896 # number of replacements +system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use -system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 419.405627 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180706 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles -system.cpu1.itb.accesses 1397499 # ITB accesses +system.cpu1.itb.accesses 1397517 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1396253 # ITB hits +system.cpu1.itb.hits 1396271 # ITB hits system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29501 # number of callpals executed +system.cpu1.kern.callpal 29503 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed @@ -459,7 +459,7 @@ system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24144 81.84% 83.16% # number of callpals executed system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed @@ -470,27 +470,27 @@ system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # nu system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count 28810 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9173 31.84% 31.84% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 17566 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20310 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511194500 0.03% 97.81% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.516566 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 532 system.cpu1.kern.mode_good_user 516 system.cpu1.kern.mode_good_idle 16 @@ -501,9 +501,9 @@ system.cpu1.kern.mode_switch_good 1.612234 # fr system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703543000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed @@ -529,8 +529,8 @@ system.cpu1.kern.syscall_132 2 1.96% 99.02% # nu system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles system.cpu1.numCycles 3943367734 # number of cpu cycles simulated -system.cpu1.num_insts 5264352 # Number of instructions executed -system.cpu1.num_refs 1703685 # Number of memory references +system.cpu1.num_insts 5264952 # Number of instructions executed +system.cpu1.num_refs 1703740 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -553,46 +553,46 @@ system.iocache.ReadReq_mshr_miss_latency 11248998 # nu system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6169.706090 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64528956 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41730 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41730 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles +system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -609,80 +609,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41698 # number of replacements system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.582076 # Cycle average of tags in use +system.iocache.tagsinuse 0.582075 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 306814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.656333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 306814 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.275832 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782800 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307447 # number of ReadReq misses +system.l2c.ReadReq_hits 1782886 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147069 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307419 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430395 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430351 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. +system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency -system.l2c.demand_hits 1782800 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses -system.l2c.demand_misses 614243 # number of demand (read+write) misses +system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency +system.l2c.demand_hits 1782886 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses +system.l2c.demand_misses 614233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782800 # number of overall hits -system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses -system.l2c.overall_misses 614243 # number of overall misses +system.l2c.overall_hits 1782886 # number of overall hits +system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses +system.l2c.overall_misses 614233 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 399043 # number of replacements -system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. +system.l2c.replacements 399005 # number of replacements +system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use -system.l2c.total_refs 1963771 # Total number of references to valid blocks. +system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use +system.l2c.total_refs 1961635 # Total number of references to valid blocks. system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123178 # number of writebacks +system.l2c.writebacks 123162 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index 6974143c8..7399f4d84 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -61,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -72,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index b4ba00cf0..b196d52a3 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:43 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:59 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1930165791000 because m5_exit instruction encountered +Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index bcad4cd62..76e60eed0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1283720 # Simulator instruction rate (inst/s) -host_mem_usage 286560 # Number of bytes of host memory used -host_seconds 43.75 # Real time elapsed on the host -host_tick_rate 44115985890 # Simulator tick rate (ticks/s) +host_inst_rate 715830 # Simulator instruction rate (inst/s) +host_mem_usage 287924 # Number of bytes of host memory used +host_seconds 78.52 # Real time elapsed on the host +host_tick_rate 24582295405 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56165112 # Number of instructions simulated -sim_seconds 1.930166 # Number of seconds simulated -sim_ticks 1930165791000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency +sim_insts 56205703 # Number of instructions simulated +sim_seconds 1.930165 # Number of seconds simulated +sim_ticks 1930164593000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13569826 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1471004 # number of overall misses +system.cpu.dcache.overall_hits 13577961 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471029 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1391586 # number of replacements -system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1391606 # number of replacements +system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use -system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use +system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430461 # number of writebacks +system.cpu.dcache.writebacks 430459 # number of writebacks system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 15421361 # DTB hits +system.cpu.dtb.hits 15429793 # DTB hits system.cpu.dtb.misses 11466 # DTB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9063577 # DTB read hits +system.cpu.dtb.read_hits 9069700 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6357784 # DTB write hits +system.cpu.dtb.write_hits 6360093 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency -system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses -system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 55246023 # number of overall hits -system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses -system.cpu.icache.overall_misses 930923 # number of overall misses +system.cpu.icache.overall_hits 55286436 # number of overall hits +system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_misses 931101 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,19 +171,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 930251 # number of replacements -system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930429 # number of replacements +system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use -system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use +system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929251 # Percentage of idle cycles -system.cpu.itb.accesses 4982832 # ITB accesses +system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.itb.accesses 4982987 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4977822 # ITB hits +system.cpu.itb.hits 4977977 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193204 # number of callpals executed +system.cpu.kern.callpal 193221 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -191,7 +191,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_swpipl 176257 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed @@ -201,40 +201,40 @@ system.cpu.kern.callpal_rti 5169 2.68% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183502 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75001 40.87% 40.87% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 106426 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149343 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930163835000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96331500 0.00% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565310500 0.03% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981774 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1910 -system.cpu.kern.mode_good_user 1743 +system.cpu.kern.ipl_used_31 0.691880 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1744 system.cpu.kern.mode_good_idle 167 system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches -system.cpu.kern.mode_switch_user 1743 # number of protection mode switches +system.cpu.kern.mode_switch_user 1744 # number of protection mode switches system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402910 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322968 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5539986000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4172 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles -system.cpu.numCycles 3860331582 # number of cpu cycles simulated -system.cpu.num_insts 56165112 # Number of instructions executed -system.cpu.num_refs 15669461 # Number of memory references +system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles +system.cpu.numCycles 3860329186 # number of cpu cycles simulated +system.cpu.num_insts 56205703 # Number of instructions executed +system.cpu.num_refs 15677891 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -293,46 +293,46 @@ system.iocache.ReadReq_mshr_miss_latency 10942998 # nu system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6163.674943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64546004 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles +system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353410 # Cycle average of tags in use +system.iocache.tagsinuse 1.353399 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1710772 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307605 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1710971 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307593 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430461 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430459 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. +system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency -system.l2c.demand_hits 1710772 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses -system.l2c.demand_misses 612230 # number of demand (read+write) misses +system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.demand_hits 1710971 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses +system.l2c.demand_misses 612229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1710772 # number of overall hits -system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses -system.l2c.overall_misses 612230 # number of overall misses +system.l2c.overall_hits 1710971 # number of overall hits +system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses +system.l2c.overall_misses 612229 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 394925 # number of replacements -system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. +system.l2c.replacements 394928 # number of replacements +system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use -system.l2c.total_refs 1889516 # Total number of references to valid blocks. +system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use +system.l2c.total_refs 1889545 # Total number of references to valid blocks. system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119047 # number of writebacks +system.l2c.writebacks 119060 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 3efa225a8..ff644ed3f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -56,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -67,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 3e554a663..3bf761d34 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-server.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -703,7 +703,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-stream-client.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal index 89c68d228..5501b27d6 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index b7a61e7b4..361a090ba 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:27 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:48:20 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 3a06809c5..80d312c00 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -139,12 +139,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 200792296 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used -host_seconds 1.36 # Real time elapsed on the host -host_tick_rate 146922204609 # Simulator tick rate (ticks/s) +host_inst_rate 184651715 # Simulator instruction rate (inst/s) +host_mem_usage 478008 # Number of bytes of host memory used +host_seconds 1.48 # Real time elapsed on the host +host_tick_rate 135077074315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses @@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 214516622449 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used +host_inst_rate 161951915284 # Simulator instruction rate (inst/s) +host_mem_usage 478008 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 582637509 # Simulator tick rate (ticks/s) +host_tick_rate 438603795 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal index c1cb6aad0..ecae2497e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 loop: loaded (max 8 devices) nbd: registered device at major 43 ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + PCI: Setting latency timer of device 0000:00:01.0 to 64 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 PIIX4: IDE controller at PCI slot 0000:00:00.0 PIIX4: chipset revision 0 PIIX4: 100% native mode on irq 31 + PCI: Setting latency timer of device 0000:00:00.0 to 64 ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA hda: M5 IDE Disk, ATA DISK drive -- cgit v1.2.3 From fb572a1d7445adb91bba588c29fff18b1d8b88b7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 17 Jan 2009 18:57:39 -0500 Subject: Stats: Update parser statistics for Linux special files update (parser runs should now be deterministic). --- .../ref/x86/linux/simple-atomic/config.ini | 2 + .../20.parser/ref/x86/linux/simple-atomic/simout | 12 ++--- .../ref/x86/linux/simple-atomic/stats.txt | 18 +++---- .../ref/x86/linux/simple-timing/config.ini | 4 +- .../20.parser/ref/x86/linux/simple-timing/simout | 14 ++--- .../ref/x86/linux/simple-timing/stats.txt | 60 +++++++++++----------- 6 files changed, 57 insertions(+), 53 deletions(-) (limited to 'tests') diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 300a3a0b4..21fdad99e 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,8 @@ children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 90786ddde..110848279 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:22:32 +M5 compiled Jan 16 2009 20:04:39 +M5 revision Unknown:Unknown +M5 commit date Unknown +M5 started Jan 16 2009 21:36:48 M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -72,4 +72,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868687490500 because target called exit() +Exiting @ tick 868687391000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 6c9e86c42..547b9bbcd 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1589069 # Simulator instruction rate (inst/s) -host_mem_usage 198676 # Number of bytes of host memory used -host_seconds 941.11 # Real time elapsed on the host -host_tick_rate 923042875 # Simulator tick rate (ticks/s) +host_inst_rate 1452666 # Simulator instruction rate (inst/s) +host_mem_usage 201308 # Number of bytes of host memory used +host_seconds 1029.48 # Real time elapsed on the host +host_tick_rate 843810674 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492702 # Number of instructions simulated +sim_insts 1495492527 # Number of instructions simulated sim_seconds 0.868687 # Number of seconds simulated -sim_ticks 868687490500 # Number of ticks simulated +sim_ticks 868687391000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737374982 # number of cpu cycles simulated -system.cpu.num_insts 1495492702 # Number of instructions executed -system.cpu.num_refs 533549000 # Number of memory references +system.cpu.numCycles 1737374783 # number of cpu cycles simulated +system.cpu.num_insts 1495492527 # Number of instructions executed +system.cpu.num_refs 533548974 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index d6948bfb4..bcc04f400 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -15,6 +15,8 @@ children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -155,7 +157,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index f24226fff..c73c77520 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2008 18:23:31 -M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e -M5 commit date Sat Nov 08 21:06:07 2008 -0800 -M5 started Nov 9 2008 18:34:37 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing +M5 compiled Jan 16 2009 20:04:39 +M5 revision Unknown:Unknown +M5 commit date Unknown +M5 started Jan 16 2009 21:37:18 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -72,4 +72,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2391380378000 because target called exit() +Exiting @ tick 2391380158000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 803dc9bdb..ddf39d868 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,27 +1,27 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 588841 # Simulator instruction rate (inst/s) -host_mem_usage 206816 # Number of bytes of host memory used -host_seconds 2539.72 # Real time elapsed on the host -host_tick_rate 941590971 # Simulator tick rate (ticks/s) +host_inst_rate 1062568 # Simulator instruction rate (inst/s) +host_mem_usage 208792 # Number of bytes of host memory used +host_seconds 1407.43 # Real time elapsed on the host +host_tick_rate 1699108877 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492697 # Number of instructions simulated +sim_insts 1495492527 # Number of instructions simulated sim_seconds 2.391380 # Number of seconds simulated -sim_ticks 2391380378000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses) +sim_ticks 2391380158000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 382375372 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 147694052 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # m system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 210.782576 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 533262385 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 530069424 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 3192961 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 533262385 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069450 # number of overall hits +system.cpu.dcache.overall_hits 530069424 # number of overall hits system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses system.cpu.dcache.overall_misses 3192961 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use -system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.151091 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744414 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1737374721 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1737371908 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 617622.434412 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1737374721 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1737371908 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1737374721 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1737372102 # number of overall hits +system.cpu.icache.overall_hits 1737371908 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use -system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 873.848487 # Cycle average of tags in use +system.cpu.icache.total_refs 1737371908 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17171.686345 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4782760756 # number of cpu cycles simulated -system.cpu.num_insts 1495492697 # Number of instructions executed -system.cpu.num_refs 533549000 # Number of memory references +system.cpu.numCycles 4782760316 # number of cpu cycles simulated +system.cpu.num_insts 1495492527 # Number of instructions executed +system.cpu.num_refs 533548974 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3 From d824af340ec98a9d7ac34a3c358666191df1f83f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Feb 2009 17:02:16 -0800 Subject: X86: Update stats now that the micropc isn't always reset on faults. --- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 2 +- .../00.gzip/ref/x86/linux/simple-atomic/simout | 14 ++--- .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 20 +++---- .../00.gzip/ref/x86/linux/simple-timing/config.ini | 2 +- .../00.gzip/ref/x86/linux/simple-timing/simout | 14 ++--- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 60 ++++++++++----------- .../10.mcf/ref/x86/linux/simple-atomic/config.ini | 2 +- .../long/10.mcf/ref/x86/linux/simple-atomic/simout | 14 ++--- .../10.mcf/ref/x86/linux/simple-atomic/stats.txt | 18 +++---- .../10.mcf/ref/x86/linux/simple-timing/config.ini | 2 +- .../long/10.mcf/ref/x86/linux/simple-timing/simout | 14 ++--- .../10.mcf/ref/x86/linux/simple-timing/stats.txt | 42 +++++++-------- .../ref/x86/linux/simple-atomic/config.ini | 1 + .../20.parser/ref/x86/linux/simple-atomic/simerr | 8 +-- .../20.parser/ref/x86/linux/simple-atomic/simout | 16 +++--- .../ref/x86/linux/simple-atomic/stats.txt | 20 +++---- .../ref/x86/linux/simple-timing/config.ini | 1 + .../20.parser/ref/x86/linux/simple-timing/simerr | 8 +-- .../20.parser/ref/x86/linux/simple-timing/simout | 16 +++--- .../ref/x86/linux/simple-timing/stats.txt | 62 +++++++++++----------- .../ref/x86/linux/simple-atomic/config.ini | 2 +- .../60.bzip2/ref/x86/linux/simple-atomic/simout | 14 ++--- .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt | 18 +++---- .../ref/x86/linux/simple-timing/config.ini | 2 +- .../60.bzip2/ref/x86/linux/simple-timing/simout | 14 ++--- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 44 +++++++-------- .../ref/x86/linux/simple-atomic/config.ini | 2 +- .../70.twolf/ref/x86/linux/simple-atomic/simout | 18 +++---- .../70.twolf/ref/x86/linux/simple-atomic/stats.txt | 16 +++--- .../70.twolf/ref/x86/linux/simple-timing/simout | 14 ++--- .../70.twolf/ref/x86/linux/simple-timing/stats.txt | 38 ++++++------- .../00.hello/ref/x86/linux/simple-atomic/simout | 14 ++--- .../00.hello/ref/x86/linux/simple-atomic/stats.txt | 16 +++--- .../00.hello/ref/x86/linux/simple-timing/simout | 14 ++--- .../00.hello/ref/x86/linux/simple-timing/stats.txt | 50 ++++++++--------- 35 files changed, 309 insertions(+), 303 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index fb96ff412..93e326b16 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 7b8dadcc0..81b1be1e0 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:03:28 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:19:42 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 962951801000 because target called exit() +Exiting @ tick 962935342000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 4f9664bbc..fcdb37b5a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1613706 # Simulator instruction rate (inst/s) -host_mem_usage 195008 # Number of bytes of host memory used -host_seconds 1003.53 # Real time elapsed on the host -host_tick_rate 959566027 # Simulator tick rate (ticks/s) +host_inst_rate 717061 # Simulator instruction rate (inst/s) +host_mem_usage 197184 # Number of bytes of host memory used +host_seconds 2258.34 # Real time elapsed on the host +host_tick_rate 426391006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 0.962952 # Number of seconds simulated -sim_ticks 962951801000 # Number of ticks simulated +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 0.962935 # Number of seconds simulated +sim_ticks 962935342000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925903603 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 1925870685 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 7d5cc5629..4630d922d 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 5b0e0d9ff..7f0c2942c 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:23:58 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:22:06 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554132875000 because target called exit() +Exiting @ tick 2554098117000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 76b073830..89a1a5647 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159099 # Simulator instruction rate (inst/s) -host_mem_usage 201888 # Number of bytes of host memory used -host_seconds 1397.12 # Real time elapsed on the host -host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +host_inst_rate 511923 # Simulator instruction rate (inst/s) +host_mem_usage 204640 # Number of bytes of host memory used +host_seconds 3163.30 # Real time elapsed on the host +host_tick_rate 807415286 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 2.554133 # Number of seconds simulated -sim_ticks 2554132875000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 2.554098 # Number of seconds simulated +sim_ticks 2554098117000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # m system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 506099 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_hits 606642715 # number of overall hits system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses system.cpu.dcache.overall_misses 506099 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use -system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.609383 # Cycle average of tags in use +system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1593417000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1925870644 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1925869923 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2671109.463245 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1925870644 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1925869923 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 721 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1925870644 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_hits 1925869923 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use -system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 658.724449 # Cycle average of tags in use +system.cpu.icache.total_refs 1925869923 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16428.000401 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108265750 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 5108196234 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 7f2a4c792..40541f366 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 195b58e3f..c22c368b8 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:20:12 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:05:48 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165731691000 because target called exit() +Exiting @ tick 165726426000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index ee5db6e3c..a4a7be0d1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1935457 # Simulator instruction rate (inst/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 139.35 # Real time elapsed on the host -host_tick_rate 1189355805 # Simulator tick rate (ticks/s) +host_inst_rate 687504 # Simulator instruction rate (inst/s) +host_mem_usage 331712 # Number of bytes of host memory used +host_seconds 392.27 # Real time elapsed on the host +host_tick_rate 422480782 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.165732 # Number of seconds simulated -sim_ticks 165731691000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.165726 # Number of seconds simulated +sim_ticks 165726426000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331463383 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 331452853 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 106b52826..2447a5715 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index a552023cf..5e04da3a3 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 13 2008 21:51:42 -M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 -M5 commit date Sun Nov 09 21:57:15 2008 -0800 -M5 started Nov 13 2008 21:51:43 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 20:14:49 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 495387670000 because target called exit() +Exiting @ tick 495377140000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 94a44a507..2fa37b8f7 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1084581 # Simulator instruction rate (inst/s) -host_mem_usage 336400 # Number of bytes of host memory used -host_seconds 248.67 # Real time elapsed on the host -host_tick_rate 1992187591 # Simulator tick rate (ticks/s) +host_inst_rate 422356 # Simulator instruction rate (inst/s) +host_mem_usage 339176 # Number of bytes of host memory used +host_seconds 638.53 # Real time elapsed on the host +host_tick_rate 775808629 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.495388 # Number of seconds simulated -sim_ticks 495387670000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.495377 # Number of seconds simulated +sim_ticks 495377140000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits +system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331462528 # number of overall hits +system.cpu.icache.overall_hits 331451998 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use -system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use +system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990775340 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 990754280 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 21fdad99e..dd5474f9a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -12,6 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 110848279..08a12f2a0 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 16 2009 20:04:39 -M5 revision Unknown:Unknown -M5 commit date Unknown -M5 started Jan 16 2009 21:36:48 -M5 executing on zizzer +M5 compiled Feb 1 2009 00:35:14 +M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase +M5 started Feb 1 2009 01:31:23 +M5 executing on fajita command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ************************************************* + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** 58924 words stored in 3784810 bytes @@ -28,6 +28,8 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +74,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868687391000 because target called exit() +Exiting @ tick 868682305500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 547b9bbcd..9ef20eecb 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1452666 # Simulator instruction rate (inst/s) -host_mem_usage 201308 # Number of bytes of host memory used -host_seconds 1029.48 # Real time elapsed on the host -host_tick_rate 843810674 # Simulator tick rate (ticks/s) +host_inst_rate 942344 # Simulator instruction rate (inst/s) +host_mem_usage 199592 # Number of bytes of host memory used +host_seconds 1586.98 # Real time elapsed on the host +host_tick_rate 547379933 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492527 # Number of instructions simulated -sim_seconds 0.868687 # Number of seconds simulated -sim_ticks 868687391000 # Number of ticks simulated +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 0.868682 # Number of seconds simulated +sim_ticks 868682305500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737374783 # number of cpu cycles simulated -system.cpu.num_insts 1495492527 # Number of instructions executed -system.cpu.num_refs 533548974 # Number of memory references +system.cpu.numCycles 1737364612 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533548971 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index bcc04f400..793578856 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -12,6 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index c73c77520..3b8d98147 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 16 2009 20:04:39 -M5 revision Unknown:Unknown -M5 commit date Unknown -M5 started Jan 16 2009 21:37:18 -M5 executing on zizzer +M5 compiled Feb 1 2009 00:35:14 +M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase +M5 started Feb 1 2009 01:51:40 +M5 executing on fajita command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ************************************************* + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** 58924 words stored in 3784810 bytes @@ -28,6 +28,8 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +74,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2391380158000 because target called exit() +Exiting @ tick 2391369984000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index ddf39d868..c473a6423 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1062568 # Simulator instruction rate (inst/s) -host_mem_usage 208792 # Number of bytes of host memory used -host_seconds 1407.43 # Real time elapsed on the host -host_tick_rate 1699108877 # Simulator tick rate (ticks/s) +host_inst_rate 856633 # Simulator instruction rate (inst/s) +host_mem_usage 207060 # Number of bytes of host memory used +host_seconds 1745.77 # Real time elapsed on the host +host_tick_rate 1369809690 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492527 # Number of instructions simulated -sim_seconds 2.391380 # Number of seconds simulated -sim_ticks 2391380158000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102185 # number of ReadReq accesses(hits+misses) +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 2.391370 # Number of seconds simulated +sim_ticks 2391369984000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382375372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # m system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.782576 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 3192961 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 533262385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069424 # number of overall hits +system.cpu.dcache.overall_hits 530069421 # number of overall hits system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses system.cpu.dcache.overall_misses 3192961 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.151091 # Cycle average of tags in use -system.cpu.dcache.total_refs 530744414 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1737374721 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1737371908 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617622.434412 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1737374721 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1737371908 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1737374721 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1737371908 # number of overall hits +system.cpu.icache.overall_hits 1737361737 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.848487 # Cycle average of tags in use -system.cpu.icache.total_refs 1737371908 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use +system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.686345 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4782760316 # number of cpu cycles simulated -system.cpu.num_insts 1495492527 # Number of instructions executed -system.cpu.num_refs 533548974 # Number of memory references +system.cpu.numCycles 4782739968 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533548971 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3a2c48ff2..13ff2455f 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index bedb92044..346eca640 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:38:14 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 20:02:35 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2835210954000 because target called exit() +Exiting @ tick 2835189187500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index a2bce703e..d428992be 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2012716 # Simulator instruction rate (inst/s) -host_mem_usage 194900 # Number of bytes of host memory used -host_seconds 2311.91 # Real time elapsed on the host -host_tick_rate 1226349708 # Simulator tick rate (ticks/s) +host_inst_rate 896643 # Simulator instruction rate (inst/s) +host_mem_usage 197076 # Number of bytes of host memory used +host_seconds 5189.55 # Real time elapsed on the host +host_tick_rate 546326494 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 2.835211 # Number of seconds simulated -sim_ticks 2835210954000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 2.835189 # Number of seconds simulated +sim_ticks 2835189187500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5670421909 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.numCycles 5670378376 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index caa9f8677..64329243b 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index c5e3246b3..f677c72d6 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 10:43:38 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 18:30:11 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 7645253019000 because target called exit() +Exiting @ tick 7645209486000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 5c98d4cbd..6bbf1280e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1139442 # Simulator instruction rate (inst/s) -host_mem_usage 201800 # Number of bytes of host memory used -host_seconds 4083.77 # Real time elapsed on the host -host_tick_rate 1872105757 # Simulator tick rate (ticks/s) +host_inst_rate 483951 # Simulator instruction rate (inst/s) +host_mem_usage 204540 # Number of bytes of host memory used +host_seconds 9614.98 # Real time elapsed on the host +host_tick_rate 795135330 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 7.645253 # Number of seconds simulated -sim_ticks 7645253019000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 7.645209 # Number of seconds simulated +sim_ticks 7645209486000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.377593 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 78020119000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 5670378338 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5670377663 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8400559.500741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5670378338 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5670377663 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5670378338 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5670421196 # number of overall hits +system.cpu.icache.overall_hits 5670377663 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use -system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.334555 # Cycle average of tags in use +system.cpu.icache.total_refs 5670377663 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25740.146811 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 6038871723000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15290506038 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.numCycles 15290418972 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index a50589b32..b8de37bf3 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 1d99c3015..eea857771 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:16:46 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:57:21 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009373500 because target called exit() +122 123 124 Exiting @ tick 130009362500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 2581f730b..90a051575 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2311586 # Simulator instruction rate (inst/s) -host_mem_usage 202280 # Number of bytes of host memory used -host_seconds 94.57 # Real time elapsed on the host -host_tick_rate 1374811015 # Simulator tick rate (ticks/s) +host_inst_rate 697777 # Simulator instruction rate (inst/s) +host_mem_usage 204448 # Number of bytes of host memory used +host_seconds 313.27 # Real time elapsed on the host +host_tick_rate 415001936 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated +sim_insts 218595300 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009373500 # Number of ticks simulated +sim_ticks 130009362500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018748 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.numCycles 260018726 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165364 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 764f17d51..6c4741848 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2008 18:23:31 -M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e -M5 commit date Sat Nov 08 21:06:07 2008 -0800 -M5 started Nov 9 2008 18:29:22 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:12:20 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469714000 because target called exit() +122 123 124 Exiting @ tick 337469692000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 897f4bc38..91975530b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 937563 # Simulator instruction rate (inst/s) -host_mem_usage 210412 # Number of bytes of host memory used -host_seconds 233.15 # Real time elapsed on the host -host_tick_rate 1447418160 # Simulator tick rate (ticks/s) +host_inst_rate 495446 # Simulator instruction rate (inst/s) +host_mem_usage 211916 # Number of bytes of host memory used +host_seconds 441.21 # Real time elapsed on the host +host_tick_rate 764874761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated +sim_insts 218595300 # Number of instructions simulated sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469714000 # Number of ticks simulated +sim_ticks 337469692000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.541033 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 260018574 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 260013881 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # ms system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 55404.619859 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 260018574 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits +system.cpu.icache.demand_hits 260013881 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 4693 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 260018574 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013903 # number of overall hits +system.cpu.icache.overall_hits 260013881 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use -system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1453.991128 # Cycle average of tags in use +system.cpu.icache.total_refs 260013881 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2031.720476 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939428 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.numCycles 674939384 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165364 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 7fa8be29e..66f32751d 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:18:22 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 18:30:07 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5518000 because target called exit() +Exiting @ tick 5513500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 3c3c458ce..2ee3e5703 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 557395 # Simulator instruction rate (inst/s) -host_mem_usage 190704 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 320851262 # Simulator tick rate (ticks/s) +host_inst_rate 5132 # Simulator instruction rate (inst/s) +host_mem_usage 192872 # Number of bytes of host memory used +host_seconds 1.85 # Real time elapsed on the host +host_tick_rate 2983162 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated +sim_insts 9484 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5518000 # Number of ticks simulated +sim_ticks 5513500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11037 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.numCycles 11028 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 9c811f04f..e9fb59225 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:19:20 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:57:21 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33851000 because target called exit() +Exiting @ tick 33842000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index cb9de2cde..4bf18211b 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106773 # Simulator instruction rate (inst/s) -host_mem_usage 197592 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 379942758 # Simulator tick rate (ticks/s) +host_inst_rate 494241 # Simulator instruction rate (inst/s) +host_mem_usage 200332 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1743803782 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated +sim_insts 9484 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33851000 # Number of ticks simulated +sim_ticks 33842000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 81.592815 # Cycle average of tags in use system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 10998 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 10770 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.020731 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.020731 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 47.236842 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 10998 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits +system.cpu.icache.demand_hits 10770 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.020731 # miss rate for demand accesses system.cpu.icache.demand_misses 228 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.020731 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 10998 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10779 # number of overall hits +system.cpu.icache.overall_hits 10770 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.020731 # miss rate for overall accesses system.cpu.icache.overall_misses 228 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.020731 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use -system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 107.523643 # Cycle average of tags in use +system.cpu.icache.total_refs 10770 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -219,13 +219,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 129.119087 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67702 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.numCycles 67684 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls -- cgit v1.2.3 From 89ea32325094665c16688212b5a2cd7b7bbf5f03 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 16 Feb 2009 12:09:45 -0500 Subject: Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway. --- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 12 +- .../long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 2 +- .../long/00.gzip/ref/alpha/tru64/o3-timing/simout | 10 +- .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../00.gzip/ref/alpha/tru64/simple-atomic/simerr | 2 +- .../00.gzip/ref/alpha/tru64/simple-atomic/simout | 10 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../00.gzip/ref/alpha/tru64/simple-timing/simerr | 2 +- .../00.gzip/ref/alpha/tru64/simple-timing/simout | 10 +- .../ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../00.gzip/ref/sparc/linux/o3-timing/config.ini | 12 +- .../long/00.gzip/ref/sparc/linux/o3-timing/simerr | 3 +- .../long/00.gzip/ref/sparc/linux/o3-timing/simout | 9 +- .../00.gzip/ref/sparc/linux/o3-timing/stats.txt | 35 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../00.gzip/ref/sparc/linux/simple-atomic/simerr | 3 +- .../00.gzip/ref/sparc/linux/simple-atomic/simout | 9 +- .../ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../00.gzip/ref/sparc/linux/simple-timing/simerr | 3 +- .../00.gzip/ref/sparc/linux/simple-timing/simout | 9 +- .../ref/sparc/linux/simple-timing/stats.txt | 35 +- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 5 +- .../00.gzip/ref/x86/linux/simple-atomic/simerr | 10 +- .../00.gzip/ref/x86/linux/simple-atomic/simout | 12 +- .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 8 +- .../00.gzip/ref/x86/linux/simple-timing/config.ini | 14 +- .../00.gzip/ref/x86/linux/simple-timing/simerr | 10 +- .../00.gzip/ref/x86/linux/simple-timing/simout | 12 +- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 35 +- .../ref/alpha/linux/tsunami-o3-dual/config.ini | 34 +- .../ref/alpha/linux/tsunami-o3-dual/simerr | 6 +- .../ref/alpha/linux/tsunami-o3-dual/simout | 10 +- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 62 +-- .../ref/alpha/linux/tsunami-o3/config.ini | 27 +- .../ref/alpha/linux/tsunami-o3/simerr | 5 +- .../ref/alpha/linux/tsunami-o3/simout | 10 +- .../ref/alpha/linux/tsunami-o3/stats.txt | 44 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../10.mcf/ref/sparc/linux/simple-atomic/simerr | 3 +- .../10.mcf/ref/sparc/linux/simple-atomic/simout | 9 +- .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../10.mcf/ref/sparc/linux/simple-timing/simerr | 3 +- .../10.mcf/ref/sparc/linux/simple-timing/simout | 9 +- .../10.mcf/ref/sparc/linux/simple-timing/stats.txt | 35 +- .../10.mcf/ref/x86/linux/simple-atomic/config.ini | 5 +- .../long/10.mcf/ref/x86/linux/simple-atomic/simerr | 5 +- .../long/10.mcf/ref/x86/linux/simple-atomic/simout | 11 +- .../10.mcf/ref/x86/linux/simple-atomic/stats.txt | 8 +- .../10.mcf/ref/x86/linux/simple-timing/config.ini | 14 +- .../long/10.mcf/ref/x86/linux/simple-timing/simerr | 5 +- .../long/10.mcf/ref/x86/linux/simple-timing/simout | 11 +- .../10.mcf/ref/x86/linux/simple-timing/stats.txt | 35 +- .../20.parser/ref/x86/linux/simple-atomic/simout | 8 +- .../ref/x86/linux/simple-atomic/stats.txt | 8 +- .../ref/x86/linux/simple-timing/config.ini | 9 +- .../20.parser/ref/x86/linux/simple-timing/simout | 8 +- .../ref/x86/linux/simple-timing/stats.txt | 35 +- .../30.eon/ref/alpha/tru64/o3-timing/config.ini | 12 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr | 3 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 11 +- .../30.eon/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../30.eon/ref/alpha/tru64/simple-atomic/simerr | 3 +- .../30.eon/ref/alpha/tru64/simple-atomic/simout | 11 +- .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../30.eon/ref/alpha/tru64/simple-timing/simerr | 3 +- .../30.eon/ref/alpha/tru64/simple-timing/simout | 11 +- .../30.eon/ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../ref/alpha/tru64/o3-timing/config.ini | 12 +- .../40.perlbmk/ref/alpha/tru64/o3-timing/simerr | 4 +- .../40.perlbmk/ref/alpha/tru64/o3-timing/simout | 11 +- .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../ref/alpha/tru64/simple-atomic/simerr | 4 +- .../ref/alpha/tru64/simple-atomic/simout | 11 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../ref/alpha/tru64/simple-timing/simerr | 4 +- .../ref/alpha/tru64/simple-timing/simout | 11 +- .../ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 12 +- .../50.vortex/ref/alpha/tru64/o3-timing/simerr | 2 +- .../50.vortex/ref/alpha/tru64/o3-timing/simout | 10 +- .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../50.vortex/ref/alpha/tru64/simple-atomic/simerr | 2 +- .../50.vortex/ref/alpha/tru64/simple-atomic/simout | 10 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../50.vortex/ref/alpha/tru64/simple-timing/simerr | 2 +- .../50.vortex/ref/alpha/tru64/simple-timing/simout | 10 +- .../ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../50.vortex/ref/sparc/linux/simple-atomic/simerr | 565 ++++++++++++++++++++- .../50.vortex/ref/sparc/linux/simple-atomic/simout | 10 +- .../ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../50.vortex/ref/sparc/linux/simple-timing/simerr | 565 ++++++++++++++++++++- .../50.vortex/ref/sparc/linux/simple-timing/simout | 10 +- .../ref/sparc/linux/simple-timing/stats.txt | 35 +- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 12 +- .../long/60.bzip2/ref/alpha/tru64/o3-timing/simerr | 3 +- .../long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 11 +- .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../60.bzip2/ref/alpha/tru64/simple-atomic/simerr | 3 +- .../60.bzip2/ref/alpha/tru64/simple-atomic/simout | 11 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../60.bzip2/ref/alpha/tru64/simple-timing/simerr | 3 +- .../60.bzip2/ref/alpha/tru64/simple-timing/simout | 11 +- .../ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../ref/x86/linux/simple-atomic/config.ini | 5 +- .../60.bzip2/ref/x86/linux/simple-atomic/simerr | 8 +- .../60.bzip2/ref/x86/linux/simple-atomic/simout | 14 +- .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt | 8 +- .../ref/x86/linux/simple-timing/config.ini | 14 +- .../60.bzip2/ref/x86/linux/simple-timing/simerr | 8 +- .../60.bzip2/ref/x86/linux/simple-timing/simout | 14 +- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 35 +- .../70.twolf/ref/alpha/tru64/o3-timing/config.ini | 12 +- .../long/70.twolf/ref/alpha/tru64/o3-timing/simerr | 2 +- .../long/70.twolf/ref/alpha/tru64/o3-timing/simout | 10 +- .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../70.twolf/ref/alpha/tru64/simple-atomic/simerr | 2 +- .../70.twolf/ref/alpha/tru64/simple-atomic/simout | 10 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../70.twolf/ref/alpha/tru64/simple-timing/simerr | 2 +- .../70.twolf/ref/alpha/tru64/simple-timing/simout | 10 +- .../ref/alpha/tru64/simple-timing/stats.txt | 35 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../70.twolf/ref/sparc/linux/simple-atomic/simerr | 4 +- .../70.twolf/ref/sparc/linux/simple-atomic/simout | 12 +- .../ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../70.twolf/ref/sparc/linux/simple-timing/simerr | 4 +- .../70.twolf/ref/sparc/linux/simple-timing/simout | 10 +- .../ref/sparc/linux/simple-timing/stats.txt | 35 +- .../ref/x86/linux/simple-atomic/config.ini | 5 +- .../70.twolf/ref/x86/linux/simple-atomic/simerr | 7 +- .../70.twolf/ref/x86/linux/simple-atomic/simout | 15 +- .../70.twolf/ref/x86/linux/simple-atomic/stats.txt | 8 +- .../ref/x86/linux/simple-timing/config.ini | 14 +- .../70.twolf/ref/x86/linux/simple-timing/simerr | 7 +- .../70.twolf/ref/x86/linux/simple-timing/simout | 17 +- .../70.twolf/ref/x86/linux/simple-timing/stats.txt | 35 +- .../sparc/solaris/t1000-simple-atomic/config.ini | 2 + .../ref/sparc/solaris/t1000-simple-atomic/simerr | 8 +- .../ref/sparc/solaris/t1000-simple-atomic/simout | 12 +- .../sparc/solaris/t1000-simple-atomic/stats.txt | 8 +- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 12 +- .../00.hello/ref/alpha/linux/o3-timing/simerr | 4 +- .../00.hello/ref/alpha/linux/o3-timing/simout | 10 +- .../00.hello/ref/alpha/linux/o3-timing/stats.txt | 35 +- .../ref/alpha/linux/simple-atomic/config.ini | 3 + .../00.hello/ref/alpha/linux/simple-atomic/simerr | 4 +- .../00.hello/ref/alpha/linux/simple-atomic/simout | 10 +- .../ref/alpha/linux/simple-atomic/stats.txt | 8 +- .../ref/alpha/linux/simple-timing/config.ini | 12 +- .../00.hello/ref/alpha/linux/simple-timing/simerr | 4 +- .../00.hello/ref/alpha/linux/simple-timing/simout | 10 +- .../ref/alpha/linux/simple-timing/stats.txt | 35 +- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 12 +- .../00.hello/ref/alpha/tru64/o3-timing/simerr | 5 +- .../00.hello/ref/alpha/tru64/o3-timing/simout | 10 +- .../00.hello/ref/alpha/tru64/o3-timing/stats.txt | 35 +- .../ref/alpha/tru64/simple-atomic/config.ini | 3 + .../00.hello/ref/alpha/tru64/simple-atomic/simerr | 5 +- .../00.hello/ref/alpha/tru64/simple-atomic/simout | 10 +- .../ref/alpha/tru64/simple-atomic/stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 12 +- .../00.hello/ref/alpha/tru64/simple-timing/simerr | 5 +- .../00.hello/ref/alpha/tru64/simple-timing/simout | 10 +- .../ref/alpha/tru64/simple-timing/stats.txt | 33 +- .../ref/mips/linux/simple-atomic/config.ini | 3 + .../00.hello/ref/mips/linux/simple-atomic/simerr | 4 +- .../00.hello/ref/mips/linux/simple-atomic/simout | 10 +- .../ref/mips/linux/simple-atomic/stats.txt | 8 +- .../ref/mips/linux/simple-timing/config.ini | 12 +- .../00.hello/ref/mips/linux/simple-timing/simerr | 4 +- .../00.hello/ref/mips/linux/simple-timing/simout | 10 +- .../ref/mips/linux/simple-timing/stats.txt | 35 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../00.hello/ref/sparc/linux/simple-atomic/simerr | 3 +- .../00.hello/ref/sparc/linux/simple-atomic/simout | 9 +- .../ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../00.hello/ref/sparc/linux/simple-timing/simerr | 3 +- .../00.hello/ref/sparc/linux/simple-timing/simout | 9 +- .../ref/sparc/linux/simple-timing/stats.txt | 35 +- .../ref/x86/linux/simple-atomic/config.ini | 3 + .../00.hello/ref/x86/linux/simple-atomic/simerr | 5 +- .../00.hello/ref/x86/linux/simple-atomic/simout | 11 +- .../00.hello/ref/x86/linux/simple-atomic/stats.txt | 8 +- .../ref/x86/linux/simple-timing/config.ini | 12 +- .../00.hello/ref/x86/linux/simple-timing/simerr | 5 +- .../00.hello/ref/x86/linux/simple-timing/simout | 11 +- .../00.hello/ref/x86/linux/simple-timing/stats.txt | 35 +- .../ref/alpha/linux/o3-timing/config.ini | 12 +- .../ref/alpha/linux/o3-timing/simerr | 5 +- .../ref/alpha/linux/o3-timing/simout | 11 +- .../ref/alpha/linux/o3-timing/stats.txt | 35 +- .../ref/sparc/linux/o3-timing/config.ini | 12 +- .../02.insttest/ref/sparc/linux/o3-timing/simerr | 3 +- .../02.insttest/ref/sparc/linux/o3-timing/simout | 9 +- .../ref/sparc/linux/o3-timing/stats.txt | 35 +- .../ref/sparc/linux/simple-atomic/config.ini | 3 + .../ref/sparc/linux/simple-atomic/simerr | 3 +- .../ref/sparc/linux/simple-atomic/simout | 9 +- .../ref/sparc/linux/simple-atomic/stats.txt | 8 +- .../ref/sparc/linux/simple-timing/config.ini | 12 +- .../ref/sparc/linux/simple-timing/simerr | 3 +- .../ref/sparc/linux/simple-timing/simout | 9 +- .../ref/sparc/linux/simple-timing/stats.txt | 35 +- .../linux/tsunami-simple-atomic-dual/config.ini | 34 +- .../alpha/linux/tsunami-simple-atomic-dual/simerr | 6 +- .../alpha/linux/tsunami-simple-atomic-dual/simout | 10 +- .../linux/tsunami-simple-atomic-dual/stats.txt | 62 +-- .../alpha/linux/tsunami-simple-atomic/config.ini | 27 +- .../ref/alpha/linux/tsunami-simple-atomic/simerr | 5 +- .../ref/alpha/linux/tsunami-simple-atomic/simout | 10 +- .../alpha/linux/tsunami-simple-atomic/stats.txt | 44 +- .../linux/tsunami-simple-timing-dual/config.ini | 34 +- .../alpha/linux/tsunami-simple-timing-dual/simerr | 6 +- .../alpha/linux/tsunami-simple-timing-dual/simout | 10 +- .../linux/tsunami-simple-timing-dual/stats.txt | 62 +-- .../alpha/linux/tsunami-simple-timing/config.ini | 27 +- .../ref/alpha/linux/tsunami-simple-timing/simerr | 5 +- .../ref/alpha/linux/tsunami-simple-timing/simout | 10 +- .../alpha/linux/tsunami-simple-timing/stats.txt | 44 +- .../ref/alpha/eio/simple-atomic/config.ini | 3 + .../ref/alpha/eio/simple-atomic/simerr | 3 +- .../ref/alpha/eio/simple-atomic/simout | 9 +- .../ref/alpha/eio/simple-atomic/stats.txt | 8 +- .../ref/alpha/eio/simple-timing/config.ini | 12 +- .../ref/alpha/eio/simple-timing/simerr | 3 +- .../ref/alpha/eio/simple-timing/simout | 9 +- .../ref/alpha/eio/simple-timing/stats.txt | 35 +- .../ref/alpha/eio/simple-atomic-mp/config.ini | 39 +- .../ref/alpha/eio/simple-atomic-mp/simerr | 3 +- .../ref/alpha/eio/simple-atomic-mp/simout | 9 +- .../ref/alpha/eio/simple-atomic-mp/stats.txt | 89 +--- .../ref/alpha/eio/simple-timing-mp/config.ini | 39 +- .../ref/alpha/eio/simple-timing-mp/simerr | 3 +- .../ref/alpha/eio/simple-timing-mp/simout | 9 +- .../ref/alpha/eio/simple-timing-mp/stats.txt | 89 +--- .../50.memtest/ref/alpha/linux/memtest/config.ini | 27 +- .../50.memtest/ref/alpha/linux/memtest/simerr | 2 +- .../50.memtest/ref/alpha/linux/memtest/simout | 9 +- .../50.memtest/ref/alpha/linux/memtest/stats.txt | 87 +--- .../linux/twosys-tsunami-simple-atomic/config.ini | 34 +- .../linux/twosys-tsunami-simple-atomic/simerr | 7 +- .../linux/twosys-tsunami-simple-atomic/simout | 11 +- .../linux/twosys-tsunami-simple-atomic/stats.txt | 14 +- 261 files changed, 2357 insertions(+), 2445 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 65280a84c..068fb2315 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 4ea4c0572..e459fc4f1 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:25:12 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 4e08b47b3..c5506c5e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4206850 # Nu global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted global.BPredUnit.lookups 76039018 # Number of BP lookups global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 193677 # Simulator instruction rate (inst/s) -host_mem_usage 202220 # Number of bytes of host memory used -host_seconds 2920.07 # Real time elapsed on the host -host_tick_rate 57217081 # Simulator tick rate (ticks/s) +host_inst_rate 244512 # Simulator instruction rate (inst/s) +host_mem_usage 204148 # Number of bytes of host memory used +host_seconds 2312.99 # Real time elapsed on the host +host_tick_rate 72234766 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.003628 # ms system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 468828 # number of replacements system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000014 # ms system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # m system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 85262 # number of replacements system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index a002dafb3..53e8ae1eb 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 4f98f10a9..2a4b52a28 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:47 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 96bd5579b..d5f13f08c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3417919 # Simulator instruction rate (inst/s) -host_mem_usage 193752 # Number of bytes of host memory used -host_seconds 176.09 # Real time elapsed on the host -host_tick_rate 1708971531 # Simulator tick rate (ticks/s) +host_inst_rate 6175770 # Simulator instruction rate (inst/s) +host_mem_usage 195684 # Number of bytes of host memory used +host_seconds 97.45 # Real time elapsed on the host +host_tick_rate 3087904278 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 9d3e94dd6..6d294469b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 912067c8f..8b3b6bb5d 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. spec_init Loading Input Data Duplicating 262144 bytes diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 5fbfd3d3d..57d9b05f8 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1797646 # Simulator instruction rate (inst/s) -host_mem_usage 201208 # Number of bytes of host memory used -host_seconds 334.80 # Real time elapsed on the host -host_tick_rate 2323765799 # Simulator tick rate (ticks/s) +host_inst_rate 1969135 # Simulator instruction rate (inst/s) +host_mem_usage 203124 # Number of bytes of host memory used +host_seconds 305.65 # Real time elapsed on the host +host_tick_rate 2545444210 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.003443 # ms system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000001 # ms system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # m system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 84513 # number of replacements system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4b4d2436b..ee1f88977 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index cf3fc26c2..4fc3f25f8 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:58 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:45:29 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index b1499e0a2..1bd86bd33 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 83681535 # Nu global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted global.BPredUnit.lookups 254458067 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116972 # Simulator instruction rate (inst/s) -host_mem_usage 204276 # Number of bytes of host memory used -host_seconds 12016.73 # Real time elapsed on the host -host_tick_rate 91760367 # Simulator tick rate (ticks/s) +host_inst_rate 104414 # Simulator instruction rate (inst/s) +host_mem_usage 206176 # Number of bytes of host memory used +host_seconds 13461.92 # Real time elapsed on the host +host_tick_rate 81909485 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. @@ -119,15 +119,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.001012 # ms system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 523278 # number of replacements system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -213,15 +204,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000004 # ms system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 222 # number of replacements system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -398,15 +380,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # m system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 84497 # number of replacements system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 94bc4dfcb..8d0eebe28 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr index ee69ae99e..eabe42249 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index 959e9811f..d1dad3acf 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:45:38 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:46:25 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 6ee039121..d5f28736a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2833353 # Simulator instruction rate (inst/s) -host_mem_usage 195884 # Number of bytes of host memory used -host_seconds 525.71 # Real time elapsed on the host -host_tick_rate 1416680719 # Simulator tick rate (ticks/s) +host_inst_rate 3714547 # Simulator instruction rate (inst/s) +host_mem_usage 197792 # Number of bytes of host memory used +host_seconds 401.00 # Real time elapsed on the host +host_tick_rate 1857278454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 2760624c7..90217b2a5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 696328daa..d7c279dee 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:13 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:50:17 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 21ee70af0..5a55fc3e0 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2121797 # Simulator instruction rate (inst/s) -host_mem_usage 203340 # Number of bytes of host memory used -host_seconds 702.01 # Real time elapsed on the host -host_tick_rate 2963511011 # Simulator tick rate (ticks/s) +host_inst_rate 1502574 # Simulator instruction rate (inst/s) +host_mem_usage 205236 # Number of bytes of host memory used +host_seconds 991.31 # Real time elapsed on the host +host_tick_rate 2098643273 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.080416 # Number of seconds simulated @@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000901 # ms system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000001 # ms system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # m system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 82905 # number of replacements system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 93e326b16..1f354a5d6 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -49,7 +52,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr index 12f446c64..d7d61bab3 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -1,9 +1,15 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 81b1be1e0..5eb2ed956 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:19:42 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:00:03 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -21,6 +20,7 @@ Input data 1048576 bytes in length Compressing Input Data, level 1 Compressed data 108074 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index fcdb37b5a..cf444d872 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 717061 # Simulator instruction rate (inst/s) -host_mem_usage 197184 # Number of bytes of host memory used -host_seconds 2258.34 # Real time elapsed on the host -host_tick_rate 426391006 # Simulator tick rate (ticks/s) +host_inst_rate 1622364 # Simulator instruction rate (inst/s) +host_mem_usage 197488 # Number of bytes of host memory used +host_seconds 998.15 # Real time elapsed on the host +host_tick_rate 964717823 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated sim_seconds 0.962935 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 4630d922d..1e457c793 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr index 12f446c64..d7d61bab3 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -1,9 +1,15 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 7f0c2942c..547d12c0b 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:22:06 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:02:02 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -21,6 +20,7 @@ Input data 1048576 bytes in length Compressing Input Data, level 1 Compressed data 108074 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 89a1a5647..3681e4f0c 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 511923 # Simulator instruction rate (inst/s) -host_mem_usage 204640 # Number of bytes of host memory used -host_seconds 3163.30 # Real time elapsed on the host -host_tick_rate 807415286 # Simulator tick rate (ticks/s) +host_inst_rate 1065301 # Simulator instruction rate (inst/s) +host_mem_usage 204932 # Number of bytes of host memory used +host_seconds 1520.10 # Real time elapsed on the host +host_tick_rate 1680214432 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated sim_seconds 2.554098 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000834 # ms system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000000 # ms system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # m system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index e35ca8bb4..cd4931e34 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -46,6 +46,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -135,12 +136,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -309,12 +309,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -354,6 +353,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -443,12 +443,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -617,12 +616,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -660,6 +658,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -679,6 +678,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -713,12 +713,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -746,12 +745,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -881,16 +879,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -1259,16 +1263,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 4cafe060d..f51a48835 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,5 +1,7 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: 125740500: Trying to launch CPU number 1! -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index cd7d66c16..1910760d1 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:47:53 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:44:44 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1907705384500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 6cd8fa945..dcbc52710 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -16,10 +16,10 @@ global.BPredUnit.lookups 10093436 # Nu global.BPredUnit.lookups 5538388 # Number of BP lookups global.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. -host_inst_rate 132487 # Simulator instruction rate (inst/s) -host_mem_usage 294244 # Number of bytes of host memory used -host_seconds 424.12 # Real time elapsed on the host -host_tick_rate 4498020766 # Simulator tick rate (ticks/s) +host_inst_rate 133092 # Simulator instruction rate (inst/s) +host_mem_usage 294856 # Number of bytes of host memory used +host_seconds 422.19 # Real time elapsed on the host +host_tick_rate 4518571306 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 2050532 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 906322 # Number of conflicting loads. memdepunit.memDep.conflictingStores 1832540 # Number of conflicting stores. @@ -146,15 +146,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # m system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.replacements 922726 # number of replacements system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -256,15 +247,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0.096077 # m system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.icache.replacements 619753 # number of replacements system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -600,15 +582,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # m system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.dcache.replacements 531784 # number of replacements system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -710,15 +683,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0.144757 # m system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.icache.replacements 446606 # number of replacements system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -985,15 +949,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41697 # number of replacements system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -1072,15 +1027,6 @@ system.l2c.overall_mshr_miss_rate 0.248969 # ms system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 402142 # number of replacements system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 1ce4a49e9..c7a30cef6 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -46,6 +46,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -135,12 +136,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -309,12 +309,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -352,6 +351,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -371,6 +371,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -405,12 +406,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -438,12 +438,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -573,16 +572,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -951,16 +956,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr index 1a557daf8..83c71fc5c 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -1,4 +1,5 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index c0c3673fc..c6712a23b 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:47:52 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:42:11 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1867363148500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index d70f58b89..37990c73f 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828629 # Nu global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted global.BPredUnit.lookups 14570242 # Number of BP lookups global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. -host_inst_rate 133323 # Simulator instruction rate (inst/s) -host_mem_usage 292856 # Number of bytes of host memory used -host_seconds 398.21 # Real time elapsed on the host -host_tick_rate 4689394624 # Simulator tick rate (ticks/s) +host_inst_rate 209657 # Simulator instruction rate (inst/s) +host_mem_usage 292968 # Number of bytes of host memory used +host_seconds 253.23 # Real time elapsed on the host +host_tick_rate 7374290880 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads. memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores. memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. @@ -134,15 +134,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.095592 # ms system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 1401991 # number of replacements system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -244,15 +235,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.110520 # ms system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 994847 # number of replacements system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -536,15 +518,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -623,15 +596,6 @@ system.l2c.overall_mshr_miss_rate 0.255051 # ms system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 396031 # number of replacements system.l2c.sampled_refs 427707 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 064c9f4af..3c2bf8020 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr index ee69ae99e..eabe42249 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 2fac0077c..6c41adbc1 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:56:43 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:51:47 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 042194df8..a02166247 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2390204 # Simulator instruction rate (inst/s) -host_mem_usage 328072 # Number of bytes of host memory used -host_seconds 102.01 # Real time elapsed on the host -host_tick_rate 1198022319 # Simulator tick rate (ticks/s) +host_inst_rate 2414989 # Simulator instruction rate (inst/s) +host_mem_usage 329980 # Number of bytes of host memory used +host_seconds 100.97 # Real time elapsed on the host +host_tick_rate 1210444801 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index e22470f97..8066afd8e 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 0d7d366fc..380022b15 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:52:55 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:53:06 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 8d551e127..ac46d4baa 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1337728 # Simulator instruction rate (inst/s) -host_mem_usage 335528 # Number of bytes of host memory used -host_seconds 182.28 # Real time elapsed on the host -host_tick_rate 2010386962 # Simulator tick rate (ticks/s) +host_inst_rate 1327795 # Simulator instruction rate (inst/s) +host_mem_usage 337424 # Number of bytes of host memory used +host_seconds 183.64 # Real time elapsed on the host +host_tick_rate 1995461602 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.366446 # Number of seconds simulated @@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.009397 # ms system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000004 # ms system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # m system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 40541f366..640586f7b 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -49,7 +52,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr index 72ba90ece..94d399eab 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,4 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index c22c368b8..225df2c54 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:05:48 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:06:25 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index a4a7be0d1..16a3e187b 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 687504 # Simulator instruction rate (inst/s) -host_mem_usage 331712 # Number of bytes of host memory used -host_seconds 392.27 # Real time elapsed on the host -host_tick_rate 422480782 # Simulator tick rate (ticks/s) +host_inst_rate 1454099 # Simulator instruction rate (inst/s) +host_mem_usage 332016 # Number of bytes of host memory used +host_seconds 185.47 # Real time elapsed on the host +host_tick_rate 893563512 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated sim_seconds 0.165726 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 2447a5715..c34572b5c 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr index 72ba90ece..94d399eab 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,4 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 5e04da3a3..fdaf99f0e 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 20:14:49 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:06:48 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 2fa37b8f7..f4739c53b 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 422356 # Simulator instruction rate (inst/s) -host_mem_usage 339176 # Number of bytes of host memory used -host_seconds 638.53 # Real time elapsed on the host -host_tick_rate 775808629 # Simulator tick rate (ticks/s) +host_inst_rate 939339 # Simulator instruction rate (inst/s) +host_mem_usage 339456 # Number of bytes of host memory used +host_seconds 287.10 # Real time elapsed on the host +host_tick_rate 1725433923 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated sim_seconds 0.495377 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.017832 # ms system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000002 # ms system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # m system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 08a12f2a0..0154cb675 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 1 2009 00:35:14 -M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase -M5 started Feb 1 2009 01:31:23 -M5 executing on fajita +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:09:31 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 9ef20eecb..2072caa4b 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 942344 # Simulator instruction rate (inst/s) -host_mem_usage 199592 # Number of bytes of host memory used -host_seconds 1586.98 # Real time elapsed on the host -host_tick_rate 547379933 # Simulator tick rate (ticks/s) +host_inst_rate 1649324 # Simulator instruction rate (inst/s) +host_mem_usage 201208 # Number of bytes of host memory used +host_seconds 906.72 # Real time elapsed on the host +host_tick_rate 958044415 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated sim_seconds 0.868682 # Number of seconds simulated diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 793578856..87163bbc2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -46,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -83,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -120,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 3b8d98147..6d4d2b6e7 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 1 2009 00:35:14 -M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase -M5 started Feb 1 2009 01:51:40 -M5 executing on fajita +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:11:36 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index c473a6423..923ce5951 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 856633 # Simulator instruction rate (inst/s) -host_mem_usage 207060 # Number of bytes of host memory used -host_seconds 1745.77 # Real time elapsed on the host -host_tick_rate 1369809690 # Simulator tick rate (ticks/s) +host_inst_rate 1421036 # Simulator instruction rate (inst/s) +host_mem_usage 208620 # Number of bytes of host memory used +host_seconds 1052.39 # Real time elapsed on the host +host_tick_rate 2272325062 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated sim_seconds 2.391370 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.005988 # ms system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000002 # ms system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # m system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 206ca6cd4..253ff4370 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr index 19732539d..f7b481bbe 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,10 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 2bc3bdeed..e8a891c22 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Eon, Version 1.1 +info: Increasing stack size by one page. OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 704dd86aa..cbcabf35c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted global.BPredUnit.lookups 62209737 # Number of BP lookups global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 151728 # Simulator instruction rate (inst/s) -host_mem_usage 209656 # Number of bytes of host memory used -host_seconds 2475.31 # Real time elapsed on the host -host_tick_rate 54537175 # Simulator tick rate (ticks/s) +host_inst_rate 183215 # Simulator instruction rate (inst/s) +host_mem_usage 211568 # Number of bytes of host memory used +host_seconds 2049.91 # Real time elapsed on the host +host_tick_rate 65854919 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 782 # number of replacements system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000061 # ms system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1975 # number of replacements system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # m system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 14 # number of replacements system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index db2c600ee..b219ea49a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr index 19732539d..f7b481bbe 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,11 +1,10 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout index bb141923e..320d9365d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:26:02 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Eon, Version 1.1 +info: Increasing stack size by one page. OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 520bb514f..f57fc8170 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3407773 # Simulator instruction rate (inst/s) -host_mem_usage 201328 # Number of bytes of host memory used -host_seconds 116.99 # Real time elapsed on the host -host_tick_rate 1703884563 # Simulator tick rate (ticks/s) +host_inst_rate 3515833 # Simulator instruction rate (inst/s) +host_mem_usage 203260 # Number of bytes of host memory used +host_seconds 113.39 # Real time elapsed on the host +host_tick_rate 1757913715 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 5e43f3356..86203bb88 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr index 19732539d..f7b481bbe 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,11 +1,10 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index c8c05bf7d..3eda1fae9 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -5,13 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:22:18 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:52 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Eon, Version 1.1 +info: Increasing stack size by one page. OO-style eon Time= 0.566667 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 99f2593a9..56640f3eb 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1526276 # Simulator instruction rate (inst/s) -host_mem_usage 208780 # Number of bytes of host memory used -host_seconds 261.20 # Real time elapsed on the host -host_tick_rate 2172088412 # Simulator tick rate (ticks/s) +host_inst_rate 1674592 # Simulator instruction rate (inst/s) +host_mem_usage 210700 # Number of bytes of host memory used +host_seconds 238.07 # Real time elapsed on the host +host_tick_rate 2383160323 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000009 # ms system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # m system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 15 # number of replacements system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index d47448621..2eb72fecc 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr index ac5607abe..01b34fd92 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 7f7e7a869..8803cb82c 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 2e0ae6799..6ff850ff7 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 29107758 # Nu global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted global.BPredUnit.lookups 349424731 # Number of BP lookups global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. -host_inst_rate 157306 # Simulator instruction rate (inst/s) -host_mem_usage 209560 # Number of bytes of host memory used -host_seconds 11589.17 # Real time elapsed on the host -host_tick_rate 60846406 # Simulator tick rate (ticks/s) +host_inst_rate 217689 # Simulator instruction rate (inst/s) +host_mem_usage 211464 # Number of bytes of host memory used +host_seconds 8374.52 # Real time elapsed on the host +host_tick_rate 84202937 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.002268 # ms system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 1526847 # number of replacements system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000028 # ms system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 8097 # number of replacements system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # m system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 1474251 # number of replacements system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index b01978881..4863763a5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr index ac5607abe..01b34fd92 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 30786b895..3e0584ae3 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:26:39 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 028814426..a2839e9d4 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3237524 # Simulator instruction rate (inst/s) -host_mem_usage 200500 # Number of bytes of host memory used -host_seconds 620.53 # Real time elapsed on the host -host_tick_rate 1619110797 # Simulator tick rate (ticks/s) +host_inst_rate 3467416 # Simulator instruction rate (inst/s) +host_mem_usage 202428 # Number of bytes of host memory used +host_seconds 579.39 # Real time elapsed on the host +host_tick_rate 1734081372 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index fb670395d..a7ffe8cab 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr index ac5607abe..01b34fd92 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr @@ -1,4 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 5e421444e..bfb6dafd6 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:29:29 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c24e3b046..87861b454 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1407375 # Simulator instruction rate (inst/s) -host_mem_usage 207960 # Number of bytes of host memory used -host_seconds 1427.47 # Real time elapsed on the host -host_tick_rate 1971983298 # Simulator tick rate (ticks/s) +host_inst_rate 2199489 # Simulator instruction rate (inst/s) +host_mem_usage 209876 # Number of bytes of host memory used +host_seconds 913.39 # Real time elapsed on the host +host_tick_rate 3081877276 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.002124 # ms system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000005 # ms system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # m system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 1473608 # number of replacements system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 2cf1e1f30..2927f396f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 305b9e178..830b96073 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:27:20 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:29:46 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 36c3049e3..ea0c05470 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 452707 # Nu global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted global.BPredUnit.lookups 16249463 # Number of BP lookups global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 155507 # Simulator instruction rate (inst/s) -host_mem_usage 212996 # Number of bytes of host memory used -host_seconds 511.82 # Real time elapsed on the host -host_tick_rate 53016132 # Simulator tick rate (ticks/s) +host_inst_rate 207814 # Simulator instruction rate (inst/s) +host_mem_usage 214944 # Number of bytes of host memory used +host_seconds 382.99 # Real time elapsed on the host +host_tick_rate 70849023 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.006031 # ms system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 200933 # number of replacements system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.006420 # ms system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 83888 # number of replacements system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # m system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 148779 # number of replacements system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 3d82ef611..5a410e8c9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index f78544a3c..7f58d408c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:24:43 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:31:50 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 7b2d6e4f7..3b23e3386 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3156054 # Simulator instruction rate (inst/s) -host_mem_usage 203904 # Number of bytes of host memory used -host_seconds 27.99 # Real time elapsed on the host -host_tick_rate 1579824710 # Simulator tick rate (ticks/s) +host_inst_rate 5386925 # Simulator instruction rate (inst/s) +host_mem_usage 205832 # Number of bytes of host memory used +host_seconds 16.40 # Real time elapsed on the host +host_tick_rate 2696520513 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 7718ab128..74756cd76 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index 7c7d8426c..9806a0cdd 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:00 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:32:07 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 4078e993e..66817a603 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1655989 # Simulator instruction rate (inst/s) -host_mem_usage 211348 # Number of bytes of host memory used -host_seconds 53.35 # Real time elapsed on the host -host_tick_rate 2533794438 # Simulator tick rate (ticks/s) +host_inst_rate 2514121 # Simulator instruction rate (inst/s) +host_mem_usage 213276 # Number of bytes of host memory used +host_seconds 35.14 # Real time elapsed on the host +host_tick_rate 3846798027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.006035 # ms system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000864 # ms system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # m system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 147561 # number of replacements system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index ce467d491..5b764e1f0 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr index 06afeeef2..b33f4f1d5 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,564 +1,1125 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall time(4026527848, 4026528248, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527400, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527312, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 413, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 414, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527288, 4026527688, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526960, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527040, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527000, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526312, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526832, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526840, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526936, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527008, 4026527408, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526560, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527184, 18732, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526632, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526736, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527744, 225, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527096, 4026527496, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526648, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526824, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527184, 1879089152, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 1595768, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525968, 20500, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525968, 4026526436, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526056, 7004192, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527512, 4, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index b0eadd5ad..95b7d967f 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:47 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:53:28 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 25cbdfb32..be8f1d320 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2431097 # Simulator instruction rate (inst/s) -host_mem_usage 204768 # Number of bytes of host memory used -host_seconds 56.00 # Real time elapsed on the host -host_tick_rate 1216955986 # Simulator tick rate (ticks/s) +host_inst_rate 3821272 # Simulator instruction rate (inst/s) +host_mem_usage 206688 # Number of bytes of host memory used +host_seconds 35.63 # Real time elapsed on the host +host_tick_rate 1912846403 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 1868a281c..4e4bcb117 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr index 06afeeef2..b33f4f1d5 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -1,564 +1,1125 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall time(4026527848, 4026528248, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527400, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527312, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 413, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 414, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527288, 4026527688, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526960, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527040, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527000, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526312, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526832, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526840, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526936, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527008, 4026527408, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526560, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527184, 18732, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526632, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526736, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527744, 225, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527096, 4026527496, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526648, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526824, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527184, 1879089152, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 1595768, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525968, 20500, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525968, 4026526436, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026526056, 7004192, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026527512, 4, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index 2b1927ccc..22ae99950 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:57 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:54:04 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 9b35ba579..0cca434c3 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1344201 # Simulator instruction rate (inst/s) -host_mem_usage 212228 # Number of bytes of host memory used -host_seconds 101.28 # Real time elapsed on the host -host_tick_rate 2025263348 # Simulator tick rate (ticks/s) +host_inst_rate 1934138 # Simulator instruction rate (inst/s) +host_mem_usage 214132 # Number of bytes of host memory used +host_seconds 70.39 # Real time elapsed on the host +host_tick_rate 2914099932 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.205117 # Number of seconds simulated @@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.002666 # ms system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.001372 # ms system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # m system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 7cd689e97..7014f9608 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr index fd3c8e17c..b2d79346c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 46c21a733..75ae695aa 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:32:43 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 2cba4195f..d59f4f0e0 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19647325 # Nu global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted global.BPredUnit.lookups 345502589 # Number of BP lookups global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. -host_inst_rate 178472 # Simulator instruction rate (inst/s) -host_mem_usage 202004 # Number of bytes of host memory used -host_seconds 9727.25 # Real time elapsed on the host -host_tick_rate 76312348 # Simulator tick rate (ticks/s) +host_inst_rate 166211 # Simulator instruction rate (inst/s) +host_mem_usage 203924 # Number of bytes of host memory used +host_seconds 10444.84 # Real time elapsed on the host +host_tick_rate 71069469 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. @@ -119,15 +119,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.013924 # ms system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 9155775 # number of replacements system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -228,15 +219,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000003 # ms system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -417,15 +399,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # m system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 2759426 # number of replacements system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 28bab6a3a..0a457f545 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index fd3c8e17c..b2d79346c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 6c0c37f87..6942bb9c6 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:32:58 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index a74bbb7e5..8b9cdfecf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3337847 # Simulator instruction rate (inst/s) -host_mem_usage 193672 # Number of bytes of host memory used -host_seconds 545.20 # Real time elapsed on the host -host_tick_rate 1674974438 # Simulator tick rate (ticks/s) +host_inst_rate 3629734 # Simulator instruction rate (inst/s) +host_mem_usage 195600 # Number of bytes of host memory used +host_seconds 501.35 # Real time elapsed on the host +host_tick_rate 1821446907 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 896ad9c05..c29e7b8cc 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index fd3c8e17c..b2d79346c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 15467090e..2a7a491ad 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:36:09 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 027e53548..b4009b3e6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1294592 # Simulator instruction rate (inst/s) -host_mem_usage 201124 # Number of bytes of host memory used -host_seconds 1405.68 # Real time elapsed on the host -host_tick_rate 1940692275 # Simulator tick rate (ticks/s) +host_inst_rate 2148631 # Simulator instruction rate (inst/s) +host_mem_usage 203048 # Number of bytes of host memory used +host_seconds 846.95 # Real time elapsed on the host +host_tick_rate 3220962828 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.015645 # ms system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000000 # ms system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # m system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 2751986 # number of replacements system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 13ff2455f..5ffe1d191 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -49,7 +52,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 346eca640..2b254f0b1 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,18 +5,20 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 20:02:35 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:15:07 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index d428992be..c42805444 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 896643 # Simulator instruction rate (inst/s) -host_mem_usage 197076 # Number of bytes of host memory used -host_seconds 5189.55 # Real time elapsed on the host -host_tick_rate 546326494 # Simulator tick rate (ticks/s) +host_inst_rate 2107205 # Simulator instruction rate (inst/s) +host_mem_usage 197384 # Number of bytes of host memory used +host_seconds 2208.22 # Real time elapsed on the host +host_tick_rate 1283923835 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated sim_seconds 2.835189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index 64329243b..4d80734e6 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index f677c72d6..97a038291 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,18 +5,20 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 18:30:11 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:16:41 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 6bbf1280e..429f68d1b 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 483951 # Simulator instruction rate (inst/s) -host_mem_usage 204540 # Number of bytes of host memory used -host_seconds 9614.98 # Real time elapsed on the host -host_tick_rate 795135330 # Simulator tick rate (ticks/s) +host_inst_rate 1048991 # Simulator instruction rate (inst/s) +host_mem_usage 204820 # Number of bytes of host memory used +host_seconds 4435.86 # Real time elapsed on the host +host_tick_rate 1723500836 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated sim_seconds 7.645209 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.005645 # ms system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000000 # ms system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # m system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9dd2a52cb..6fbd6e595 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 4aef79cf1..f827bf3c9 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:52 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:37:34 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index bf979a603..485a8a7d7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted global.BPredUnit.lookups 19468548 # Number of BP lookups global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 123995 # Simulator instruction rate (inst/s) -host_mem_usage 207276 # Number of bytes of host memory used -host_seconds 678.90 # Real time elapsed on the host -host_tick_rate 60124800 # Simulator tick rate (ticks/s) +host_inst_rate 179748 # Simulator instruction rate (inst/s) +host_mem_usage 209188 # Number of bytes of host memory used +host_seconds 468.32 # Real time elapsed on the host +host_tick_rate 87159490 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000079 # ms system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000523 # ms system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 8143 # number of replacements system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # m system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 035d4db65..593992332 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 17a346373..d3d15e406 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:41:19 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py long/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index fd63e8611..bce09d7dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2797283 # Simulator instruction rate (inst/s) -host_mem_usage 198592 # Number of bytes of host memory used -host_seconds 32.85 # Real time elapsed on the host -host_tick_rate 1398634763 # Simulator tick rate (ticks/s) +host_inst_rate 5743124 # Simulator instruction rate (inst/s) +host_mem_usage 200524 # Number of bytes of host memory used +host_seconds 16.00 # Real time elapsed on the host +host_tick_rate 2871531471 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index c80a77e5d..b166b9052 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr index cd7a7fb23..b2d79346c 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index a43a9ad37..c9ffcf959 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:54 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:41:35 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py long/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 3b3e2ccb7..c77e086b4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1637033 # Simulator instruction rate (inst/s) -host_mem_usage 206044 # Number of bytes of host memory used -host_seconds 56.14 # Real time elapsed on the host -host_tick_rate 2115189911 # Simulator tick rate (ticks/s) +host_inst_rate 2902114 # Simulator instruction rate (inst/s) +host_mem_usage 207972 # Number of bytes of host memory used +host_seconds 31.67 # Real time elapsed on the host +host_tick_rate 3749775750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000088 # ms system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000093 # ms system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # m system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 0da6124a8..3d5e2c242 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr index 5ff857a03..eabe42249 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 997da0518..eb6462de2 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,14 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:54:24 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:55:15 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py long/70.twolf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +25,5 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +info: Increasing stack size by one page. 122 123 124 Exiting @ tick 96722951500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 0c05fead2..9b4c86591 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2346541 # Simulator instruction rate (inst/s) -host_mem_usage 200408 # Number of bytes of host memory used -host_seconds 82.44 # Real time elapsed on the host -host_tick_rate 1173274177 # Simulator tick rate (ticks/s) +host_inst_rate 2406877 # Simulator instruction rate (inst/s) +host_mem_usage 202316 # Number of bytes of host memory used +host_seconds 80.37 # Real time elapsed on the host +host_tick_rate 1203441627 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index afa783463..65aeb1d48 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr index 5ff857a03..eabe42249 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index e76e61d8a..5a804eb57 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 17 2008 13:45:49 -M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f -M5 commit date Sat Nov 15 23:42:11 2008 -0500 -M5 started Nov 17 2008 13:46:11 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:56:10 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +25,5 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +info: Increasing stack size by one page. 122 123 124 Exiting @ tick 270578573000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 304bdc3f9..571ff6af8 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1229412 # Simulator instruction rate (inst/s) -host_mem_usage 207888 # Number of bytes of host memory used -host_seconds 157.35 # Real time elapsed on the host -host_tick_rate 1719613407 # Simulator tick rate (ticks/s) +host_inst_rate 1319897 # Simulator instruction rate (inst/s) +host_mem_usage 209760 # Number of bytes of host memory used +host_seconds 146.56 # Real time elapsed on the host +host_tick_rate 1846186883 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270579 # Number of seconds simulated @@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000021 # ms system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000064 # ms system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # m system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index b8de37bf3..d0a878165 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -49,7 +52,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr index 27f336eb4..94d399eab 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index eea857771..fd5d4825d 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,14 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:57:21 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:24:38 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,6 +17,8 @@ TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 90a051575..5f9bdeb8f 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 697777 # Simulator instruction rate (inst/s) -host_mem_usage 204448 # Number of bytes of host memory used -host_seconds 313.27 # Real time elapsed on the host -host_tick_rate 415001936 # Simulator tick rate (ticks/s) +host_inst_rate 1349784 # Simulator instruction rate (inst/s) +host_mem_usage 204760 # Number of bytes of host memory used +host_seconds 161.95 # Real time elapsed on the host +host_tick_rate 802781753 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 86cbaffb4..c231a2f5e 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr index 27f336eb4..94d399eab 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 6c4741848..c8bd5d18c 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,14 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:12:20 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:27:21 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,6 +19,8 @@ TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 91975530b..21956901a 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 495446 # Simulator instruction rate (inst/s) -host_mem_usage 211916 # Number of bytes of host memory used -host_seconds 441.21 # Real time elapsed on the host -host_tick_rate 764874761 # Simulator tick rate (ticks/s) +host_inst_rate 1082313 # Simulator instruction rate (inst/s) +host_mem_usage 212196 # Number of bytes of host memory used +host_seconds 201.97 # Real time elapsed on the host +host_tick_rate 1670883730 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.337470 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000018 # ms system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # m system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 279ca6f7b..1a673fafa 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -48,6 +48,7 @@ side_b=system.membus.port[2] [system.cpu] type=AtomicSimpleCPU children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -103,6 +104,7 @@ pio=system.iobus.port[15] type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index 6814dd775..d6849b6b0 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -2,14 +2,14 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 Warning: rounding error > tolerance 0.002000 rounded to 0 -warn: No kernel set for full system simulation. Assuming you know what you're doing... Warning: rounding error > tolerance 0.002000 rounded to 0 warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b Warning: rounding error > tolerance 0.002000 rounded to 0 warn: Sockets disabled, not accepting gdb connections -warn: Ignoring write to SPARC ERROR regsiter -warn: Ignoring write to SPARC ERROR regsiter +For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/7fe1004f +hack: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 2f6efdd10..177f45aa2 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -5,12 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 15:59:58 -M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e -M5 commit date Wed Nov 05 15:30:49 2008 -0500 -M5 started Nov 5 2008 16:00:22 +M5 compiled Feb 16 2009 01:00:04 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:00:27 M5 executing on zizzer -command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second +info: No kernel set for full system simulation. Assuming you know what you're doing... info: Entering event queue @ 0. Starting simulation... +info: Ignoring write to SPARC ERROR regsiter +info: Ignoring write to SPARC ERROR regsiter Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index fb4170969..74e0ebf1a 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2656730 # Simulator instruction rate (inst/s) -host_mem_usage 499828 # Number of bytes of host memory used -host_seconds 839.06 # Real time elapsed on the host -host_tick_rate 2662232 # Simulator tick rate (ticks/s) +host_inst_rate 2534703 # Simulator instruction rate (inst/s) +host_mem_usage 501600 # Number of bytes of host memory used +host_seconds 879.46 # Real time elapsed on the host +host_tick_rate 2539952 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 3764c941e..46ef9d2b9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr index 5ff857a03..eabe42249 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index b502697af..0d9f81ac8 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 12474500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 93747295c..b0c4635e4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 440 # Nu global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted global.BPredUnit.lookups 2263 # Number of BP lookups global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 7058 # Simulator instruction rate (inst/s) -host_mem_usage 199016 # Number of bytes of host memory used -host_seconds 0.90 # Real time elapsed on the host -host_tick_rate 13784618 # Simulator tick rate (ticks/s) +host_inst_rate 68343 # Simulator instruction rate (inst/s) +host_mem_usage 200684 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 133183507 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. @@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.070730 # ms system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.170366 # ms system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -405,15 +387,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # m system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index f3b922bb8..5b4a31473 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr index 5ff857a03..eabe42249 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index 9a255c446..8975ff812 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:44 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 712fc898c..93917b1eb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6758 # Simulator instruction rate (inst/s) -host_mem_usage 190848 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host -host_tick_rate 3391912 # Simulator tick rate (ticks/s) +host_inst_rate 122377 # Simulator instruction rate (inst/s) +host_mem_usage 192524 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 61135620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 0b9f96b2e..26edcc7cf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr index 5ff857a03..eabe42249 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index c3d847e3f..22d348b2d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 33777000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index f97f1c530..dc4411624 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 68165 # Simulator instruction rate (inst/s) -host_mem_usage 198212 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 358563073 # Simulator tick rate (ticks/s) +host_inst_rate 344098 # Simulator instruction rate (inst/s) +host_mem_usage 199968 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1795121173 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.088780 # ms system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.043492 # ms system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -223,15 +205,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # m system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 21f8bc603..9abe15dfc 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index 28251ddf8..bb8489f81 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index e4872d461..d373e353b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:52 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 12af7d1b2..af633c5e8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 209 # Nu global.BPredUnit.condPredicted 447 # Number of conditional branches predicted global.BPredUnit.lookups 859 # Number of BP lookups global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 31288 # Simulator instruction rate (inst/s) -host_mem_usage 198012 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 93885607 # Simulator tick rate (ticks/s) +host_inst_rate 22600 # Simulator instruction rate (inst/s) +host_mem_usage 199684 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 67889683 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. @@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.113033 # ms system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.242303 # ms system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -404,15 +386,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 1 # m system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index bbdfaa101..8ca1fff45 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr index 28251ddf8..bb8489f81 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 55a4a98f7..7c13e1d4c 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:24:43 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 051f6dec4..ddfd1ad69 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334328 # Simulator instruction rate (inst/s) -host_mem_usage 189900 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 162370166 # Simulator tick rate (ticks/s) +host_inst_rate 147781 # Simulator instruction rate (inst/s) +host_mem_usage 191596 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 73371409 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 6a2eadca9..f0bdf09de 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr index 28251ddf8..bb8489f81 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 779993228..3560f6496 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:46 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index af7d3609f..5c25b785f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59950 # Simulator instruction rate (inst/s) -host_mem_usage 197352 # Number of bytes of host memory used +host_inst_rate 73131 # Simulator instruction rate (inst/s) +host_mem_usage 199016 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 402241104 # Simulator tick rate (ticks/s) +host_tick_rate 490513834 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.131171 # ms system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.063032 # ms system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -222,15 +204,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 1 # m system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 83f026450..766c4f486 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -67,9 +67,12 @@ CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false UnifiedTLB=true +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr index 5ff857a03..eabe42249 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 77c8639ab..7b1955a4b 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:37:22 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:37:50 +M5 compiled Feb 16 2009 00:16:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:16:42 M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello World! Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 6c370ab2d..20921ce17 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 10079 # Simulator instruction rate (inst/s) -host_mem_usage 192068 # Number of bytes of host memory used -host_seconds 0.56 # Real time elapsed on the host -host_tick_rate 5037819 # Simulator tick rate (ticks/s) +host_inst_rate 24803 # Simulator instruction rate (inst/s) +host_mem_usage 193824 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 12384497 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 9ef900f1f..d6fb3e91a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -67,9 +67,12 @@ CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false UnifiedTLB=true +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -99,12 +102,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -136,12 +138,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -173,12 +174,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr index 5ff857a03..eabe42249 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 17fb9f581..a5bd2cd4d 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:37:22 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:37:51 +M5 compiled Feb 16 2009 00:16:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:16:42 M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello World! Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index d5658e44c..de10d4a74 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334992 # Simulator instruction rate (inst/s) -host_mem_usage 199532 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1887416058 # Simulator tick rate (ticks/s) +host_inst_rate 26568 # Simulator instruction rate (inst/s) +host_mem_usage 201268 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 151609105 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.071081 # ms system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -135,15 +126,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.053552 # ms system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # m system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 7ebff17bf..970388ae5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr index ee69ae99e..eabe42249 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout index 946edd9f0..eefaf1737 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:47 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 8a19f5ea4..b09b910ba 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 371297 # Simulator instruction rate (inst/s) -host_mem_usage 191740 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 185101425 # Simulator tick rate (ticks/s) +host_inst_rate 25851 # Simulator instruction rate (inst/s) +host_mem_usage 193720 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 13060676 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index c8a9fb583..f68b9582f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 92edc3116..fcae28521 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:19 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 7d5ee5db9..cf7518d98 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 419811 # Simulator instruction rate (inst/s) -host_mem_usage 199192 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2213741040 # Simulator tick rate (ticks/s) +host_inst_rate 21374 # Simulator instruction rate (inst/s) +host_mem_usage 201092 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 116036277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.107991 # ms system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.047734 # ms system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -207,15 +189,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # m system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 140ac8ef9..1a9a034e8 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr index 72ba90ece..94d399eab 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,4 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 66f32751d..5d849e6d3 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 18:30:07 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:19:16 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 2ee3e5703..a5ec37276 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5132 # Simulator instruction rate (inst/s) -host_mem_usage 192872 # Number of bytes of host memory used -host_seconds 1.85 # Real time elapsed on the host -host_tick_rate 2983162 # Simulator tick rate (ticks/s) +host_inst_rate 51320 # Simulator instruction rate (inst/s) +host_mem_usage 193224 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 29796099 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 6b3961ac8..d1edd6c59 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr index 72ba90ece..94d399eab 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,4 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index e9fb59225..23d83ecb3 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:57:21 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:19:16 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 4bf18211b..58aaf6112 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 494241 # Simulator instruction rate (inst/s) -host_mem_usage 200332 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1743803782 # Simulator tick rate (ticks/s) +host_inst_rate 63293 # Simulator instruction rate (inst/s) +host_mem_usage 200624 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 225441997 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.076497 # ms system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.020731 # ms system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -207,15 +189,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # m system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 62ebb142a..9c8da927d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr index fc5805f9e..eabe42249 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 958798ce3..73f0d5969 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:54 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. Hello world! Hello world! Exiting @ tick 14251500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index ecc7ae363..c9242b886 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1595 # Nu global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted global.BPredUnit.lookups 5548 # Number of BP lookups global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -host_inst_rate 85524 # Simulator instruction rate (inst/s) -host_mem_usage 199540 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 95322021 # Simulator tick rate (ticks/s) +host_inst_rate 67823 # Simulator instruction rate (inst/s) +host_mem_usage 201212 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 75589135 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. @@ -195,15 +195,6 @@ system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements @@ -369,15 +360,6 @@ system.cpu.icache.overall_mshr_uncacheable_latency_1 0 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 6 # number of replacements system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements @@ -707,15 +689,6 @@ system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index b0fb0c129..102ce19a3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -107,12 +110,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +283,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -318,12 +319,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 1f6eb4b07..d0efe85b3 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:55 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d80957aed..0584aa2e2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 2923 # Nu global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted global.BPredUnit.lookups 11413 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 55497 # Simulator instruction rate (inst/s) -host_mem_usage 199732 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -host_tick_rate 106451563 # Simulator tick rate (ticks/s) +host_inst_rate 30716 # Simulator instruction rate (inst/s) +host_mem_usage 201632 # Number of bytes of host memory used +host_seconds 0.47 # Real time elapsed on the host +host_tick_rate 58973694 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. @@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.031593 # ms system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -205,15 +196,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.048804 # ms system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -388,15 +370,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # m system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index bd75b6dd2..c81ee3264 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr index ee69ae99e..eabe42249 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index 7103e96c6..cb610b0c6 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:56 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index fa5cbc97a..d9897842c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 641188 # Simulator instruction rate (inst/s) -host_mem_usage 191520 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 319099476 # Simulator tick rate (ticks/s) +host_inst_rate 61727 # Simulator instruction rate (inst/s) +host_mem_usage 193528 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 30956425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 35e384fb9..8777df95f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr index ee69ae99e..eabe42249 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 796520389..65fc22a94 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:56 +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index f45ffd986..323f23c0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 494848 # Simulator instruction rate (inst/s) -host_mem_usage 199068 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1383502218 # Simulator tick rate (ticks/s) +host_inst_rate 71328 # Simulator instruction rate (inst/s) +host_mem_usage 200972 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 200611199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated @@ -66,15 +66,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.042257 # ms system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -128,15 +119,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.018396 # ms system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # m system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 9d8e5c8ed..56dec3815 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -36,6 +36,7 @@ side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -74,12 +75,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -111,12 +111,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -146,6 +145,7 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=1 defer_registration=false @@ -184,12 +184,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -221,12 +220,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -264,6 +262,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -283,6 +282,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -317,12 +317,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -350,12 +349,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -485,16 +483,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -863,16 +867,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr index d445cb942..5a1d0bef0 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -1,5 +1,7 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: 97861500: Trying to launch CPU number 1! -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 2e7c9e61b..8c40366bc 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:48:26 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:50 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 55ea1f24a..8ed468432 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1560779 # Simulator instruction rate (inst/s) -host_mem_usage 292076 # Number of bytes of host memory used -host_seconds 40.46 # Real time elapsed on the host -host_tick_rate 46222973494 # Simulator tick rate (ticks/s) +host_inst_rate 2804596 # Simulator instruction rate (inst/s) +host_mem_usage 292704 # Number of bytes of host memory used +host_seconds 22.52 # Real time elapsed on the host +host_tick_rate 83058483755 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -60,15 +60,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0 # m system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.replacements 1978962 # number of replacements system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -128,15 +119,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0 # m system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.icache.replacements 884404 # number of replacements system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -294,15 +276,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0 # m system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.dcache.replacements 62338 # number of replacements system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -362,15 +335,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0 # m system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.icache.replacements 103091 # number of replacements system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -513,15 +477,6 @@ system.iocache.overall_mshr_miss_rate 0 # ms system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -577,15 +532,6 @@ system.l2c.overall_mshr_miss_rate 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 1056803 # number of replacements system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index a6db3884d..15e3ec649 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -36,6 +36,7 @@ side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -74,12 +75,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -111,12 +111,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -154,6 +153,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -173,6 +173,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -207,12 +208,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -240,12 +240,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -375,16 +374,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -753,16 +758,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr index 1a557daf8..83c71fc5c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr @@ -1,4 +1,5 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 2ea90534e..778e7a3b4 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:47:54 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:52 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 19b0c43d9..749efa0bc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1610025 # Simulator instruction rate (inst/s) -host_mem_usage 290828 # Number of bytes of host memory used -host_seconds 37.29 # Real time elapsed on the host -host_tick_rate 49056237387 # Simulator tick rate (ticks/s) +host_inst_rate 2844723 # Simulator instruction rate (inst/s) +host_mem_usage 291452 # Number of bytes of host memory used +host_seconds 21.11 # Real time elapsed on the host +host_tick_rate 86676065750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -60,15 +60,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0 # ms system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 2042700 # number of replacements system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -128,15 +119,6 @@ system.cpu.icache.overall_mshr_miss_rate 0 # ms system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 919594 # number of replacements system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -291,15 +273,6 @@ system.iocache.overall_mshr_miss_rate 0 # ms system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -355,15 +328,6 @@ system.l2c.overall_mshr_miss_rate 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 1050724 # number of replacements system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index de9bfc9e4..f8e47e1b8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -36,6 +36,7 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -71,12 +72,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -108,12 +108,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -143,6 +142,7 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=1 defer_registration=false @@ -178,12 +178,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -215,12 +214,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -258,6 +256,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -277,6 +276,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -311,12 +311,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -344,12 +343,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -479,16 +477,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -857,16 +861,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index dad1cad88..e077a7fd9 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -1,5 +1,7 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: 591544000: Trying to launch CPU number 1! -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 9f8bf8070..6b56db972 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:47:52 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:51 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 2f2449fdc..4a6754053 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 741695 # Simulator instruction rate (inst/s) -host_mem_usage 289172 # Number of bytes of host memory used -host_seconds 80.11 # Real time elapsed on the host -host_tick_rate 24616375840 # Simulator tick rate (ticks/s) +host_inst_rate 1382701 # Simulator instruction rate (inst/s) +host_mem_usage 289788 # Number of bytes of host memory used +host_seconds 42.97 # Real time elapsed on the host +host_tick_rate 45890646030 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated @@ -88,15 +88,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # m system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.replacements 1338610 # number of replacements system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -162,15 +153,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0.016917 # m system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.icache.replacements 915684 # number of replacements system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -356,15 +338,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # m system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.dcache.replacements 53724 # number of replacements system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -430,15 +403,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0.016597 # m system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.icache.replacements 86896 # number of replacements system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -597,15 +561,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41698 # number of replacements system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -684,15 +639,6 @@ system.l2c.overall_mshr_miss_rate 0.256233 # ms system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 399005 # number of replacements system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 3e8e04375..468bf0248 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -36,6 +36,7 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -71,12 +72,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -108,12 +108,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -151,6 +150,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -170,6 +170,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -204,12 +205,11 @@ latency=50000 max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -237,12 +237,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -372,16 +371,22 @@ pio=system.iobus.port[1] [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -750,16 +755,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr index 1a557daf8..83c71fc5c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr @@ -1,4 +1,5 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index b196d52a3..ba86a45b9 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:47:59 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:52 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 76e60eed0..cbf231e85 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 715830 # Simulator instruction rate (inst/s) -host_mem_usage 287924 # Number of bytes of host memory used -host_seconds 78.52 # Real time elapsed on the host -host_tick_rate 24582295405 # Simulator tick rate (ticks/s) +host_inst_rate 1953289 # Simulator instruction rate (inst/s) +host_mem_usage 288556 # Number of bytes of host memory used +host_seconds 28.78 # Real time elapsed on the host +host_tick_rate 67077404616 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated @@ -88,15 +88,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.097749 # ms system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 1391606 # number of replacements system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -162,15 +153,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.016562 # ms system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 930429 # number of replacements system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -337,15 +319,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -423,15 +396,6 @@ system.l2c.overall_mshr_miss_rate 0.263528 # ms system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 394928 # number of replacements system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 836233457..014feb13e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr index a1d152694..c0312fe31 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout index 539afef68..103b40a61 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:27:20 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 51d5de7dc..1e8dfa007 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4911987 # Simulator instruction rate (inst/s) -host_mem_usage 189996 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 2448419888 # Simulator tick rate (ticks/s) +host_inst_rate 4171159 # Simulator instruction rate (inst/s) +host_mem_usage 191588 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2080999983 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 0f1cefdac..84839b10d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr index a1d152694..c0312fe31 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index 337a3a052..d93e92292 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:29:51 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 041421492..66e101984 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 883179 # Simulator instruction rate (inst/s) -host_mem_usage 197372 # Number of bytes of host memory used -host_seconds 0.57 # Real time elapsed on the host -host_tick_rate 1301859777 # Simulator tick rate (ticks/s) +host_inst_rate 1619389 # Simulator instruction rate (inst/s) +host_mem_usage 199040 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +host_tick_rate 2386410783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.003463 # ms system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000806 # ms system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -222,15 +204,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 1 # m system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 78394da28..af926f81c 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 @@ -46,12 +49,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -83,12 +85,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -125,9 +126,12 @@ system=system [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=1 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 @@ -159,12 +163,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -196,12 +199,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -238,9 +240,12 @@ system=system [system.cpu2] type=AtomicSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=2 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu2.dtb function_trace=false function_trace_start=0 @@ -272,12 +277,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -309,12 +313,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -351,9 +354,12 @@ system=system [system.cpu3] type=AtomicSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=3 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu3.dtb function_trace=false function_trace_start=0 @@ -385,12 +391,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -422,12 +427,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -472,12 +476,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 496a7244f..75c83d350 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -1,5 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index b1dd747a5..0c841053d 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:11 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 12655b8fd..aecd60ac7 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2958551 # Simulator instruction rate (inst/s) -host_mem_usage 1121980 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host -host_tick_rate 369689554 # Simulator tick rate (ticks/s) +host_inst_rate 4658528 # Simulator instruction rate (inst/s) +host_mem_usage 1123612 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host +host_tick_rate 582033733 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -52,15 +52,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0 # m system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.replacements 61 # number of replacements system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -120,15 +111,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0 # m system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.icache.replacements 152 # number of replacements system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -190,15 +172,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0 # m system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.dcache.replacements 61 # number of replacements system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -258,15 +231,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0 # m system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.icache.replacements 152 # number of replacements system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -328,15 +292,6 @@ system.cpu2.dcache.overall_mshr_miss_rate 0 # m system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.dcache.replacements 61 # number of replacements system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -396,15 +351,6 @@ system.cpu2.icache.overall_mshr_miss_rate 0 # m system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.icache.replacements 152 # number of replacements system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -466,15 +412,6 @@ system.cpu3.dcache.overall_mshr_miss_rate 0 # m system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.dcache.replacements 61 # number of replacements system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -534,15 +471,6 @@ system.cpu3.icache.overall_mshr_miss_rate 0 # m system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.icache.replacements 152 # number of replacements system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -608,15 +536,6 @@ system.l2c.overall_mshr_miss_rate 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 0077a0004..2d269877c 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,9 +123,12 @@ system=system [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=1 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 @@ -153,12 +157,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -190,12 +193,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -232,9 +234,12 @@ system=system [system.cpu2] type=TimingSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=2 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu2.dtb function_trace=false function_trace_start=0 @@ -263,12 +268,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -300,12 +304,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -342,9 +345,12 @@ system=system [system.cpu3] type=TimingSimpleCPU children=dcache dtb icache itb tracer workload +checker=Null clock=500 cpu_id=3 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu3.dtb function_trace=false function_trace_start=0 @@ -373,12 +379,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -410,12 +415,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -460,12 +464,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 496a7244f..75c83d350 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -1,5 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index edbace7b2..edab14950 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:30:50 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 5dc3a25b6..1fb750134 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1370296 # Simulator instruction rate (inst/s) -host_mem_usage 204468 # Number of bytes of host memory used -host_seconds 1.46 # Real time elapsed on the host -host_tick_rate 505820394 # Simulator tick rate (ticks/s) +host_inst_rate 1521087 # Simulator instruction rate (inst/s) +host_mem_usage 206108 # Number of bytes of host memory used +host_seconds 1.32 # Real time elapsed on the host +host_tick_rate 561475161 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # m system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.replacements 61 # number of replacements system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0.000926 # m system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.icache.replacements 152 # number of replacements system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -220,15 +202,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # m system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.dcache.replacements 61 # number of replacements system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -294,15 +267,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0.000926 # m system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.icache.replacements 152 # number of replacements system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -376,15 +340,6 @@ system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # m system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.dcache.replacements 61 # number of replacements system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -450,15 +405,6 @@ system.cpu2.icache.overall_mshr_miss_rate 0.000926 # m system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.icache.replacements 152 # number of replacements system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -532,15 +478,6 @@ system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # m system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.dcache.replacements 61 # number of replacements system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -606,15 +543,6 @@ system.cpu3.icache.overall_mshr_miss_rate 0.000926 # m system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.icache.replacements 152 # number of replacements system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -698,15 +626,6 @@ system.l2c.overall_mshr_miss_rate 0.925486 # ms system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 3ae48f3b4..f9dfac7de 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -36,12 +36,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -85,12 +84,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -134,12 +132,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -183,12 +180,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -232,12 +228,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -281,12 +276,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -330,12 +324,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -379,12 +372,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -422,12 +414,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr index 507652626..b09f497b8 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -71,4 +71,4 @@ system.cpu5: completed 90000 read accesses @243633950 system.cpu4: completed 90000 read accesses @243710816 system.cpu2: completed 90000 read accesses @243974160 system.cpu6: completed 100000 read accesses @268915439 -warn: be nice to actually delete the event here +hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index a9b5dbd1a..9d66255a0 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:11 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 07a437af0..7f0400045 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 324480 # Number of bytes of host memory used -host_seconds 257.27 # Real time elapsed on the host -host_tick_rate 1045249 # Simulator tick rate (ticks/s) +host_mem_usage 326140 # Number of bytes of host memory used +host_seconds 207.97 # Real time elapsed on the host +host_tick_rate 1293031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated @@ -66,15 +66,6 @@ system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # ms system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l1c.replacements 28158 # number of replacements system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -145,15 +136,6 @@ system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # ms system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l1c.replacements 27563 # number of replacements system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -224,15 +206,6 @@ system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # ms system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.l1c.replacements 27725 # number of replacements system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -303,15 +276,6 @@ system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # ms system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.l1c.replacements 27562 # number of replacements system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -382,15 +346,6 @@ system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # ms system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu4.l1c.replacements 27721 # number of replacements system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -461,15 +416,6 @@ system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # ms system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu5.l1c.replacements 27632 # number of replacements system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -540,15 +486,6 @@ system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # ms system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu6.l1c.replacements 28139 # number of replacements system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -619,15 +556,6 @@ system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # ms system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu7.l1c.replacements 27627 # number of replacements system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -711,15 +639,6 @@ system.l2c.overall_mshr_miss_rate 0.570509 # ms system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.l2c.replacements 73303 # number of replacements system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 3bf761d34..a2a52df64 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -36,6 +36,7 @@ side_b=drivesys.membus.port[0] [drivesys.cpu] type=AtomicSimpleCPU children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -88,6 +89,7 @@ image=drivesys.disk0.image type=CowDiskImage children=child child=drivesys.disk0.image.child +image_file= read_only=false table_size=65536 @@ -107,6 +109,7 @@ image=drivesys.disk2.image type=CowDiskImage children=child child=drivesys.disk2.image.child +image_file= read_only=false table_size=65536 @@ -215,16 +218,22 @@ pio=drivesys.iobus.port[1] [drivesys.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -594,16 +603,22 @@ pio=drivesys.iobus.port[22] [drivesys.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -703,7 +718,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -725,6 +740,7 @@ side_b=testsys.membus.port[0] [testsys.cpu] type=AtomicSimpleCPU children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -777,6 +793,7 @@ image=testsys.disk0.image type=CowDiskImage children=child child=testsys.disk0.image.child +image_file= read_only=false table_size=65536 @@ -796,6 +813,7 @@ image=testsys.disk2.image type=CowDiskImage children=child child=testsys.disk2.image.child +image_file= read_only=false table_size=65536 @@ -904,16 +922,22 @@ pio=testsys.iobus.port[1] [testsys.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -1283,16 +1307,22 @@ pio=testsys.iobus.port[22] [testsys.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr index 73103c03f..c18ca3505 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -1,6 +1,7 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections -warn: kernel located at: /dist/m5/system/binaries/vmlinux +For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: Obsolete M5 ivlb instruction encountered. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/fcbd217d +hack: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 361a090ba..70f17d877 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 14 2008 21:47:07 -M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 -M5 commit date Sun Dec 14 21:45:15 2008 -0800 -M5 started Dec 14 2008 21:48:20 -M5 executing on tater +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:51 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 80d312c00..267fa9175 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 184651715 # Simulator instruction rate (inst/s) -host_mem_usage 478008 # Number of bytes of host memory used -host_seconds 1.48 # Real time elapsed on the host -host_tick_rate 135077074315 # Simulator tick rate (ticks/s) +host_inst_rate 151383583 # Simulator instruction rate (inst/s) +host_mem_usage 478624 # Number of bytes of host memory used +host_seconds 1.81 # Real time elapsed on the host +host_tick_rate 110738300112 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 161951915284 # Simulator instruction rate (inst/s) -host_mem_usage 478008 # Number of bytes of host memory used +host_inst_rate 133483805176 # Simulator instruction rate (inst/s) +host_mem_usage 478624 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 438603795 # Simulator tick rate (ticks/s) +host_tick_rate 360871442 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -- cgit v1.2.3 From f02df8cb7400d59c338abf44d2f7adfc9a665fa0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:16:29 -0800 Subject: X86: Update stats for in place TLB miss handling. --- .../00.gzip/ref/x86/linux/simple-atomic/simout | 10 ++--- .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 16 ++++---- .../00.gzip/ref/x86/linux/simple-timing/simout | 10 ++--- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 40 +++++++++--------- .../long/10.mcf/ref/x86/linux/simple-atomic/simout | 10 ++--- .../10.mcf/ref/x86/linux/simple-atomic/stats.txt | 16 ++++---- .../long/10.mcf/ref/x86/linux/simple-timing/simout | 10 ++--- .../10.mcf/ref/x86/linux/simple-timing/stats.txt | 40 +++++++++--------- .../20.parser/ref/x86/linux/simple-atomic/simout | 10 ++--- .../ref/x86/linux/simple-atomic/stats.txt | 16 ++++---- .../20.parser/ref/x86/linux/simple-timing/simout | 10 ++--- .../ref/x86/linux/simple-timing/stats.txt | 42 +++++++++---------- .../60.bzip2/ref/x86/linux/simple-atomic/simout | 10 ++--- .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt | 16 ++++---- .../60.bzip2/ref/x86/linux/simple-timing/simout | 10 ++--- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 42 +++++++++---------- .../70.twolf/ref/x86/linux/simple-atomic/simout | 12 +++--- .../70.twolf/ref/x86/linux/simple-atomic/stats.txt | 14 +++---- .../70.twolf/ref/x86/linux/simple-timing/simout | 10 ++--- .../70.twolf/ref/x86/linux/simple-timing/stats.txt | 36 ++++++++-------- .../00.hello/ref/x86/linux/simple-atomic/simout | 10 ++--- .../00.hello/ref/x86/linux/simple-atomic/stats.txt | 16 ++++---- .../00.hello/ref/x86/linux/simple-timing/simout | 10 ++--- .../00.hello/ref/x86/linux/simple-timing/stats.txt | 48 +++++++++++----------- 24 files changed, 233 insertions(+), 231 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 5eb2ed956..1d076eebd 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:00:03 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 962935342000 because target called exit() +Exiting @ tick 962928676500 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index cf444d872..fd612c556 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1622364 # Simulator instruction rate (inst/s) -host_mem_usage 197488 # Number of bytes of host memory used -host_seconds 998.15 # Real time elapsed on the host -host_tick_rate 964717823 # Simulator tick rate (ticks/s) +host_inst_rate 977325 # Simulator instruction rate (inst/s) +host_mem_usage 197144 # Number of bytes of host memory used +host_seconds 1656.94 # Real time elapsed on the host +host_tick_rate 581149945 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 0.962935 # Number of seconds simulated -sim_ticks 962935342000 # Number of ticks simulated +sim_seconds 0.962929 # Number of seconds simulated +sim_ticks 962928676500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925870685 # number of cpu cycles simulated +system.cpu.numCycles 1925857354 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed -system.cpu.num_refs 607160031 # Number of memory references +system.cpu.num_refs 607148814 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 547d12c0b..f6eeaa6d1 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:02:02 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554098117000 because target called exit() +Exiting @ tick 2554084828000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 3681e4f0c..f6f018cc6 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1065301 # Simulator instruction rate (inst/s) -host_mem_usage 204932 # Number of bytes of host memory used -host_seconds 1520.10 # Real time elapsed on the host -host_tick_rate 1680214432 # Simulator tick rate (ticks/s) +host_inst_rate 751612 # Simulator instruction rate (inst/s) +host_mem_usage 204588 # Number of bytes of host memory used +host_seconds 2154.53 # Real time elapsed on the host +host_tick_rate 1185451424 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 2.554098 # Number of seconds simulated -sim_ticks 2554098117000 # Number of ticks simulated +sim_seconds 2.554085 # Number of seconds simulated +sim_ticks 2554084828000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.609383 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.610676 # Cycle average of tags in use system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1593417000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 1592465000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925870644 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1925857355 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925869923 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1925856634 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671109.463245 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2671091.031900 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925870644 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1925857355 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925869923 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1925856634 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 721 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925870644 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1925857355 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925869923 # number of overall hits +system.cpu.icache.overall_hits 1925856634 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.724449 # Cycle average of tags in use -system.cpu.icache.total_refs 1925869923 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 658.724808 # Cycle average of tags in use +system.cpu.icache.total_refs 1925856634 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16428.000401 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16428.009263 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108196234 # number of cpu cycles simulated +system.cpu.numCycles 5108169656 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed -system.cpu.num_refs 607160031 # Number of memory references +system.cpu.num_refs 607148814 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 225df2c54..b197a138a 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:06:25 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165726426000 because target called exit() +Exiting @ tick 164697191500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 16a3e187b..412b43cf4 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1454099 # Simulator instruction rate (inst/s) -host_mem_usage 332016 # Number of bytes of host memory used -host_seconds 185.47 # Real time elapsed on the host -host_tick_rate 893563512 # Simulator tick rate (ticks/s) +host_inst_rate 738696 # Simulator instruction rate (inst/s) +host_mem_usage 331676 # Number of bytes of host memory used +host_seconds 365.09 # Real time elapsed on the host +host_tick_rate 451120089 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.165726 # Number of seconds simulated -sim_ticks 165726426000 # Number of ticks simulated +sim_seconds 0.164697 # Number of seconds simulated +sim_ticks 164697191500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331452853 # number of cpu cycles simulated +system.cpu.numCycles 329394384 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references +system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index fdaf99f0e..ea464f620 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:06:48 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 495377140000 because target called exit() +Exiting @ tick 493318720000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index f4739c53b..f7746cc78 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 939339 # Simulator instruction rate (inst/s) -host_mem_usage 339456 # Number of bytes of host memory used -host_seconds 287.10 # Real time elapsed on the host -host_tick_rate 1725433923 # Simulator tick rate (ticks/s) +host_inst_rate 472092 # Simulator instruction rate (inst/s) +host_mem_usage 339120 # Number of bytes of host memory used +host_seconds 571.26 # Real time elapsed on the host +host_tick_rate 863564130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.495377 # Number of seconds simulated -sim_ticks 495377140000 # Number of ticks simulated +sim_seconds 0.493319 # Number of seconds simulated +sim_ticks 493318720000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.561270 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 165886080000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 329394385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 329393578 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 408170.480793 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 329394385 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits +system.cpu.icache.demand_hits 329393578 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 329394385 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331451998 # number of overall hits +system.cpu.icache.overall_hits 329393578 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use -system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 665.896527 # Cycle average of tags in use +system.cpu.icache.total_refs 329393578 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18017.047263 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990754280 # number of cpu cycles simulated +system.cpu.numCycles 986637440 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references +system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 0154cb675..6f49cefcf 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:09:31 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868682305500 because target called exit() +Exiting @ tick 868476152500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 2072caa4b..a32bcd78e 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1649324 # Simulator instruction rate (inst/s) -host_mem_usage 201208 # Number of bytes of host memory used -host_seconds 906.72 # Real time elapsed on the host -host_tick_rate 958044415 # Simulator tick rate (ticks/s) +host_inst_rate 954040 # Simulator instruction rate (inst/s) +host_mem_usage 200820 # Number of bytes of host memory used +host_seconds 1567.53 # Real time elapsed on the host +host_tick_rate 554042856 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated -sim_seconds 0.868682 # Number of seconds simulated -sim_ticks 868682305500 # Number of ticks simulated +sim_seconds 0.868476 # Number of seconds simulated +sim_ticks 868476152500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737364612 # number of cpu cycles simulated +system.cpu.numCycles 1736952306 # number of cpu cycles simulated system.cpu.num_insts 1495482356 # Number of instructions executed -system.cpu.num_refs 533548971 # Number of memory references +system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 6d4d2b6e7..bc32d8a8e 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:11:36 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2391369984000 because target called exit() +Exiting @ tick 2390957741000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 923ce5951..c30384fe4 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1421036 # Simulator instruction rate (inst/s) -host_mem_usage 208620 # Number of bytes of host memory used -host_seconds 1052.39 # Real time elapsed on the host -host_tick_rate 2272325062 # Simulator tick rate (ticks/s) +host_inst_rate 732305 # Simulator instruction rate (inst/s) +host_mem_usage 208264 # Number of bytes of host memory used +host_seconds 2042.16 # Real time elapsed on the host +host_tick_rate 1170799737 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated -sim_seconds 2.391370 # Number of seconds simulated -sim_ticks 2391369984000 # Number of ticks simulated +sim_seconds 2.390958 # Number of seconds simulated +sim_ticks 2390957741000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.149487 # Cycle average of tags in use system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 12270471000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1736952307 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1736949494 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 617472.269463 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1736952307 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1736949494 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1736952307 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1737361737 # number of overall hits +system.cpu.icache.overall_hits 1736949494 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use -system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 873.828248 # Cycle average of tags in use +system.cpu.icache.total_refs 1736949494 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17171.450430 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 1312958337000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4782739968 # number of cpu cycles simulated +system.cpu.numCycles 4781915482 # number of cpu cycles simulated system.cpu.num_insts 1495482356 # Number of instructions executed -system.cpu.num_refs 533548971 # Number of memory references +system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 2b254f0b1..66e6ec11e 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:15:07 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2835189187500 because target called exit() +Exiting @ tick 2829164056000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index c42805444..a2ce3d743 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2107205 # Simulator instruction rate (inst/s) -host_mem_usage 197384 # Number of bytes of host memory used -host_seconds 2208.22 # Real time elapsed on the host -host_tick_rate 1283923835 # Simulator tick rate (ticks/s) +host_inst_rate 1367500 # Simulator instruction rate (inst/s) +host_mem_usage 197040 # Number of bytes of host memory used +host_seconds 3402.69 # Real time elapsed on the host +host_tick_rate 831449663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated -sim_seconds 2.835189 # Number of seconds simulated -sim_ticks 2835189187500 # Number of ticks simulated +sim_seconds 2.829164 # Number of seconds simulated +sim_ticks 2829164056000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5670378376 # number of cpu cycles simulated +system.cpu.numCycles 5658328113 # number of cpu cycles simulated system.cpu.num_insts 4653176258 # Number of instructions executed -system.cpu.num_refs 1686313781 # Number of memory references +system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 97a038291..3f9a5b324 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:16:41 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 7645209486000 because target called exit() +Exiting @ tick 7633159262000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 429f68d1b..bf04eb747 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1048991 # Simulator instruction rate (inst/s) -host_mem_usage 204820 # Number of bytes of host memory used -host_seconds 4435.86 # Real time elapsed on the host -host_tick_rate 1723500836 # Simulator tick rate (ticks/s) +host_inst_rate 953941 # Simulator instruction rate (inst/s) +host_mem_usage 204484 # Number of bytes of host memory used +host_seconds 4877.84 # Real time elapsed on the host +host_tick_rate 1564863626 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated -sim_seconds 7.645209 # Number of seconds simulated -sim_ticks 7645209486000 # Number of ticks simulated +sim_seconds 7.633159 # Number of seconds simulated +sim_ticks 7633159262000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377593 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78020119000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5670378338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5670377663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8400559.500741 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5670378338 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5670377663 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5670378338 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5670377663 # number of overall hits +system.cpu.icache.overall_hits 5658327439 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.334555 # Cycle average of tags in use -system.cpu.icache.total_refs 5670377663 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use +system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25740.146811 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6038871723000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15290418972 # number of cpu cycles simulated +system.cpu.numCycles 15266318524 # number of cpu cycles simulated system.cpu.num_insts 4653176258 # Number of instructions executed -system.cpu.num_refs 1686313781 # Number of memory references +system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index fd5d4825d..100c59b7e 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:24:38 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:54:15 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +29,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009362500 because target called exit() +122 123 124 Exiting @ tick 130009234000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 5f9bdeb8f..f3c94835b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1349784 # Simulator instruction rate (inst/s) -host_mem_usage 204760 # Number of bytes of host memory used -host_seconds 161.95 # Real time elapsed on the host -host_tick_rate 802781753 # Simulator tick rate (ticks/s) +host_inst_rate 744144 # Simulator instruction rate (inst/s) +host_mem_usage 204416 # Number of bytes of host memory used +host_seconds 293.75 # Real time elapsed on the host +host_tick_rate 442578451 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009362500 # Number of ticks simulated +sim_ticks 130009234000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018726 # number of cpu cycles simulated +system.cpu.numCycles 260018469 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed -system.cpu.num_refs 77165364 # Number of memory references +system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index c8bd5d18c..4e1b45a86 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:27:21 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:57:42 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 @@ -29,4 +29,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469692000 because target called exit() +122 123 124 Exiting @ tick 337469588000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 21956901a..a85a5c18f 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1082313 # Simulator instruction rate (inst/s) -host_mem_usage 212196 # Number of bytes of host memory used -host_seconds 201.97 # Real time elapsed on the host -host_tick_rate 1670883730 # Simulator tick rate (ticks/s) +host_inst_rate 565225 # Simulator instruction rate (inst/s) +host_mem_usage 211860 # Number of bytes of host memory used +host_seconds 386.74 # Real time elapsed on the host +host_tick_rate 872598896 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469692000 # Number of ticks simulated +sim_ticks 337469588000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.541033 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013881 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # ms system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.619859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018574 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013881 # number of demand (read+write) hits +system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 4693 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018574 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013881 # number of overall hits +system.cpu.icache.overall_hits 260013777 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991128 # Cycle average of tags in use -system.cpu.icache.total_refs 260013881 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use +system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720476 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939384 # number of cpu cycles simulated +system.cpu.numCycles 674939176 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed -system.cpu.num_refs 77165364 # Number of memory references +system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 5d849e6d3..60f35ee0f 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:19:16 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:59:09 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5513500 because target called exit() +Exiting @ tick 5484500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index a5ec37276..454f55a63 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51320 # Simulator instruction rate (inst/s) -host_mem_usage 193224 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 29796099 # Simulator tick rate (ticks/s) +host_inst_rate 165270 # Simulator instruction rate (inst/s) +host_mem_usage 192880 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 95268287 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5513500 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5484500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11028 # number of cpu cycles simulated +system.cpu.numCycles 10970 # number of cpu cycles simulated system.cpu.num_insts 9484 # Number of instructions executed -system.cpu.num_refs 2003 # Number of memory references +system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 23d83ecb3..03584f0f8 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:19:16 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:59:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33842000 because target called exit() +Exiting @ tick 33815000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 58aaf6112..d6a4a1186 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 63293 # Simulator instruction rate (inst/s) -host_mem_usage 200624 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 225441997 # Simulator tick rate (ticks/s) +host_inst_rate 184291 # Simulator instruction rate (inst/s) +host_mem_usage 200284 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 654707739 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33842000 # Number of ticks simulated +sim_ticks 33815000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.592815 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 81.615734 # Cycle average of tags in use system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 10998 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 10971 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 10743 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.020782 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020731 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.020782 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.236842 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 47.118421 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 10998 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 10971 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10770 # number of demand (read+write) hits +system.cpu.icache.demand_hits 10743 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.020782 # miss rate for demand accesses system.cpu.icache.demand_misses 228 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020731 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.020782 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 10998 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 10971 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10770 # number of overall hits +system.cpu.icache.overall_hits 10743 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.020782 # miss rate for overall accesses system.cpu.icache.overall_misses 228 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020731 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.020782 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.523643 # Cycle average of tags in use -system.cpu.icache.total_refs 10770 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 107.556413 # Cycle average of tags in use +system.cpu.icache.total_refs 10743 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -192,14 +192,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.119087 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 129.158632 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67684 # number of cpu cycles simulated +system.cpu.numCycles 67630 # number of cpu cycles simulated system.cpu.num_insts 9484 # Number of instructions executed -system.cpu.num_refs 2003 # Number of memory references +system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3 From 1bfab291f1899a3e241977425339c799dc96fa9d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:18:45 -0800 Subject: CPU: Update stats now that there's no fetch in the middle of macroops. --- .../00.gzip/ref/sparc/linux/simple-timing/simout | 10 ++--- .../ref/sparc/linux/simple-timing/stats.txt | 38 ++++++++-------- .../00.gzip/ref/x86/linux/simple-atomic/simout | 1 + .../00.gzip/ref/x86/linux/simple-timing/simout | 8 ++-- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 50 ++++++++++----------- .../10.mcf/ref/sparc/linux/simple-timing/simout | 10 ++--- .../10.mcf/ref/sparc/linux/simple-timing/stats.txt | 38 ++++++++-------- .../long/10.mcf/ref/x86/linux/simple-timing/simout | 8 ++-- .../10.mcf/ref/x86/linux/simple-timing/stats.txt | 50 ++++++++++----------- .../20.parser/ref/x86/linux/simple-timing/simout | 8 ++-- .../ref/x86/linux/simple-timing/stats.txt | 52 +++++++++++----------- .../50.vortex/ref/sparc/linux/simple-timing/simout | 10 ++--- .../ref/sparc/linux/simple-timing/stats.txt | 52 +++++++++++----------- .../60.bzip2/ref/x86/linux/simple-timing/simout | 8 ++-- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 40 ++++++++--------- .../70.twolf/ref/sparc/linux/simple-timing/simout | 12 ++--- .../ref/sparc/linux/simple-timing/stats.txt | 36 +++++++-------- .../70.twolf/ref/x86/linux/simple-timing/simout | 8 ++-- .../70.twolf/ref/x86/linux/simple-timing/stats.txt | 48 ++++++++++---------- .../00.hello/ref/x86/linux/simple-timing/simout | 8 ++-- .../00.hello/ref/x86/linux/simple-timing/stats.txt | 48 ++++++++++---------- 21 files changed, 273 insertions(+), 270 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index d7c279dee..12ee4624b 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:50:17 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:33 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2080416155000 because target called exit() +Exiting @ tick 2076000961000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 5a55fc3e0..9a15c39dd 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1502574 # Simulator instruction rate (inst/s) -host_mem_usage 205236 # Number of bytes of host memory used -host_seconds 991.31 # Real time elapsed on the host -host_tick_rate 2098643273 # Simulator tick rate (ticks/s) +host_inst_rate 779483 # Simulator instruction rate (inst/s) +host_mem_usage 204800 # Number of bytes of host memory used +host_seconds 1910.91 # Real time elapsed on the host +host_tick_rate 1086392421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.080416 # Number of seconds simulated -sim_ticks 2080416155000 # Number of ticks simulated +sim_seconds 2.076001 # Number of seconds simulated +sim_ticks 2076000961000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316420 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_hits 1485111905 # number of overall hits system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1107 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use -system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.413769 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 82905 # number of replacements system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16358.028924 # Cycle average of tags in use system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61861 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4160832310 # number of cpu cycles simulated +system.cpu.numCycles 4152001922 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 1d076eebd..21fdf6d28 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -26,6 +26,7 @@ Uncompressed data compared correctly Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index f6eeaa6d1..1a67dff68 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:41:46 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554084828000 because target called exit() +Exiting @ tick 1814744167000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index f6f018cc6..44628642c 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 751612 # Simulator instruction rate (inst/s) -host_mem_usage 204588 # Number of bytes of host memory used -host_seconds 2154.53 # Real time elapsed on the host -host_tick_rate 1185451424 # Simulator tick rate (ticks/s) +host_inst_rate 759916 # Simulator instruction rate (inst/s) +host_mem_usage 204700 # Number of bytes of host memory used +host_seconds 2130.98 # Real time elapsed on the host +host_tick_rate 851601124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 2.554085 # Number of seconds simulated -sim_ticks 2554084828000 # Number of ticks simulated +sim_seconds 1.814744 # Number of seconds simulated +sim_ticks 1814744167000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.610676 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.900260 # Cycle average of tags in use system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1592465000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925857355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925856634 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1186515973 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671091.031900 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1645653.221914 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925857355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1186516694 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925856634 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1186515973 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925857355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1186516694 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925856634 # number of overall hits +system.cpu.icache.overall_hits 1186515973 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.724808 # Cycle average of tags in use -system.cpu.icache.total_refs 1925856634 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 659.165920 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16428.009263 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16488.807758 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108169656 # number of cpu cycles simulated +system.cpu.numCycles 3629488334 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed system.cpu.num_refs 607148814 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 380022b15..3aaf04828 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:53:06 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:31:11 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 366445521000 because target called exit() +Exiting @ tick 366435406000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index ac46d4baa..61025e455 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1327795 # Simulator instruction rate (inst/s) -host_mem_usage 337424 # Number of bytes of host memory used -host_seconds 183.64 # Real time elapsed on the host -host_tick_rate 1995461602 # Simulator tick rate (ticks/s) +host_inst_rate 712663 # Simulator instruction rate (inst/s) +host_mem_usage 336988 # Number of bytes of host memory used +host_seconds 342.15 # Real time elapsed on the host +host_tick_rate 1070988197 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.366446 # Number of seconds simulated -sim_ticks 366445521000 # Number of ticks simulated +sim_seconds 0.366435 # Number of seconds simulated +sim_ticks 366435406000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits +system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 882 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244430745 # number of overall hits +system.cpu.icache.overall_hits 244420630 # number of overall hits system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 882 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use -system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use +system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 732891042 # number of cpu cycles simulated +system.cpu.numCycles 732870812 # number of cpu cycles simulated system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_refs 105711442 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index ea464f620..160928f1d 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:36:40 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 493318720000 because target called exit() +Exiting @ tick 381620498000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index f7746cc78..cc9d82b6a 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 472092 # Simulator instruction rate (inst/s) -host_mem_usage 339120 # Number of bytes of host memory used -host_seconds 571.26 # Real time elapsed on the host -host_tick_rate 863564130 # Simulator tick rate (ticks/s) +host_inst_rate 587866 # Simulator instruction rate (inst/s) +host_mem_usage 339232 # Number of bytes of host memory used +host_seconds 458.76 # Real time elapsed on the host +host_tick_rate 831860032 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.493319 # Number of seconds simulated -sim_ticks 493318720000 # Number of ticks simulated +sim_seconds 0.381620 # Number of seconds simulated +sim_ticks 381620498000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.561270 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.427520 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165886080000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 127225609000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 329394385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 217696163 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 329393578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 408170.480793 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269758.805452 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 329394385 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 217696163 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 329393578 # number of demand (read+write) hits +system.cpu.icache.demand_hits 217695356 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 329394385 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 217696163 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 329393578 # number of overall hits +system.cpu.icache.overall_hits 217695356 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 665.896527 # Cycle average of tags in use -system.cpu.icache.total_refs 329393578 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.511426 # Cycle average of tags in use +system.cpu.icache.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18017.047263 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18002.978067 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 986637440 # number of cpu cycles simulated +system.cpu.numCycles 763240996 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index bc32d8a8e..e9b88174e 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:46:46 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2390957741000 because target called exit() +Exiting @ tick 1722352498000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index c30384fe4..422faa1c9 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 732305 # Simulator instruction rate (inst/s) -host_mem_usage 208264 # Number of bytes of host memory used -host_seconds 2042.16 # Real time elapsed on the host -host_tick_rate 1170799737 # Simulator tick rate (ticks/s) +host_inst_rate 782704 # Simulator instruction rate (inst/s) +host_mem_usage 208376 # Number of bytes of host memory used +host_seconds 1910.66 # Real time elapsed on the host +host_tick_rate 901442913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated -sim_seconds 2.390958 # Number of seconds simulated -sim_ticks 2390957741000 # Number of ticks simulated +sim_seconds 1.722352 # Number of seconds simulated +sim_ticks 1722352498000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.149487 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.831321 # Cycle average of tags in use system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270471000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 8217698000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1736952307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1068347064 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1736949494 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1068344251 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617472.269463 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379788.215784 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1736952307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1068347064 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1736949494 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1068344251 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1736952307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1068347064 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1736949494 # number of overall hits +system.cpu.icache.overall_hits 1068344251 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.828248 # Cycle average of tags in use -system.cpu.icache.total_refs 1736949494 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 886.488028 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.450430 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17216.029598 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1312958337000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 921771430000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4781915482 # number of cpu cycles simulated +system.cpu.numCycles 3444704996 # number of cpu cycles simulated system.cpu.num_insts 1495482356 # Number of instructions executed system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index 22ae99950..d6b904f84 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:54:04 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:32 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 205116920000 because target called exit() +Exiting @ tick 203376692000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 0cca434c3..3d50b13ca 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1934138 # Simulator instruction rate (inst/s) -host_mem_usage 214132 # Number of bytes of host memory used -host_seconds 70.39 # Real time elapsed on the host -host_tick_rate 2914099932 # Simulator tick rate (ticks/s) +host_inst_rate 683746 # Simulator instruction rate (inst/s) +host_mem_usage 213692 # Number of bytes of host memory used +host_seconds 199.11 # Real time elapsed on the host +host_tick_rate 1021439068 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.205117 # Number of seconds simulated -sim_ticks 205116920000 # Number of ticks simulated +sim_seconds 0.203377 # Number of seconds simulated +sim_ticks 203376692000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency @@ -77,62 +77,62 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks -system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits +system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136106788 # number of overall hits +system.cpu.icache.overall_hits 134366560 # number of overall hits system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use -system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use +system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19319.557750 # Cycle average of tags in use system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 410233840 # number of cpu cycles simulated +system.cpu.numCycles 406753384 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 3f9a5b324..bdea83ec4 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:32 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 7633159262000 because target called exit() +Exiting @ tick 5988064029000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index bf04eb747..55231f8a8 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 953941 # Simulator instruction rate (inst/s) -host_mem_usage 204484 # Number of bytes of host memory used -host_seconds 4877.84 # Real time elapsed on the host -host_tick_rate 1564863626 # Simulator tick rate (ticks/s) +host_inst_rate 929786 # Simulator instruction rate (inst/s) +host_mem_usage 204596 # Number of bytes of host memory used +host_seconds 5004.56 # Real time elapsed on the host +host_tick_rate 1196520405 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated -sim_seconds 7.633159 # Number of seconds simulated -sim_ticks 7633159262000 # Number of ticks simulated +sim_seconds 5.988064 # Number of seconds simulated +sim_ticks 5988064029000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.778559 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 58863922000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4013232881 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4013232206 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.194074 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4013232881 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4013232206 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4013232881 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5658327439 # number of overall hits +system.cpu.icache.overall_hits 4013232206 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use -system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232206 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25742.940427 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 4737814303000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15266318524 # number of cpu cycles simulated +system.cpu.numCycles 11976128058 # number of cpu cycles simulated system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 5a804eb57..b27d83682 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:56:10 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:33:08 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270578573000 because target called exit() +122 123 124 Exiting @ tick 270578335000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 571ff6af8..f73a0dcbf 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1319897 # Simulator instruction rate (inst/s) -host_mem_usage 209760 # Number of bytes of host memory used -host_seconds 146.56 # Real time elapsed on the host -host_tick_rate 1846186883 # Simulator tick rate (ticks/s) +host_inst_rate 732316 # Simulator instruction rate (inst/s) +host_mem_usage 209324 # Number of bytes of host memory used +host_seconds 264.15 # Real time elapsed on the host +host_tick_rate 1024317022 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270579 # Number of seconds simulated -sim_ticks 270578573000 # Number of ticks simulated +sim_seconds 0.270578 # Number of seconds simulated +sim_ticks 270578335000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # ms system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits +system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193433499 # number of overall hits +system.cpu.icache.overall_hits 193433261 # number of overall hits system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses system.cpu.icache.overall_misses 12288 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use -system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use +system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541157146 # number of cpu cycles simulated +system.cpu.numCycles 541156670 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 4e1b45a86..2a43627aa 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:57:42 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:58:47 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav @@ -29,4 +29,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469588000 because target called exit() +122 123 124 Exiting @ tick 250945484000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a85a5c18f..3d7cbb069 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 565225 # Simulator instruction rate (inst/s) -host_mem_usage 211860 # Number of bytes of host memory used -host_seconds 386.74 # Real time elapsed on the host -host_tick_rate 872598896 # Simulator tick rate (ticks/s) +host_inst_rate 660588 # Simulator instruction rate (inst/s) +host_mem_usage 211972 # Number of bytes of host memory used +host_seconds 330.91 # Real time elapsed on the host +host_tick_rate 758349031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated -sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469588000 # Number of ticks simulated +sim_seconds 0.250945 # Number of seconds simulated +sim_ticks 250945484000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits +system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013777 # number of overall hits +system.cpu.icache.overall_hits 173489673 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use -system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use +system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939176 # number of cpu cycles simulated +system.cpu.numCycles 501890968 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 03584f0f8..a84f40e19 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:59:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:37:33 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33815000 because target called exit() +Exiting @ tick 29717000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index d6a4a1186..b8a17302a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 184291 # Simulator instruction rate (inst/s) -host_mem_usage 200284 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 654707739 # Simulator tick rate (ticks/s) +host_inst_rate 139542 # Simulator instruction rate (inst/s) +host_mem_usage 200396 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 436046426 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33815000 # Number of ticks simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29717000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.615734 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.867418 # Cycle average of tags in use system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 10971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 6873 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10743 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 6645 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020782 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.033173 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020782 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.033173 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.118421 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29.144737 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 10971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 6873 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10743 # number of demand (read+write) hits +system.cpu.icache.demand_hits 6645 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020782 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.033173 # miss rate for demand accesses system.cpu.icache.demand_misses 228 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020782 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.033173 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 10971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 6873 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10743 # number of overall hits +system.cpu.icache.overall_hits 6645 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020782 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.033173 # miss rate for overall accesses system.cpu.icache.overall_misses 228 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020782 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.033173 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.556413 # Cycle average of tags in use -system.cpu.icache.total_refs 10743 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.639571 # Cycle average of tags in use +system.cpu.icache.total_refs 6645 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -192,12 +192,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.158632 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 128.121989 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67630 # number of cpu cycles simulated +system.cpu.numCycles 59434 # number of cpu cycles simulated system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls -- cgit v1.2.3 From 5d5e001ac3d980f8a0902049db75604f7d7a2ea1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:19:28 -0800 Subject: X86: Update stats now that prefetch is implemented. --- .../00.gzip/ref/x86/linux/simple-atomic/simerr | 8 - .../00.gzip/ref/x86/linux/simple-atomic/simout | 7 +- .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 10 +- .../00.gzip/ref/x86/linux/simple-timing/simerr | 8 - .../00.gzip/ref/x86/linux/simple-timing/simout | 8 +- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 188 ++++++++++----------- 6 files changed, 106 insertions(+), 123 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr index d7d61bab3..94d399eab 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -4,12 +4,4 @@ warn: instruction 'fnstcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 21fdf6d28..875533d57 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -26,7 +26,6 @@ Uncompressed data compared correctly Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data -info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index fd612c556..0158d9e3d 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 977325 # Simulator instruction rate (inst/s) -host_mem_usage 197144 # Number of bytes of host memory used -host_seconds 1656.94 # Real time elapsed on the host -host_tick_rate 581149945 # Simulator tick rate (ticks/s) +host_inst_rate 1045935 # Simulator instruction rate (inst/s) +host_mem_usage 197296 # Number of bytes of host memory used +host_seconds 1548.25 # Real time elapsed on the host +host_tick_rate 621947296 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated sim_seconds 0.962929 # Number of seconds simulated @@ -12,7 +12,7 @@ system.cpu.idle_fraction 0 # Pe system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1925857354 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed -system.cpu.num_refs 607148814 # Number of memory references +system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr index d7d61bab3..94d399eab 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -4,12 +4,4 @@ warn: instruction 'fnstcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 1a67dff68..4f608c9b1 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2009 01:30:29 -M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch -M5 started Feb 24 2009 01:41:46 +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814744167000 because target called exit() +Exiting @ tick 1814896671000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 44628642c..b764de67a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 759916 # Simulator instruction rate (inst/s) -host_mem_usage 204700 # Number of bytes of host memory used -host_seconds 2130.98 # Real time elapsed on the host -host_tick_rate 851601124 # Simulator tick rate (ticks/s) +host_inst_rate 660241 # Simulator instruction rate (inst/s) +host_mem_usage 204740 # Number of bytes of host memory used +host_seconds 2452.69 # Real time elapsed on the host +host_tick_rate 739961389 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 1.814744 # Number of seconds simulated -sim_ticks 1814744167000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses +sim_seconds 1.814897 # Number of seconds simulated +sim_ticks 1814896671000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 20939.027041 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17939.027041 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418844309 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4141928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 197809 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3548501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000472 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 197809 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 187873910 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17480176000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001659 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 312146 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses -system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606718219 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21622104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000840 # miss rate for demand accesses +system.cpu.dcache.demand_misses 509955 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 20092239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000840 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 509955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606642715 # number of overall hits -system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses -system.cpu.dcache.overall_misses 506099 # number of overall misses +system.cpu.dcache.overall_hits 606718219 # number of overall hits +system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses +system.cpu.dcache.overall_misses 509955 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 20092239000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000840 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 509955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439707 # number of replacements -system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 440755 # number of replacements +system.cpu.dcache.sampled_refs 444851 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.900260 # Cycle average of tags in use -system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.900352 # Cycle average of tags in use +system.cpu.dcache.total_refs 606783323 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 308507 # number of writebacks +system.cpu.dcache.writebacks 308934 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,88 +120,88 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 659.165920 # Cycle average of tags in use +system.cpu.icache.tagsinuse 659.162719 # Cycle average of tags in use system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247042 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 12846184000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 247042 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9881680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 247042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 198530 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 165128 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1736904000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.168247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33402 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1336080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33402 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 65104 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3385408000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 65104 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2604160000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.437930 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 445572 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 165128 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14583088000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.629402 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 280444 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11217760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.629402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 280444 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 445572 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 161820 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 282704 # number of overall misses +system.cpu.l2cache.overall_hits 165128 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14583088000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.629402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 280444 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11217760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.629402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 280444 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82097 # number of replacements -system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82238 # number of replacements +system.cpu.l2cache.sampled_refs 97728 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16488.807758 # Cycle average of tags in use -system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16489.299090 # Cycle average of tags in use +system.cpu.l2cache.total_refs 335982 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61702 # number of writebacks +system.cpu.l2cache.writebacks 61724 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3629488334 # number of cpu cycles simulated +system.cpu.numCycles 3629793342 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed -system.cpu.num_refs 607148814 # Number of memory references +system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3 From 5cf060576623f3681b497c46934fb4fe6f8853a6 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 7 Mar 2009 14:30:55 -0800 Subject: tests: update tests because of changes in stat names and in the stats package --- .../long/00.gzip/ref/alpha/tru64/o3-timing/simout | 10 +- .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 +- .../00.gzip/ref/sparc/linux/o3-timing/stats.txt | 64 +++++----- .../ref/alpha/linux/tsunami-o3-dual/simout | 10 +- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 120 +++++++++--------- .../ref/alpha/linux/tsunami-o3/simout | 10 +- .../ref/alpha/linux/tsunami-o3/stats.txt | 64 +++++----- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 10 +- .../30.eon/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../40.perlbmk/ref/alpha/tru64/o3-timing/simout | 10 +- .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../50.vortex/ref/alpha/tru64/o3-timing/simout | 10 +- .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 10 +- .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../long/70.twolf/ref/alpha/tru64/o3-timing/simout | 10 +- .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 64 +++++----- .../00.hello/ref/alpha/linux/o3-timing/simout | 10 +- .../00.hello/ref/alpha/linux/o3-timing/stats.txt | 128 ++++++++++--------- .../00.hello/ref/alpha/tru64/o3-timing/simout | 10 +- .../00.hello/ref/alpha/tru64/o3-timing/stats.txt | 128 ++++++++++--------- .../ref/alpha/linux/o3-timing/simout | 10 +- .../ref/alpha/linux/o3-timing/stats.txt | 136 +++++++++++---------- .../02.insttest/ref/sparc/linux/o3-timing/simout | 10 +- .../ref/sparc/linux/o3-timing/stats.txt | 128 ++++++++++--------- 26 files changed, 663 insertions(+), 619 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index e459fc4f1..0988daaa5 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:27:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:58 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index c5506c5e0..b3f903358 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718859 # Number of BTB hits -global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -global.BPredUnit.lookups 76039018 # Number of BP lookups -global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 244512 # Simulator instruction rate (inst/s) -host_mem_usage 204148 # Number of bytes of host memory used -host_seconds 2312.99 # Real time elapsed on the host -host_tick_rate 72234766 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. +host_inst_rate 309694 # Simulator instruction rate (inst/s) +host_mem_usage 206028 # Number of bytes of host memory used +host_seconds 1826.17 # Real time elapsed on the host +host_tick_rate 91491135 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated sim_ticks 167078146500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92203773 2772.37% - 1 67051353 2016.09% - 2 80133780 2409.45% - 3 36043478 1083.75% - 4 30084945 904.59% - 5 14579095 438.36% - 6 10850493 326.25% - 7 1143008 34.37% - 8 491187 14.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% +system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 16333.162457 # Cy system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 63236 # number of writebacks +system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 334156294 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 4fc3f25f8..b7b45d62c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:45:29 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing +M5 compiled Mar 6 2009 18:29:06 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:38:25 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 1bd86bd33..a8a069318 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 182414509 # Number of BTB hits -global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted -global.BPredUnit.lookups 254458067 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 104414 # Simulator instruction rate (inst/s) -host_mem_usage 206176 # Number of bytes of host memory used -host_seconds 13461.92 # Real time elapsed on the host -host_tick_rate 81909485 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. +host_inst_rate 148318 # Simulator instruction rate (inst/s) +host_mem_usage 208044 # Number of bytes of host memory used +host_seconds 9477.08 # Real time elapsed on the host +host_tick_rate 116350072 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated sim_ticks 1102659164000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 203429504 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254458067 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -291,21 +287,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1083882017 4918.21% - 1 586425796 2660.96% - 2 298714416 1355.44% - 3 164995052 748.68% - 4 47215795 214.25% - 5 14943133 67.81% - 6 6716024 30.47% - 7 790185 3.59% - 8 132701 0.60% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083882017 49.18% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425796 26.61% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714416 13.55% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995052 7.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215795 2.14% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943133 0.68% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716024 0.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790185 0.04% +system.cpu.iq.ISSUE:issued_per_cycle::8 132701 0.01% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued @@ -387,6 +385,10 @@ system.cpu.l2cache.tagsinuse 16402.911294 # Cy system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 141106006 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 2205318329 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 1910760d1..a6115dc06 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:44:44 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +M5 compiled Mar 6 2009 18:15:39 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:43 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dcbc52710..a35446ce7 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,37 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4976196 # Number of BTB hits -global.BPredUnit.BTBHits 2271370 # Number of BTB hits -global.BPredUnit.BTBLookups 9270308 # Number of BTB lookups -global.BPredUnit.BTBLookups 5052293 # Number of BTB lookups -global.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. -global.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect -global.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted -global.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted -global.BPredUnit.lookups 10093436 # Number of BP lookups -global.BPredUnit.lookups 5538388 # Number of BP lookups -global.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. -global.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. -host_inst_rate 133092 # Simulator instruction rate (inst/s) -host_mem_usage 294856 # Number of bytes of host memory used -host_seconds 422.19 # Real time elapsed on the host -host_tick_rate 4518571306 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 2050532 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 906322 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 1832540 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 817104 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. +host_inst_rate 195579 # Simulator instruction rate (inst/s) +host_mem_usage 296668 # Number of bytes of host memory used +host_seconds 287.30 # Real time elapsed on the host +host_tick_rate 6640015618 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56190549 # Number of instructions simulated sim_seconds 1.907705 # Number of seconds simulated sim_ticks 1907705384500 # Number of ticks simulated +system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.BPredUnit.BTBHits 4976196 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9270308 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10093436 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. system.cpu0.commit.COM:branches 5979895 # Number of branches committed system.cpu0.commit.COM:bw_lim_events 670394 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -334,21 +318,23 @@ system.cpu0.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle.samples 70526789 -system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49764698 7056.14% - 1 10507711 1489.89% - 2 4625293 655.82% - 3 2839060 402.55% - 4 1729945 245.29% - 5 663621 94.09% - 6 315226 44.70% - 7 67152 9.52% - 8 14083 2.00% -system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764698 70.56% +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507711 14.90% +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625293 6.56% +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839060 4.03% +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729945 2.45% +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663621 0.94% +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315226 0.45% +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67152 0.10% +system.cpu0.iq.ISSUE:issued_per_cycle::8 14083 0.02% +system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu0.iq.ISSUE:issued_per_cycle::total 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581161 +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133095 system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate system.cpu0.iq.iqInstsAdded 42280485 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 40987446 # Number of instructions issued @@ -449,6 +435,10 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2050532 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1832540 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. system.cpu0.numCycles 100902021 # number of cpu cycles simulated system.cpu0.rename.RENAME:BlockCycles 10627682 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed @@ -468,6 +458,14 @@ system.cpu0.rename.RENAME:serializingInsts 1163461 # system.cpu0.rename.RENAME:skidInsts 8536821 # count of insts added to the skid buffer system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed system.cpu0.timesIdled 904725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.BPredUnit.BTBHits 2271370 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 5052293 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. system.cpu1.commit.COM:branches 2947825 # Number of branches committed system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -770,21 +768,23 @@ system.cpu1.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full.end_dist -system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle.samples 38118977 -system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28405823 7451.88% - 1 4664380 1223.64% - 2 1989669 521.96% - 3 1362790 357.51% - 4 979073 256.85% - 5 465618 122.15% - 6 186895 49.03% - 7 52286 13.72% - 8 12443 3.26% -system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu1.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405823 74.52% +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664380 12.24% +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989669 5.22% +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362790 3.58% +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979073 2.57% +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465618 1.22% +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186895 0.49% +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52286 0.14% +system.cpu1.iq.ISSUE:issued_per_cycle::8 12443 0.03% +system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu1.iq.ISSUE:issued_per_cycle::total 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539453 +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158806 system.cpu1.iq.ISSUE:rate 0.479953 # Inst issue rate system.cpu1.iq.iqInstsAdded 21283894 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 20563386 # Number of instructions issued @@ -864,6 +864,10 @@ system.cpu1.kern.syscall_59 1 0.96% 57.69% # nu system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 906322 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 817104 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. system.cpu1.numCycles 42844582 # number of cpu cycles simulated system.cpu1.rename.RENAME:BlockCycles 3655834 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index c6712a23b..139f5f740 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:42:11 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +M5 compiled Mar 6 2009 18:15:39 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:42 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 37990c73f..4534484ec 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 6937900 # Number of BTB hits -global.BPredUnit.BTBLookups 13339861 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted -global.BPredUnit.lookups 14570242 # Number of BP lookups -global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. -host_inst_rate 209657 # Simulator instruction rate (inst/s) -host_mem_usage 292968 # Number of bytes of host memory used -host_seconds 253.23 # Real time elapsed on the host -host_tick_rate 7374290880 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. +host_inst_rate 203131 # Simulator instruction rate (inst/s) +host_mem_usage 294692 # Number of bytes of host memory used +host_seconds 261.36 # Real time elapsed on the host +host_tick_rate 7144744614 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53090630 # Number of instructions simulated sim_seconds 1.867363 # Number of seconds simulated sim_ticks 1867363148500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 6937900 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 13339861 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14570242 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 8461943 # Number of branches committed system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -322,21 +318,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 102267931 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 73151138 7152.89% - 1 14628619 1430.42% - 2 6419666 627.73% - 3 3934330 384.71% - 4 2528894 247.28% - 5 1032607 100.97% - 6 444582 43.47% - 7 106443 10.41% - 8 21652 2.12% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73151138 71.53% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14628619 14.30% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6419666 6.28% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3934330 3.85% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528894 2.47% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1032607 1.01% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 444582 0.43% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 106443 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::8 21652 0.02% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568461 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.134174 system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued @@ -433,6 +431,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.memDep0.conflictingLoads 3083644 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2877472 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 136996939 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index e8a891c22..d243310c6 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:27:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:25:10 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index cbcabf35c..5e076a275 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38296034 # Number of BTB hits -global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted -global.BPredUnit.lookups 62209737 # Number of BP lookups -global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 183215 # Simulator instruction rate (inst/s) -host_mem_usage 211568 # Number of bytes of host memory used -host_seconds 2049.91 # Real time elapsed on the host -host_tick_rate 65854919 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. +host_inst_rate 243217 # Simulator instruction rate (inst/s) +host_mem_usage 213460 # Number of bytes of host memory used +host_seconds 1544.20 # Real time elapsed on the host +host_tick_rate 87422028 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.134997 # Number of seconds simulated sim_ticks 134996684500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 38296034 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 45834466 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62209737 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99465935 3685.94% - 1 57766030 2140.65% - 2 39984554 1481.72% - 3 29664959 1099.30% - 4 23966120 888.12% - 5 10452563 387.34% - 6 5712016 211.67% - 7 2252970 83.49% - 8 587500 21.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% +system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 3875.343408 # Cy system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 73961217 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54131405 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 269993372 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 8803cb82c..3ec2c9e61 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:27:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:24:11 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 6ff850ff7..655e48f3b 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 240462096 # Number of BTB hits -global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups -global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -global.BPredUnit.lookups 349424731 # Number of BP lookups -global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. -host_inst_rate 217689 # Simulator instruction rate (inst/s) -host_mem_usage 211464 # Number of bytes of host memory used -host_seconds 8374.52 # Real time elapsed on the host -host_tick_rate 84202937 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. +host_inst_rate 233158 # Simulator instruction rate (inst/s) +host_mem_usage 213372 # Number of bytes of host memory used +host_seconds 7818.92 # Real time elapsed on the host +host_tick_rate 90186298 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.705159 # Number of seconds simulated sim_ticks 705159454500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 240462096 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 294213603 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 349424731 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 266706457 # Number of branches committed system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 537278436 3810.05% - 1 285217724 2022.59% - 2 273546804 1939.83% - 3 154810620 1097.82% - 4 63341841 449.18% - 5 51438515 364.77% - 6 32491109 230.41% - 7 9036668 64.08% - 8 3000168 21.28% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% +system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 31919.645552 # Cy system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.memDep0.conflictingLoads 118847053 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21034746 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 1410318910 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 830b96073..3c4f7e5f4 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:29:46 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:23:18 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ea0c05470..c3cb349a5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8039250 # Number of BTB hits -global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted -global.BPredUnit.lookups 16249463 # Number of BP lookups -global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 207814 # Simulator instruction rate (inst/s) -host_mem_usage 214944 # Number of bytes of host memory used -host_seconds 382.99 # Real time elapsed on the host -host_tick_rate 70849023 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. +host_inst_rate 261905 # Simulator instruction rate (inst/s) +host_mem_usage 216920 # Number of bytes of host memory used +host_seconds 303.90 # Real time elapsed on the host +host_tick_rate 89289765 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated sim_ticks 27134794500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17563410 3311.27% - 1 13937999 2627.76% - 2 8266125 1558.43% - 3 4784809 902.09% - 4 4627568 872.45% - 5 2066740 389.65% - 6 1112374 209.72% - 7 454507 85.69% - 8 227738 42.94% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% +system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 18483.925058 # Cy system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 54269590 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 75ae695aa..644c3eb5c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:32:43 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:18:05 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d59f4f0e0..16f472fdf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 312845737 # Number of BTB hits -global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups -global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted -global.BPredUnit.lookups 345502589 # Number of BP lookups -global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. -host_inst_rate 166211 # Simulator instruction rate (inst/s) -host_mem_usage 203924 # Number of bytes of host memory used -host_seconds 10444.84 # Real time elapsed on the host -host_tick_rate 71069469 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. +host_inst_rate 226973 # Simulator instruction rate (inst/s) +host_mem_usage 205820 # Number of bytes of host memory used +host_seconds 7648.67 # Real time elapsed on the host +host_tick_rate 97050740 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated sim_ticks 742309425500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 312845737 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 319575559 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 345502589 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 214632552 # Number of branches committed system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -306,21 +302,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 577695763 3923.77% - 1 271543756 1844.35% - 2 242868170 1649.58% - 3 139713874 948.95% - 4 122021082 828.78% - 5 69652698 473.09% - 6 39670196 269.44% - 7 8017828 54.46% - 8 1116174 7.58% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% +system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued @@ -406,6 +404,10 @@ system.cpu.l2cache.tagsinuse 25902.034914 # Cy system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1195718 # number of writebacks +system.cpu.memDep0.conflictingLoads 127392983 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 67515291 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 1484618852 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index f827bf3c9..4f595ede7 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:37:34 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:16:08 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 485a8a7d7..21c5777d8 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13008791 # Number of BTB hits -global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -global.BPredUnit.lookups 19468548 # Number of BP lookups -global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 179748 # Simulator instruction rate (inst/s) -host_mem_usage 209188 # Number of bytes of host memory used -host_seconds 468.32 # Real time elapsed on the host -host_tick_rate 87159490 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. +host_inst_rate 205423 # Simulator instruction rate (inst/s) +host_mem_usage 211084 # Number of bytes of host memory used +host_seconds 409.79 # Real time elapsed on the host +host_tick_rate 99609545 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040819 # Number of seconds simulated sim_ticks 40818658500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35305774 4330.49% - 1 18904885 2318.81% - 2 11574997 1419.75% - 3 6762756 829.50% - 4 5075415 622.53% - 5 2394533 293.71% - 6 1208963 148.29% - 7 250769 30.76% - 8 50251 6.16% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% +system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 2244.769579 # Cy system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 81637318 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0d9f81ac8..f448ee025 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:22:19 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index b0c4635e4..21437f2a4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 806 # Number of BTB hits -global.BPredUnit.BTBLookups 1937 # Number of BTB lookups -global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -global.BPredUnit.lookups 2263 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 68343 # Simulator instruction rate (inst/s) -host_mem_usage 200684 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 133183507 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +host_inst_rate 83921 # Simulator instruction rate (inst/s) +host_mem_usage 202572 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163392144 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated sim_ticks 12474500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2263 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12416 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 9513 7661.89% - 1 1627 1310.41% - 2 488 393.04% - 3 267 215.05% - 4 153 123.23% - 5 104 83.76% - 6 96 77.32% - 7 53 42.69% - 8 115 92.62% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9513 76.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 115 0.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515706 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.304935 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -147,21 +145,23 @@ system.cpu.fetch.branchRate 0.090701 # Nu system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 13314 -system.cpu.fetch.rateDist.min_value 0 - 0 10844 8144.81% - 1 252 189.27% - 2 238 178.76% - 3 230 172.75% - 4 272 204.30% - 5 162 121.68% - 6 232 174.25% - 7 129 96.89% - 8 955 717.29% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10844 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 252 1.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 238 1.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 230 1.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 272 2.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 162 1.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 232 1.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 129 0.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 955 7.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency @@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 13314 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 9113 6844.67% - 1 1716 1288.87% - 2 1071 804.42% - 3 725 544.54% - 4 355 266.64% - 5 172 129.19% - 6 115 86.38% - 7 34 25.54% - 8 13 9.76% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% +system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 13314 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued @@ -394,6 +396,10 @@ system.cpu.l2cache.tagsinuse 214.901533 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 24950 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index d373e353b..038644e5f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:16:36 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index af633c5e8..14b605eaa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 198 # Number of BTB hits -global.BPredUnit.BTBLookups 684 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 447 # Number of conditional branches predicted -global.BPredUnit.lookups 859 # Number of BP lookups -global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 22600 # Simulator instruction rate (inst/s) -host_mem_usage 199684 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 67889683 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. +host_inst_rate 39458 # Simulator instruction rate (inst/s) +host_mem_usage 201572 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 118256203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated sim_ticks 7183000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 859 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6196 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5239 8455.46% - 1 263 424.47% - 2 334 539.06% - 3 134 216.27% - 4 73 117.82% - 5 63 101.68% - 6 32 51.65% - 7 20 32.28% - 8 38 61.33% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 6196 +system.cpu.commit.COM:committed_per_cycle::min_value 0 +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::0-1 5239 84.55% +system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% +system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% +system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% +system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% +system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% +system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% +system.cpu.commit.COM:committed_per_cycle::8 38 0.61% +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::total 6196 +system.cpu.commit.COM:committed_per_cycle::max_value 8 +system.cpu.commit.COM:committed_per_cycle::mean 0.415752 +system.cpu.commit.COM:committed_per_cycle::stdev 1.208059 system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -147,21 +145,23 @@ system.cpu.fetch.branchRate 0.059790 # Nu system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6528 -system.cpu.fetch.rateDist.min_value 0 - 0 5595 8570.77% - 1 36 55.15% - 2 100 153.19% - 3 69 105.70% - 4 130 199.14% - 5 72 110.29% - 6 45 68.93% - 7 48 73.53% - 8 433 663.30% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5595 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 36 0.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 100 1.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 69 1.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 130 1.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 72 1.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 45 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 48 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 433 6.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency @@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5051 7737.44% - 1 569 871.63% - 2 331 507.05% - 3 253 387.56% - 4 172 263.48% - 5 97 148.59% - 6 39 59.74% - 7 11 16.85% - 8 5 7.66% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 6528 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued @@ -393,6 +395,10 @@ system.cpu.l2cache.tagsinuse 110.762790 # Cy system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 14367 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 73f0d5969..7101807df 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:23:16 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index c9242b886..783867939 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,29 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 916 # Number of BTB hits -global.BPredUnit.BTBLookups 4733 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted -global.BPredUnit.lookups 5548 # Number of BP lookups -global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -host_inst_rate 67823 # Simulator instruction rate (inst/s) -host_mem_usage 201212 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 75589135 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit. +host_inst_rate 106034 # Simulator instruction rate (inst/s) +host_mem_usage 203088 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 118060043 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated sim_ticks 14251500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 2102 # Number of branches committed system.cpu.commit.COM:branches_0 1051 # Number of branches committed system.cpu.commit.COM:branches_1 1051 # Number of branches committed @@ -31,21 +23,23 @@ system.cpu.commit.COM:bw_lim_events 122 # nu system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 22837 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16880 7391.51% - 1 3016 1320.66% - 2 1386 606.91% - 3 576 252.22% - 4 326 142.75% - 5 268 117.35% - 6 170 74.44% - 7 93 40.72% - 8 122 53.42% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 16880 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.560800 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272250 # Number of insts commited each cycle system.cpu.commit.COM:count 12807 # Number of instructions committed system.cpu.commit.COM:count_0 6403 # Number of instructions committed system.cpu.commit.COM:count_1 6404 # Number of instructions committed @@ -239,21 +233,23 @@ system.cpu.fetch.branchRate 0.194639 # Nu system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 22904 -system.cpu.fetch.rateDist.min_value 0 - 0 17622 7693.85% - 1 416 181.63% - 2 353 154.12% - 3 477 208.26% - 4 425 185.56% - 5 349 152.38% - 6 442 192.98% - 7 261 113.95% - 8 2559 1117.27% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 17622 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 416 1.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 353 1.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 477 2.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 425 1.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 349 1.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 442 1.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 261 1.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2559 11.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency @@ -530,21 +526,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 22904 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 14156 6180.58% - 1 3289 1435.99% - 2 2351 1026.46% - 3 1373 599.46% - 4 854 372.86% - 5 535 233.58% - 6 261 113.95% - 7 57 24.89% - 8 28 12.22% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% +system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 22904 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued @@ -702,6 +700,14 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 28504 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index d0efe85b3..f1994d462 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:17:34 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing +M5 compiled Mar 6 2009 18:29:06 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:30:50 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 0584aa2e2..67e62423e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4398 # Number of BTB hits -global.BPredUnit.BTBLookups 9844 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted -global.BPredUnit.lookups 11413 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 30716 # Simulator instruction rate (inst/s) -host_mem_usage 201632 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host -host_tick_rate 58973694 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit. +host_inst_rate 66771 # Simulator instruction rate (inst/s) +host_mem_usage 203496 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 128111456 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated sim_ticks 27756500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 4398 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 9844 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11413 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11413 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 42766 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 34594 8089.14% - 1 4804 1123.32% - 2 1741 407.10% - 3 720 168.36% - 4 413 96.57% - 5 144 33.67% - 6 196 45.83% - 7 51 11.93% - 8 103 24.08% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 34594 80.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 4804 11.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1741 4.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 720 1.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 413 0.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 144 0.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 196 0.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 51 0.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 103 0.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.354838 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.957636 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -134,21 +132,23 @@ system.cpu.fetch.branchRate 0.205588 # Nu system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 47090 -system.cpu.fetch.rateDist.min_value 0 - 0 30448 6465.92% - 1 7532 1599.49% - 2 1217 258.44% - 3 1059 224.89% - 4 1060 225.10% - 5 1193 253.34% - 6 711 150.99% - 7 327 69.44% - 8 3543 752.39% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 30448 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 7532 15.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1217 2.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1059 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 1060 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1193 2.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 711 1.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 327 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3543 7.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.236929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.372442 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency @@ -283,21 +283,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 47090 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 34112 7244.00% - 1 5516 1171.37% - 2 3070 651.94% - 3 2146 455.72% - 4 997 211.72% - 5 653 138.67% - 6 342 72.63% - 7 211 44.81% - 8 43 9.13% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% +system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 47090 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued @@ -377,6 +379,10 @@ system.cpu.l2cache.tagsinuse 251.642612 # Cy system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 3415 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 55514 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -- cgit v1.2.3 From 4f1855484c1fe148d66b2dbc2dc0d7964b578c5c Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 7 Mar 2009 16:58:51 -0800 Subject: Fix up regression execution to better handle tests that end abnormally. E.g., mark aborts due to assertion failures as failed tests, but those that get killed by the user as needing to be rerun, etc. --- tests/SConscript | 142 +++++++++++++++++++++++++++++++++++-------------------- tests/run.py | 2 +- 2 files changed, 92 insertions(+), 52 deletions(-) (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 016b3a26a..5c4a61e18 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -29,7 +29,7 @@ # Authors: Steve Reinhardt # Kevin Lim -import os +import os, signal import sys import glob from SCons.Script.SConscript import SConsEnvironment @@ -44,57 +44,113 @@ env.Tests = {} def contents(node): return file(str(node)).read() -def check_test(target, source, env): +# functions to parse return value from scons Execute()... not the same +# as wait() etc., so python built-in os funcs don't work. +def signaled(status): + return (status & 0x80) != 0; + +def signum(status): + return (status & 0x7f); + +# List of signals that indicate that we should retry the test rather +# than consider it failed. +retry_signals = (signal.SIGTERM, signal.SIGKILL, signal.SIGINT, + signal.SIGQUIT, signal.SIGHUP) + +# regular expressions of lines to ignore when diffing outputs +output_ignore_regexes = ( + '^command line:', # for stdout file + '^M5 compiled ', # for stderr file + '^M5 started ', # for stderr file + '^M5 executing on ', # for stderr file + '^Simulation complete at', # for stderr file + '^Listening for', # for stderr file + 'listening for remote gdb', # for stderr file + ) + +output_ignore_args = ' '.join(["-I '"+s+"'" for s in output_ignore_regexes]) + +output_ignore_args += ' --exclude=stats.txt --exclude=outdiff' + +def run_test(target, source, env): """Check output from running test. Targets are as follows: - target[0] : outdiff - target[1] : statsdiff - target[2] : status + target[0] : status + + Sources are: + source[0] : M5 binary + source[1] : tests/run.py script + source[2] : reference stats file """ # make sure target files are all gone for t in target: if os.path.exists(t.abspath): Execute(Delete(t.abspath)) - # Run diff on output & ref directories to find differences. - # Exclude the stats file since we will use diff-out on that. - Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + - '-I "^command line:" ' + # for stdout file - '-I "^M5 compiled " ' + # for stderr file - '-I "^M5 started " ' + # for stderr file - '-I "^M5 executing on " ' + # for stderr file - '-I "^Simulation complete at" ' + # for stderr file - '-I "^Listening for" ' + # for stderr file - '-I "listening for remote gdb" ' + # for stderr file - '--exclude=stats.txt --exclude=SCCS ' + - '--exclude=${TARGETS[0].file} ' + - '> ${TARGETS[0]}', target=target, source=source), None) - print "===== Output differences =====" - print contents(target[0]) - # Run diff-out on stats.txt file - status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}', - target=target, source=source), - strfunction=None) - print "===== Statistics differences =====" - print contents(target[1]) - # Generate status file contents based on exit status of diff-out + + tgt_dir = os.path.dirname(str(target[0])) + + # Base command for running test. We mess around with indirectly + # referring to files via SOURCES and TARGETS so that scons can mess + # with paths all it wants to and we still get the right files. + cmd = '${SOURCES[0]} -d %s -re ${SOURCES[1]} %s' % (tgt_dir, tgt_dir) + + # Prefix test run with batch job submission command if appropriate. + # Batch command also supports timeout arg (in seconds, not minutes). + timeout = 15 * 60 # used to be a param, probably should be again + if env['BATCH']: + cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) + + status = Execute(env.subst(cmd, target=target, source=source)) + if status == 0: + # M5 terminated normally. + # Run diff on output & ref directories to find differences. + # Exclude the stats file since we will use diff-out on that. + outdiff = os.path.join(tgt_dir, 'outdiff') + diffcmd = 'diff -ubr %s ${SOURCES[2].dir} %s > %s' \ + % (output_ignore_args, tgt_dir, outdiff) + Execute(env.subst(diffcmd, target=target, source=source)) + print "===== Output differences =====" + print contents(outdiff) + # Run diff-out on stats.txt file + statsdiff = os.path.join(tgt_dir, 'statsdiff') + diffcmd = '$DIFFOUT ${SOURCES[2]} %s > %s' \ + % (os.path.join(tgt_dir, 'stats.txt'), statsdiff) + diffcmd = env.subst(diffcmd, target=target, source=source) + status = Execute(diffcmd, strfunction=None) + print "===== Statistics differences =====" + print contents(statsdiff) + + else: # m5 exit status != 0 + # M5 did not terminate properly, so no need to check the output + if signaled(status) and signum(status) in retry_signals: + # Consider the test incomplete; don't create a 'status' output. + # Hand the return status to scons and let scons decide what + # to do about it (typically terminate unless run with -k). + print 'M5 terminated with signal', signum(status) + return status + # complete but failed execution (call to exit() with non-zero + # status, SIGABORT due to assertion failure, etc.)... fall through + # and generate FAILED status as if output comparison had failed + print 'M5 exited with non-zero status', status + + # Generate status file contents based on exit status of m5 or diff-out if status == 0: status_str = "passed." else: status_str = "FAILED!" - f = file(str(target[2]), 'w') - print >>f, env.subst('${TARGETS[2].dir}', target=target, source=source), \ - status_str + f = file(str(target[0]), 'w') + print >>f, tgt_dir, status_str f.close() # done return 0 -def check_test_string(target, source, env): - return env.subst("Comparing outputs in ${TARGETS[0].dir}.", +def run_test_string(target, source, env): + return env.subst("Running test in ${TARGETS[0].dir}.", target=target, source=source) -testAction = env.Action(check_test, check_test_string) +testAction = env.Action(run_test, run_test_string) def print_test(target, source, env): print '***** ' + contents(source[0]) @@ -174,24 +230,8 @@ def test_builder(env, ref_dir): new_stats = tgt('stats.txt') status_file = tgt('status') - # Base command for running test. We mess around with indirectly - # referring to files via SOURCES and TARGETS so that scons can - # mess with paths all it wants to and we still get the right - # files. - cmd = '${SOURCES[0]} -d $TARGET.dir -re ${SOURCES[1]} %s' % tgt_dir - - # Prefix test run with batch job submission command if appropriate. - # Batch command also supports timeout arg (in seconds, not minutes). - timeout = 15 * 60 # used to be a param, probably should be again - if env['BATCH']: - cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) - - env.Command([tgt('simout'), tgt('simerr'), new_stats], - [env.M5Binary, 'run.py'], cmd) - - # order of targets is important... see check_test - env.Command([tgt('outdiff'), tgt('statsdiff'), status_file], - [ref_stats, new_stats], + env.Command([status_file], + [env.M5Binary, 'run.py', ref_stats], testAction) # phony target to echo status diff --git a/tests/run.py b/tests/run.py index aadc16b93..df26c88c5 100644 --- a/tests/run.py +++ b/tests/run.py @@ -34,7 +34,7 @@ import m5 m5.disableAllListeners() # single "path" arg encodes everything we need to know about test -(category, name, isa, opsys, config) = sys.argv[1].split('/') +(category, name, isa, opsys, config) = sys.argv[1].split('/')[-5:] # find path to directory containing this file tests_root = os.path.dirname(__file__) -- cgit v1.2.3 From 4c902714f7c41d6e31cdf7c41642c22cb5fa9fcd Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 7 Mar 2009 17:24:13 -0800 Subject: Minor tweak to regression exit status message. --- tests/SConscript | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 5c4a61e18..2d5bd5da0 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -124,16 +124,18 @@ def run_test(target, source, env): else: # m5 exit status != 0 # M5 did not terminate properly, so no need to check the output - if signaled(status) and signum(status) in retry_signals: - # Consider the test incomplete; don't create a 'status' output. - # Hand the return status to scons and let scons decide what - # to do about it (typically terminate unless run with -k). + if signaled(status): print 'M5 terminated with signal', signum(status) - return status + if signum(status) in retry_signals: + # Consider the test incomplete; don't create a 'status' output. + # Hand the return status to scons and let scons decide what + # to do about it (typically terminate unless run with -k). + return status + else: + print 'M5 exited with non-zero status', status # complete but failed execution (call to exit() with non-zero # status, SIGABORT due to assertion failure, etc.)... fall through # and generate FAILED status as if output comparison had failed - print 'M5 exited with non-zero status', status # Generate status file contents based on exit status of m5 or diff-out if status == 0: -- cgit v1.2.3 From 17cb191c981ddb5a40f40a14a44e7b7ee7576c0d Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 11 Mar 2009 10:54:42 -0700 Subject: tests: use env.Execute instead of Execute to pick up env vars. --- tests/SConscript | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/SConscript b/tests/SConscript index 2d5bd5da0..38e9ae9d2 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -87,7 +87,7 @@ def run_test(target, source, env): # make sure target files are all gone for t in target: if os.path.exists(t.abspath): - Execute(Delete(t.abspath)) + env.Execute(Delete(t.abspath)) tgt_dir = os.path.dirname(str(target[0])) @@ -102,7 +102,7 @@ def run_test(target, source, env): if env['BATCH']: cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) - status = Execute(env.subst(cmd, target=target, source=source)) + status = env.Execute(env.subst(cmd, target=target, source=source)) if status == 0: # M5 terminated normally. # Run diff on output & ref directories to find differences. @@ -110,7 +110,7 @@ def run_test(target, source, env): outdiff = os.path.join(tgt_dir, 'outdiff') diffcmd = 'diff -ubr %s ${SOURCES[2].dir} %s > %s' \ % (output_ignore_args, tgt_dir, outdiff) - Execute(env.subst(diffcmd, target=target, source=source)) + env.Execute(env.subst(diffcmd, target=target, source=source)) print "===== Output differences =====" print contents(outdiff) # Run diff-out on stats.txt file @@ -118,7 +118,7 @@ def run_test(target, source, env): diffcmd = '$DIFFOUT ${SOURCES[2]} %s > %s' \ % (os.path.join(tgt_dir, 'stats.txt'), statsdiff) diffcmd = env.subst(diffcmd, target=target, source=source) - status = Execute(diffcmd, strfunction=None) + status = env.Execute(diffcmd, strfunction=None) print "===== Statistics differences =====" print contents(statsdiff) @@ -205,7 +205,7 @@ def update_test(target, source, env): print " Creating new file", f copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f)) copyAction.strfunction = None - Execute(copyAction) + env.Execute(copyAction) return 0 def update_test_string(target, source, env): -- cgit v1.2.3 From 15f0e44060ffcf1ab6648469678cefa9081a68a1 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 16 Mar 2009 11:01:23 -0400 Subject: Very minor regression stats updates due top previous changeset. Setting dirty bit on swaps added a handful of writebacks in a few of the longer-running SPARC_SE benchmarks. --- .../long/00.gzip/ref/sparc/linux/o3-timing/simout | 12 +- .../00.gzip/ref/sparc/linux/o3-timing/stats.txt | 350 ++++++++++----------- .../00.gzip/ref/sparc/linux/simple-timing/simout | 12 +- .../ref/sparc/linux/simple-timing/stats.txt | 96 +++--- .../10.mcf/ref/sparc/linux/simple-timing/simout | 10 +- .../10.mcf/ref/sparc/linux/simple-timing/stats.txt | 16 +- .../50.vortex/ref/sparc/linux/simple-timing/simout | 10 +- .../ref/sparc/linux/simple-timing/stats.txt | 26 +- 8 files changed, 266 insertions(+), 266 deletions(-) (limited to 'tests') diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index b7b45d62c..293987f44 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 6 2009 18:29:06 -M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip -M5 started Mar 6 2009 18:38:25 -M5 executing on maize -command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1102659164000 because target called exit() +Exiting @ tick 1102659088000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index a8a069318..3e5a615cf 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,36 +1,36 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 148318 # Simulator instruction rate (inst/s) -host_mem_usage 208044 # Number of bytes of host memory used -host_seconds 9477.08 # Real time elapsed on the host -host_tick_rate 116350072 # Simulator tick rate (ticks/s) +host_inst_rate 159348 # Simulator instruction rate (inst/s) +host_mem_usage 206344 # Number of bytes of host memory used +host_seconds 8821.04 # Real time elapsed on the host +host_tick_rate 125003315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated -sim_ticks 1102659164000 # Number of ticks simulated +sim_ticks 1102659088000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 203429504 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 203429498 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 254458067 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 254458061 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254458061 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1964055138 +system.cpu.commit.COM:committed_per_cycle.samples 1964055004 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1088074348 5539.94% - 1 575643775 2930.89% - 2 120435536 613.20% - 3 120975808 615.95% - 4 27955061 142.33% - 5 8084154 41.16% + 0 1088074201 5539.94% + 1 575643784 2930.89% + 2 120435541 613.20% + 3 120975798 615.95% + 4 27955067 142.33% + 5 8084166 41.16% 6 10447088 53.19% - 7 4343249 22.11% - 8 8096119 41.22% + 7 4343250 22.11% + 8 8096109 41.22% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -42,20 +42,20 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1390237652 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405618365 # Number of Instructions Simulated system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346235 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092355500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 915699 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667386 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) @@ -69,48 +69,48 @@ system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 83930150000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency -system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980331 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022505500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 3138233 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2538011 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382118500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 589980362 # number of overall hits -system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles +system.cpu.dcache.overall_hits 589980331 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3138202 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 3138233 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2538011 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382118500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -119,44 +119,44 @@ system.cpu.dcache.replacements 523278 # nu system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use -system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 590215067 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 348745 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched -system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed +system.cpu.dcache.writebacks 348749 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443317 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538799 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668513 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001789 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759977 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941385 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458061 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588619 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2203815119 +system.cpu.fetch.rateDist.samples 2203814981 system.cpu.fetch.rateDist.min_value 0 - 0 1359103013 6167.05% - 1 256500552 1163.89% + 0 1359102894 6167.05% + 1 256500547 1163.89% 2 81150170 368.23% 3 38425919 174.36% - 4 85384466 387.44% - 5 41200028 186.95% + 4 85384463 387.44% + 5 41200023 186.95% 6 32567288 147.78% 7 20688755 93.88% - 8 288794928 1310.43% + 8 288794922 1310.43% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 354586492 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses @@ -166,16 +166,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits +system.cpu.icache.demand_hits 354586492 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses @@ -186,11 +186,11 @@ system.cpu.icache.demand_mshr_misses 1379 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354586500 # number of overall hits +system.cpu.icache.overall_hits 354586492 # number of overall hits system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses system.cpu.icache.overall_misses 2127 # number of overall misses @@ -203,40 +203,40 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 222 # number of replacements system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use -system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1057.993144 # Cycle average of tags in use +system.cpu.icache.total_refs 354586492 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1503196 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 128154505 # Number of branches executed system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed system.cpu.iew.EXEC:stores 207432555 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value -system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1490113215 # num instructions consuming a value +system.cpu.iew.WB:count 1862924801 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1435567316 # num instructions producing a value +system.cpu.iew.WB:producers 1435567297 # num instructions producing a value system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle -system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking +system.cpu.iew.WB:sent 1872447487 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100855 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispNonSpecInsts 21390967 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059392 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399339 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831174 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions +system.cpu.iew.iewExecSquashedInsts 94512444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795217 # Number of executed instructions system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9892 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75722 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores @@ -246,19 +246,19 @@ system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Nu system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541383 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 1989307661 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186637130 59.65% # Type of FU issued + IntAlu 1186637129 59.65% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2990817 0.15% # Type of FU issued + FloatAdd 2990803 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued @@ -269,68 +269,68 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 142220 3.54% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 232758 5.80% # attempts to use FU when none available + FloatAdd 232755 5.80% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3328923 82.92% # attempts to use FU when none available - MemWrite 310728 7.74% # attempts to use FU when none available + MemRead 3328922 82.92% # attempts to use FU when none available + MemWrite 310730 7.74% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083882017 49.18% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425796 26.61% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714416 13.55% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995052 7.49% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215795 2.14% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943133 0.68% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716024 0.30% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 790185 0.04% -system.cpu.iq.ISSUE:issued_per_cycle::8 132701 0.01% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% +system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate -system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315429 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646014 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439374 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054156 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.562838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.514866 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.857257 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384760 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214678 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194217500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140229 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35014 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085517500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140229 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35014 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency @@ -340,75 +340,75 @@ system.cpu.l2cache.UpgradeReq_misses 72896 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214678 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314075 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9781481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593992 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314075 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 214675 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 314078 # number of overall misses +system.cpu.l2cache.overall_hits 214678 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314075 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9781481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593992 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84497 # number of replacements -system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84499 # number of replacements +system.cpu.l2cache.sampled_refs 99950 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16402.920353 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.l2cache.writebacks 61948 # number of writebacks system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 141106006 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 141106002 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2205318329 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking +system.cpu.memDep0.insertedStores 301399339 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2205318177 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694861 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 27117 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425901 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298995 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed -system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 4917191691 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611594 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068259 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791884 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759977 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521130 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984761 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775082 # count of temporary serializing insts renamed +system.cpu.timesIdled 43184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 12ee4624b..d75186ab5 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2009 01:30:29 -M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch -M5 started Feb 24 2009 01:30:33 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2076000961000 because target called exit() +Exiting @ tick 2076000877000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 9a15c39dd..8851d2d2a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 779483 # Simulator instruction rate (inst/s) -host_mem_usage 204800 # Number of bytes of host memory used -host_seconds 1910.91 # Real time elapsed on the host -host_tick_rate 1086392421 # Simulator tick rate (ticks/s) +host_inst_rate 1328193 # Simulator instruction rate (inst/s) +host_mem_usage 205396 # Number of bytes of host memory used +host_seconds 1121.47 # Real time elapsed on the host +host_tick_rate 1851148785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated -sim_ticks 2076000961000 # Number of ticks simulated +sim_ticks 2076000877000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568846579 # number of overall hits -system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -80,7 +80,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316420 # number of writebacks +system.cpu.dcache.writebacks 316424 # number of writebacks system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency @@ -130,7 +130,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.413769 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -147,13 +147,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 259735 # nu system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -163,11 +163,11 @@ system.cpu.l2cache.UpgradeReq_misses 59900 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -176,14 +176,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -191,25 +191,25 @@ system.cpu.l2cache.overall_accesses 454328 # nu system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160847 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293481 # number of overall misses +system.cpu.l2cache.overall_hits 160849 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293479 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82905 # number of replacements -system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82908 # number of replacements +system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16358.028924 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61861 # number of writebacks +system.cpu.l2cache.writebacks 61864 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4152001922 # number of cpu cycles simulated +system.cpu.numCycles 4152001754 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 3aaf04828..b171def01 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2009 01:30:29 -M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch -M5 started Feb 24 2009 01:31:11 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 61025e455..1e841feab 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 712663 # Simulator instruction rate (inst/s) -host_mem_usage 336988 # Number of bytes of host memory used -host_seconds 342.15 # Real time elapsed on the host -host_tick_rate 1070988197 # Simulator tick rate (ticks/s) +host_inst_rate 1212571 # Simulator instruction rate (inst/s) +host_mem_usage 337588 # Number of bytes of host memory used +host_seconds 201.09 # Real time elapsed on the host +host_tick_rate 1822248337 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.366435 # Number of seconds simulated @@ -80,7 +80,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 94875 # number of writebacks +system.cpu.dcache.writebacks 94877 # number of writebacks system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency @@ -163,8 +163,8 @@ system.cpu.l2cache.UpgradeReq_misses 48257 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. @@ -204,7 +204,7 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index d6b904f84..397f2cd80 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2009 01:30:29 -M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch -M5 started Feb 24 2009 01:30:32 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py long/50.vortex/sparc/linux/simple-timing +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3d50b13ca..24dff0498 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 683746 # Simulator instruction rate (inst/s) -host_mem_usage 213692 # Number of bytes of host memory used -host_seconds 199.11 # Real time elapsed on the host -host_tick_rate 1021439068 # Simulator tick rate (ticks/s) +host_inst_rate 1347607 # Simulator instruction rate (inst/s) +host_mem_usage 214288 # Number of bytes of host memory used +host_seconds 101.02 # Real time elapsed on the host +host_tick_rate 2013168641 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.203377 # Number of seconds simulated @@ -80,7 +80,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107271 # number of writebacks +system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency @@ -163,11 +163,11 @@ system.cpu.l2cache.UpgradeReq_misses 4266 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107279 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.433874 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -201,13 +201,13 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # m system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 120486 # number of replacements -system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 120487 # number of replacements +system.cpu.l2cache.sampled_refs 139197 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19319.557750 # Cycle average of tags in use -system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 19319.562378 # Cycle average of tags in use +system.cpu.l2cache.total_refs 199591 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 87413 # number of writebacks +system.cpu.l2cache.writebacks 87414 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 406753384 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed -- cgit v1.2.3