From f85286b3debf4a4a94d3b959e5bb880be81bd692 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:08 -0600 Subject: MEM: Add port proxies instead of non-structural ports Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh --- tests/configs/inorder-timing.py | 1 + tests/configs/memtest-ruby.py | 4 ++++ tests/configs/memtest.py | 2 ++ tests/configs/o3-timing-mp.py | 2 ++ tests/configs/o3-timing.py | 1 + tests/configs/rubytest-ruby.py | 3 +++ tests/configs/simple-atomic-mp.py | 2 ++ tests/configs/simple-atomic.py | 1 + tests/configs/simple-timing-mp-ruby.py | 3 +++ tests/configs/simple-timing-mp.py | 2 ++ tests/configs/simple-timing-ruby.py | 3 +++ tests/configs/simple-timing.py | 1 + 12 files changed, 25 insertions(+) (limited to 'tests') diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index ddf37b5ec..1bab83609 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -50,6 +50,7 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 49f152017..2517e7670 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -109,6 +109,10 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.access_phys_mem = False + +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f62381473..66e49a63e 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -76,6 +76,8 @@ for cpu in cpus: cpu.l1c.mem_side = system.toL2Bus.port system.funcmem.port = cpu.functional +system.system_port = system.membus.port + # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 9f7c89c7b..67aaebd21 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -79,6 +79,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# connect system port to membus +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index fec21c177..395fd24a3 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -50,6 +50,7 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index b63833ccf..a7e598b0a 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -105,6 +105,9 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.access_phys_mem = False +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index 4db741b8a..e722ef334 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -78,6 +78,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# connect system port to membus +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index 4a2efcc57..191230164 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -32,6 +32,7 @@ from m5.objects import * system = System(cpu = AtomicSimpleCPU(cpu_id=0), physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port system.cpu.connectAllPorts(system.membus) system.cpu.clock = '2GHz' diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index d57ccea15..58ca862e1 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -88,6 +88,9 @@ for (i, cpu) in enumerate(system.cpu): cpu.icache_port = system.ruby._cpu_ruby_ports[i].port cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 6f4090ec2..f1ebb1939 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -75,6 +75,8 @@ for cpu in cpus: cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' +system.system_port = system.membus.port + # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 1d67f6f97..359421a49 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,6 +85,9 @@ assert(len(system.ruby._cpu_ruby_ports) == 1) cpu.icache_port = system.ruby._cpu_ruby_ports[0].port cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index bc9d016c5..cc0d1d207 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -46,6 +46,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) cpu.clock = '2GHz' -- cgit v1.2.3