From 4a3f11149d791284a012af71067f6b2199aa165c Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Tue, 29 Apr 2014 16:05:02 -0500 Subject: arm: use condition code registers for ARM ISA Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file. --- util/cpt_upgrader.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'util/cpt_upgrader.py') diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py index df3604754..66c671025 100755 --- a/util/cpt_upgrader.py +++ b/util/cpt_upgrader.py @@ -574,6 +574,33 @@ def from_A(cpt): def from_B(cpt): cpt.set('Globals', 'numMainEventQueues', '1') +# Checkpoint version D uses condition code registers for the ARM +# architecture; previously the integer register file was used for these +# registers. To upgrade, we move those 5 integer registers to the ccRegs +# register file. +def from_C(cpt): + if cpt.get('root','isa') == 'arm': + for sec in cpt.sections(): + import re + + re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) + # Search for all the execution contexts + if not re_cpu_match: + continue + + items = [] + for (item,value) in cpt.items(sec): + items.append(item) + if 'ccRegs' not in items: + intRegs = cpt.get(sec, 'intRegs').split() + + ccRegs = intRegs[38:43] + del intRegs[38:43] + + ccRegs.append('0') # CCREG_ZERO + + cpt.set(sec, 'intRegs', ' '.join(intRegs)) + cpt.set(sec, 'ccRegs', ' '.join(ccRegs)) migrations = [] migrations.append(from_0) @@ -588,6 +615,7 @@ migrations.append(from_8) migrations.append(from_9) migrations.append(from_A) migrations.append(from_B) +migrations.append(from_C) verbose_print = False -- cgit v1.2.3