From 55f5c4dd8a10d14a24208110df891b8b2bbf56e4 Mon Sep 17 00:00:00 2001 From: Christian Menard Date: Thu, 9 Feb 2017 19:15:33 -0500 Subject: misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10] The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add the Master Port. Add an example application that isslustrates its * use. Testing Done: A simple example application consisting of a TLM traffic generator and a gem5 memory is part of the patch. Reviewed at http://reviews.gem5.org/r/3528/ Signed-off-by: Jason Lowe-Power --- util/tlm/sim_control.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'util/tlm/sim_control.cc') diff --git a/util/tlm/sim_control.cc b/util/tlm/sim_control.cc index ef04c6bbd..2423f1fb6 100644 --- a/util/tlm/sim_control.cc +++ b/util/tlm/sim_control.cc @@ -46,6 +46,7 @@ #include #include +#include "sc_master_port.hh" #include "sc_slave_port.hh" #include "sim/cxx_config_ini.hh" #include "sim/init_signals.hh" @@ -90,6 +91,7 @@ SimControl::SimControl(sc_core::sc_module_name name, int argc_, char** argv_) cxxConfigInit(); Gem5SystemC::SCSlavePort::registerPortHandler(); + Gem5SystemC::SCMasterPort::registerPortHandler(*this); Trace::setDebugLogger(&logger); -- cgit v1.2.3