From 2f14baaabca315e078597e3441bf8cf3dc703264 Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Tue, 31 Jan 2017 17:11:24 +0000 Subject: arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg Reviewed-by: Weiping Liao --- util/cpt_upgraders/arm-gicv2-banked-regs.py | 2 -- 1 file changed, 2 deletions(-) (limited to 'util') diff --git a/util/cpt_upgraders/arm-gicv2-banked-regs.py b/util/cpt_upgraders/arm-gicv2-banked-regs.py index 4cdb9e3f4..5c23383b0 100644 --- a/util/cpt_upgraders/arm-gicv2-banked-regs.py +++ b/util/cpt_upgraders/arm-gicv2-banked-regs.py @@ -52,7 +52,6 @@ def upgrader(cpt): b_intEnabled = intEnabled[0] b_pendingInt = pendingInt[0] b_activeInt = activeInt[0] - b_cpuTarget = cpuTarget[0:32] del intEnabled[0] del pendingInt[0] @@ -78,4 +77,3 @@ def upgrader(cpt): cpt.set(new_sec, 'pendingInt', b_pendingInt) cpt.set(new_sec, 'activeInt', b_activeInt) cpt.set(new_sec, 'intPriority',' '.join(intPriority)) - cpt.set(new_sec, 'cpuTarget', ' '.join(b_cpuTarget)) -- cgit v1.2.3