# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert

Import('*')

need_simple_base = False
if 'AtomicSimpleCPU' in env['CPU_MODELS']:
    need_simple_base = True
    SimObject('AtomicSimpleCPU.py')
    Source('atomic.cc')

    # The NonCachingSimpleCPU is really an atomic CPU in
    # disguise. It's therefore always enabled when the atomic CPU is
    # enabled.
    SimObject('NonCachingSimpleCPU.py')
    Source('noncaching.cc')

if 'TimingSimpleCPU' in env['CPU_MODELS']:
    need_simple_base = True
    SimObject('TimingSimpleCPU.py')
    Source('timing.cc')

if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
       'TimingSimpleCPU' in env['CPU_MODELS']:
    DebugFlag('SimpleCPU')

if need_simple_base:
    Source('base.cc')
    SimObject('BaseSimpleCPU.py')