# Copyright (c) 2008 The Regents of The University of Michigan
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# Authors: Gabe Black

from m5.params import *
from m5.proxy import *

from Device import IsaFake
from Pci import PciConfigAll
from Platform import Platform
from SouthBridge import SouthBridge
from Terminal import Terminal
from Uart import Uart8250

def x86IOAddress(port):
    IO_address_space_base = 0x8000000000000000
    return IO_address_space_base + port;

class PC(Platform):
    type = 'PC'
    system = Param.System(Parent.any, "system")

    pciconfig = PciConfigAll()

    south_bridge = SouthBridge()

    # "Non-existant" port used for timing purposes by the linux kernel
    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)

    # Ports behind the pci config and data regsiters. These don't do anything,
    # but the linux kernel fiddles with them anway.
    behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)

    # Serial port and terminal
    terminal = Terminal()
    com_1 = Uart8250()
    com_1.pio_addr = x86IOAddress(0x3f8)
    com_1.terminal = terminal

    def attachIO(self, bus):
        self.south_bridge.pio = bus.port
        self.i_dont_exist.pio = bus.port
        self.behind_pci.pio = bus.port
        self.com_1.pio = bus.port
        self.pciconfig.pio = bus.default
        bus.responder_set = True
        bus.responder = self.pciconfig