# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt

import m5
from m5.objects import *

import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)

cpu = DerivO3CPU(cpu_id=0)

system = System(cpu = cpu,
                physmem = ruby_memory,
                membus = SystemXBar(),
                mem_mode = "timing",
                clk_domain = SrcClockDomain(clock = '1GHz'))

# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')

system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)

# Connect the system port for loading of binaries etc
system.system_port = system.membus.slave

root = Root(full_system = False, system = system)