---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 183168209 # Number of BTB hits global.BPredUnit.BTBLookups 207693172 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 83686538 # Number of conditional branches incorrect global.BPredUnit.condPredicted 256168234 # Number of conditional branches predicted global.BPredUnit.lookups 256168234 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. host_inst_rate 108517 # Simulator instruction rate (inst/s) host_mem_usage 202532 # Number of bytes of host memory used host_seconds 13726.13 # Real time elapsed on the host host_tick_rate 80131991 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 457134527 # Number of conflicting loads. memdepunit.memDep.conflictingStores 154100032 # Number of conflicting stores. memdepunit.memDep.insertedLoads 745124340 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 301027499 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated sim_seconds 1.099902 # Number of seconds simulated sim_ticks 1099901861500 # Number of ticks simulated system.cpu.commit.COM:branches 86246390 # Number of branches committed system.cpu.commit.COM:bw_lim_events 9028629 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 1956850179 system.cpu.commit.COM:committed_per_cycle.min_value 0 0 1082285235 5530.75% 1 575067444 2938.74% 2 119112331 608.69% 3 121687931 621.86% 4 26918285 137.56% 5 9398970 48.03% 6 9197638 47.00% 7 4153716 21.23% 8 9028629 46.14% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 1489514761 # Number of instructions committed system.cpu.commit.COM:loads 402511688 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569359656 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 83686538 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489514761 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 1386494932 # The number of squashed insts skipped by commit system.cpu.committedInsts 1489514761 # Number of Instructions Simulated system.cpu.committedInsts_total 1489514761 # Number of Instructions Simulated system.cpu.cpi 1.476859 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.476859 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 432423106 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21577.217813 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4456.675710 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 432175035 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 5352682000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 248071 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 707847 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1105572000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000574 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 248071 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 7012.500000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5012.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits system.cpu.dcache.SwapReq_miss_latency 280500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses system.cpu.dcache.SwapReq_mshr_miss_latency 200500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 165036365 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 45516.173877 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5913.886312 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 164687129 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 15895886500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002116 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 349236 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1810277 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 2065342000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002116 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 349236 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1139.085750 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 597459471 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 35573.948573 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency system.cpu.dcache.demand_hits 596862164 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 21248568500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.001000 # miss rate for demand accesses system.cpu.dcache.demand_misses 597307 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2518124 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3170914000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001000 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 597307 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 597459471 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35573.948573 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596862164 # number of overall hits system.cpu.dcache.overall_miss_latency 21248568500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.001000 # miss rate for overall accesses system.cpu.dcache.overall_misses 597307 # number of overall misses system.cpu.dcache.overall_mshr_hits 2518124 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3170914000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001000 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 597307 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 519953 # number of replacements system.cpu.dcache.sampled_refs 524049 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.788106 # Cycle average of tags in use system.cpu.dcache.total_refs 596936748 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 72857000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 346070 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 407153301 # Number of cycles decode is blocked system.cpu.decode.DECODE:DecodedInsts 3453639261 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 763587746 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 783418811 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 242953531 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 2690321 # Number of cycles decode is unblocking system.cpu.fetch.Branches 256168234 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 355186488 # Number of cache lines fetched system.cpu.fetch.Cycles 1201174807 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 10202313 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 3743631874 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 91259594 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.116450 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 355186488 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 183168209 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.701803 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 2199803710 system.cpu.fetch.rateDist.min_value 0 0 1353815392 6154.26% 1 255570605 1161.79% 2 82946121 377.06% 3 38413739 174.62% 4 83998079 381.84% 5 40983172 186.30% 6 33041033 150.20% 7 20511116 93.24% 8 290524453 1320.68% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 355186427 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 7448.556625 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5296.447076 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 355185076 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 10063000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1351 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 7155500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1351 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 262905.311621 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 355186427 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 7448.556625 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency system.cpu.icache.demand_hits 355185076 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 10063000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 1351 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 61 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 7155500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1351 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 355186427 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 7448.556625 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 355185076 # number of overall hits system.cpu.icache.overall_miss_latency 10063000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 1351 # number of overall misses system.cpu.icache.overall_mshr_hits 61 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 7155500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1351 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 207 # number of replacements system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 1040.211796 # Cycle average of tags in use system.cpu.icache.total_refs 355185076 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 8497 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 126707080 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed system.cpu.iew.EXEC:rate 1.003361 # Inst execution rate system.cpu.iew.EXEC:refs 760962527 # number of memory reference insts executed system.cpu.iew.EXEC:stores 208093186 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 1493645383 # num instructions consuming a value system.cpu.iew.WB:count 2165444744 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.962819 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1438109572 # num instructions producing a value system.cpu.iew.WB:rate 0.984381 # insts written-back per cycle system.cpu.iew.WB:sent 2178310152 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 91514542 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 458290 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 745124340 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 21362312 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 17090675 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 301027499 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 2876000922 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 552869341 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 140121943 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 2207196457 # Number of executed instructions system.cpu.iew.iewIQFullEvents 56098 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 8365 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 242953531 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 87287 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 119737756 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 85786 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 10100571 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 31 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 342612652 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 134179531 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 10100571 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1514083 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 90000459 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.677113 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.677113 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 2347318400 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 351441317 14.97% # Type of FU issued IntAlu 1181231771 50.32% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 3000185 0.13% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 586473179 24.98% # Type of FU issued MemWrite 225171948 9.59% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 3997880 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.001703 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 155579 3.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 244024 6.10% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 3267233 81.72% # attempts to use FU when none available MemWrite 331044 8.28% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 2199803710 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 993478594 4516.21% 1 570157916 2591.86% 2 321116547 1459.75% 3 178901320 813.26% 4 92584833 420.88% 5 34984610 159.04% 6 7286511 33.12% 7 1105050 5.02% 8 188329 0.86% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.067058 # Inst issue rate system.cpu.iq.iqInstsAdded 2854330173 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2347318400 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 21670749 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 1311892803 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 993660 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 19427250 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1293606933 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 275979 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 4897.575540 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2897.575540 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 1351628000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 275979 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 799670000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 275979 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 249421 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 4201.208939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2201.208939 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 64300 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 777732000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.742203 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 185121 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 407490000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.742203 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 185121 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 73301 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 4221.136137 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2221.136137 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_latency 309413500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 73301 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 162811500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 73301 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 346070 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_misses 346070 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 346070 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.935065 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 525400 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 4618.000434 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency system.cpu.l2cache.demand_hits 64300 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 2129360000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.877617 # miss rate for demand accesses system.cpu.l2cache.demand_misses 461100 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 1207160000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.877617 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 461100 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 525400 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 4618.000434 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 64300 # number of overall hits system.cpu.l2cache.overall_miss_latency 2129360000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.877617 # miss rate for overall accesses system.cpu.l2cache.overall_misses 461100 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 1207160000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.877617 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 461100 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 19390 # number of replacements system.cpu.l2cache.sampled_refs 20790 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 8555.838166 # Cycle average of tags in use system.cpu.l2cache.total_refs 102600 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 2199803710 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 12980165 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244762261 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers system.cpu.rename.RENAME:IQFullEvents 40711 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IdleCycles 826156851 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 20049545 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 4942866473 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 3108910588 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 2431469653 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 720639508 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 242953531 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 28416809 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 1186707392 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 368656846 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 21929426 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 159084902 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21683995 # count of temporary serializing insts renamed system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 19 # Number of system calls ---------- End Simulation Statistics ----------