---------- Begin Simulation Statistics ---------- host_inst_rate 185731 # Simulator instruction rate (inst/s) host_mem_usage 330796 # Number of bytes of host memory used host_seconds 306.85 # Real time elapsed on the host host_tick_rate 6194726969 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56990828 # Number of instructions simulated sim_seconds 1.900831 # Number of seconds simulated sim_ticks 1900831106500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.BPredUnit.BTBHits 5875746 # Number of BTB hits system.cpu0.BPredUnit.BTBLookups 11164335 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 27734 # Number of incorrect RAS predictions. system.cpu0.BPredUnit.condIncorrect 509345 # Number of conditional branches incorrect system.cpu0.BPredUnit.condPredicted 10431005 # Number of conditional branches predicted system.cpu0.BPredUnit.lookups 12489231 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 879926 # Number of times the RAS was used to get a target. system.cpu0.commit.COM:branches 7522155 # Number of branches committed system.cpu0.commit.COM:bw_lim_events 922955 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu0.commit.COM:committed_per_cycle::samples 78251630 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::mean 0.636074 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::stdev 1.403101 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::0 56997001 72.84% 72.84% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::1 9309948 11.90% 84.74% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::2 5423861 6.93% 91.67% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::3 2443172 3.12% 94.79% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::4 1857246 2.37% 97.16% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::5 632479 0.81% 97.97% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::6 343172 0.44% 98.41% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::7 321796 0.41% 98.82% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::8 922955 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::total 78251630 # Number of insts commited each cycle system.cpu0.commit.COM:count 49773809 # Number of instructions committed system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions. system.cpu0.commit.COM:function_calls 636047 # Number of function calls committed. system.cpu0.commit.COM:int_insts 46098602 # Number of committed integer instructions. system.cpu0.commit.COM:loads 7894859 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed system.cpu0.commit.COM:refs 13318738 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.branchMispredicts 652841 # The number of times a branch was mispredicted system.cpu0.commit.commitCommittedInsts 49773809 # The number of committed instructions system.cpu0.commit.commitNonSpecStalls 564763 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.commitSquashedInsts 7279602 # The number of squashed insts skipped by commit system.cpu0.committedInsts 46913237 # Number of Instructions Simulated system.cpu0.committedInsts_total 46913237 # Number of Instructions Simulated system.cpu0.cpi 2.403611 # CPI: Cycles Per Instruction system.cpu0.cpi_total 2.403611 # CPI: Total CPI of All Threads system.cpu0.dcache.LoadLockedReq_accesses::0 178261 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 178261 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_hits::0 158904 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 158904 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_latency 278417000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108588 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_misses::0 19357 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 19357 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_hits 4355 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158427500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084157 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_misses 15002 # number of LoadLockedReq MSHR misses system.cpu0.dcache.ReadReq_accesses::0 8017759 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8017759 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_hits::0 6640640 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6640640 # number of ReadReq hits system.cpu0.dcache.ReadReq_miss_latency 32717458500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_rate::0 0.171759 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_misses::0 1377119 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1377119 # number of ReadReq misses system.cpu0.dcache.ReadReq_mshr_hits 391971 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_miss_latency 23413523000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122871 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 985148 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920844000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_miss_latency 48641500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37679500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_avg_miss_latency::0 32402.197389 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.574400 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_hits::0 3607020 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 3607020 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_latency 52384340899 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_rate::0 0.309491 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses::0 1616691 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1616691 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_hits 1353284 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_miss_latency 8057771431 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050425 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 263407 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320171998 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8769.741125 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 8.499136 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 83743 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 734404431 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses::0 13241470 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 13241470 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency::0 28425.918612 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency system.cpu0.dcache.demand_hits::0 10247660 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 10247660 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 85101799399 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate::0 0.226093 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu0.dcache.demand_misses::0 2993810 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2993810 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 1745255 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 31471294431 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate::0 0.094291 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 1248555 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.occ_%::0 0.973190 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy system.cpu0.dcache.occ_blocks::0 498.273055 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context system.cpu0.dcache.overall_accesses::0 13241470 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 13241470 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency::0 28425.918612 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits::0 10247660 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits system.cpu0.dcache.overall_hits::total 10247660 # number of overall hits system.cpu0.dcache.overall_miss_latency 85101799399 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate::0 0.226093 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu0.dcache.overall_misses::0 2993810 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses system.cpu0.dcache.overall_misses::total 2993810 # number of overall misses system.cpu0.dcache.overall_mshr_hits 1745255 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 31471294431 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate::0 0.094291 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 1248555 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 2241015998 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 1246755 # number of replacements system.cpu0.dcache.sampled_refs 1247267 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.tagsinuse 497.273055 # Cycle average of tags in use system.cpu0.dcache.total_refs 10600692 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 721595 # number of writebacks system.cpu0.decode.DECODE:BlockedCycles 33789769 # Number of cycles decode is blocked system.cpu0.decode.DECODE:BranchMispred 33336 # Number of times decode detected a branch misprediction system.cpu0.decode.DECODE:BranchResolved 520770 # Number of times decode resolved a branch system.cpu0.decode.DECODE:DecodedInsts 62593203 # Number of instructions handled by decode system.cpu0.decode.DECODE:IdleCycles 32176765 # Number of cycles decode is idle system.cpu0.decode.DECODE:RunCycles 11304168 # Number of cycles decode is running system.cpu0.decode.DECODE:SquashCycles 1271210 # Number of cycles decode is squashing system.cpu0.decode.DECODE:SquashedInsts 100660 # Number of squashed instructions handled by decode system.cpu0.decode.DECODE:UnblockCycles 980927 # Number of cycles decode is unblocking system.cpu0.dtb.data_accesses 794756 # DTB accesses system.cpu0.dtb.data_acv 688 # DTB access violations system.cpu0.dtb.data_hits 14240512 # DTB hits system.cpu0.dtb.data_misses 32288 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 599054 # DTB read accesses system.cpu0.dtb.read_acv 519 # DTB read access violations system.cpu0.dtb.read_hits 8656143 # DTB read hits system.cpu0.dtb.read_misses 26649 # DTB read misses system.cpu0.dtb.write_accesses 195702 # DTB write accesses system.cpu0.dtb.write_acv 169 # DTB write access violations system.cpu0.dtb.write_hits 5584369 # DTB write hits system.cpu0.dtb.write_misses 5639 # DTB write misses system.cpu0.fetch.Branches 12489231 # Number of branches that fetch encountered system.cpu0.fetch.CacheLines 7790870 # Number of cache lines fetched system.cpu0.fetch.Cycles 12447773 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.IcacheSquashes 374462 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.Insts 63680808 # Number of instructions fetch has processed system.cpu0.fetch.MiscStallCycles 30775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.SquashCycles 745389 # Number of cycles fetch has spent squashing system.cpu0.fetch.branchRate 0.110758 # Number of branch fetches per cycle system.cpu0.fetch.icacheStallCycles 7790867 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.predictedBranches 6755672 # Number of branches that fetch has predicted taken system.cpu0.fetch.rate 0.564741 # Number of inst fetches per cycle system.cpu0.fetch.rateDist::samples 79522840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 0.800786 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 2.103997 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::0 67075067 84.35% 84.35% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 894690 1.13% 85.47% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 1774768 2.23% 87.70% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 813051 1.02% 88.73% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 2745482 3.45% 92.18% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::5 583376 0.73% 92.91% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 681368 0.86% 93.77% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 829891 1.04% 94.81% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 4125147 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 79522840 # Number of instructions fetched each cycle (Total) system.cpu0.fp_regfile_reads 120909 # number of floating regfile reads system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes system.cpu0.icache.ReadReq_accesses::0 7790870 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 7790870 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.877874 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.582299 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_hits::0 6933419 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 6933419 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_latency 12919109500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate::0 0.110058 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses::0 857451 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 857451 # number of ReadReq misses system.cpu0.icache.ReadReq_mshr_hits 36636 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_miss_latency 9863391000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105356 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 820815 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs 11214.285714 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 8.448187 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 628000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses::0 7790870 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 7790870 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency::0 15066.877874 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency system.cpu0.icache.demand_hits::0 6933419 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 6933419 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 12919109500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate::0 0.110058 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu0.icache.demand_misses::0 857451 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 857451 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 36636 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 9863391000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate::0 0.105356 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 820815 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context system.cpu0.icache.overall_accesses::0 7790870 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 7790870 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency::0 15066.877874 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits::0 6933419 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits system.cpu0.icache.overall_hits::total 6933419 # number of overall hits system.cpu0.icache.overall_miss_latency 12919109500 # number of overall miss cycles system.cpu0.icache.overall_miss_rate::0 0.110058 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu0.icache.overall_misses::0 857451 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses system.cpu0.icache.overall_misses::total 857451 # number of overall misses system.cpu0.icache.overall_mshr_hits 36636 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 9863391000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate::0 0.105356 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 820815 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.replacements 820188 # number of replacements system.cpu0.icache.sampled_refs 820699 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use system.cpu0.icache.total_refs 6933419 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 160 # number of writebacks system.cpu0.idleCycles 33238338 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.iew.EXEC:branches 8088609 # Number of branches executed system.cpu0.iew.EXEC:nop 3190653 # number of nop insts executed system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate system.cpu0.iew.EXEC:refs 14307346 # number of memory reference insts executed system.cpu0.iew.EXEC:stores 5602769 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed system.cpu0.iew.WB:consumers 31606079 # num instructions consuming a value system.cpu0.iew.WB:count 49988014 # cumulative count of insts written-back system.cpu0.iew.WB:fanout 0.757991 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.iew.WB:producers 23957137 # num instructions producing a value system.cpu0.iew.WB:rate 0.443309 # insts written-back per cycle system.cpu0.iew.WB:sent 50069991 # cumulative count of insts sent to commit system.cpu0.iew.branchMispredicts 711883 # Number of branch mispredicts detected at execute system.cpu0.iew.iewBlockCycles 9018658 # Number of cycles IEW is blocking system.cpu0.iew.iewDispLoadInsts 9134985 # Number of dispatched load instructions system.cpu0.iew.iewDispNonSpecInsts 1511781 # Number of dispatched non-speculative instructions system.cpu0.iew.iewDispSquashedInsts 755973 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispStoreInsts 5843371 # Number of dispatched store instructions system.cpu0.iew.iewDispatchedInsts 57163675 # Number of instructions dispatched to IQ system.cpu0.iew.iewExecLoadInsts 8704577 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 462590 # Number of squashed instructions skipped in execute system.cpu0.iew.iewExecutedInsts 50363992 # Number of executed instructions system.cpu0.iew.iewIQFullEvents 59575 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 7002 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewSquashCycles 1271210 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 547356 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 122264 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.lsq.thread.0.forwLoads 410769 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 10661 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread.0.memOrderViolation 38527 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 18607 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread.0.squashedLoads 1240126 # Number of loads squashed system.cpu0.iew.lsq.thread.0.squashedStores 419492 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 38527 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 332123 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 379760 # Number of branches that were predicted taken incorrectly system.cpu0.int_regfile_reads 66329017 # number of integer regfile reads system.cpu0.int_regfile_writes 36275514 # number of integer regfile writes system.cpu0.ipc 0.416041 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.416041 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35321880 69.49% 69.50% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntMult 55711 0.11% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003030 17.71% 87.36% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645816 11.11% 98.47% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779182 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::total 50826584 # Type of FU issued system.cpu0.iq.ISSUE:fu_busy_cnt 382291 # FU busy when requested system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IntAlu 40945 10.71% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::MemRead 226304 59.20% 69.91% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::MemWrite 115042 30.09% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:issued_per_cycle::samples 79522840 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639144 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209964 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::0 54765189 68.87% 68.87% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::1 12085919 15.20% 84.07% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::2 5449520 6.85% 90.92% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::3 3416832 4.30% 95.21% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::4 2223696 2.80% 98.01% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::5 992162 1.25% 99.26% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::6 434798 0.55% 99.81% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::7 111045 0.14% 99.95% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::8 43679 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::total 79522840 # Number of insts issued each cycle system.cpu0.iq.ISSUE:rate 0.450745 # Inst issue rate system.cpu0.iq.fp_alu_accesses 260468 # Number of floating point alu accesses system.cpu0.iq.fp_inst_queue_reads 508171 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_wakeup_accesses 246837 # Number of floating instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_writes 251931 # Number of floating instruction queue writes system.cpu0.iq.int_alu_accesses 50944645 # Number of integer alu accesses system.cpu0.iq.int_inst_queue_reads 181074223 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_wakeup_accesses 49741177 # Number of integer instruction queue wakeup accesses system.cpu0.iq.int_inst_queue_writes 60494022 # Number of integer instruction queue writes system.cpu0.iq.iqInstsAdded 52251057 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 50826584 # Number of instructions issued system.cpu0.iq.iqNonSpecInstsAdded 1721965 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqSquashedInstsExamined 6740106 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 24097 # Number of squashed instructions issued system.cpu0.iq.iqSquashedNonSpecRemoved 1157202 # Number of squashed non-spec instructions that were removed system.cpu0.iq.iqSquashedOperandsExamined 3425536 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.fetch_accesses 951932 # ITB accesses system.cpu0.itb.fetch_acv 733 # ITB acv system.cpu0.itb.fetch_hits 923000 # ITB hits system.cpu0.itb.fetch_misses 28932 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 351 0.22% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed system.cpu0.kern.callpal::swpipl 147044 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::rdusp 7 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 162036 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 176105 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 89358 58.06% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_count::total 153912 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks::0 1862707102000 97.99% 97.99% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 96290500 0.01% 98.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 398437500 0.02% 98.02% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 103382500 0.01% 98.03% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 37525043500 1.97% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1900830256000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.682793 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good::kernel 1171 system.cpu0.kern.mode_good::user 1172 system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches system.cpu0.kern.mode_switch::user 1172 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good::kernel 0.169956 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1898861301500 99.90% 99.90% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1968946500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed system.cpu0.kern.syscall::3 17 8.46% 11.44% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.49% 12.94% # number of syscalls executed system.cpu0.kern.syscall::6 27 13.43% 26.37% # number of syscalls executed system.cpu0.kern.syscall::12 1 0.50% 26.87% # number of syscalls executed system.cpu0.kern.syscall::17 9 4.48% 31.34% # number of syscalls executed system.cpu0.kern.syscall::19 6 2.99% 34.33% # number of syscalls executed system.cpu0.kern.syscall::20 4 1.99% 36.32% # number of syscalls executed system.cpu0.kern.syscall::23 1 0.50% 36.82% # number of syscalls executed system.cpu0.kern.syscall::24 3 1.49% 38.31% # number of syscalls executed system.cpu0.kern.syscall::33 7 3.48% 41.79% # number of syscalls executed system.cpu0.kern.syscall::41 2 1.00% 42.79% # number of syscalls executed system.cpu0.kern.syscall::45 36 17.91% 60.70% # number of syscalls executed system.cpu0.kern.syscall::47 3 1.49% 62.19% # number of syscalls executed system.cpu0.kern.syscall::48 7 3.48% 65.67% # number of syscalls executed system.cpu0.kern.syscall::54 9 4.48% 70.15% # number of syscalls executed system.cpu0.kern.syscall::58 1 0.50% 70.65% # number of syscalls executed system.cpu0.kern.syscall::59 5 2.49% 73.13% # number of syscalls executed system.cpu0.kern.syscall::71 27 13.43% 86.57% # number of syscalls executed system.cpu0.kern.syscall::73 3 1.49% 88.06% # number of syscalls executed system.cpu0.kern.syscall::74 7 3.48% 91.54% # number of syscalls executed system.cpu0.kern.syscall::87 1 0.50% 92.04% # number of syscalls executed system.cpu0.kern.syscall::90 1 0.50% 92.54% # number of syscalls executed system.cpu0.kern.syscall::92 7 3.48% 96.02% # number of syscalls executed system.cpu0.kern.syscall::97 2 1.00% 97.01% # number of syscalls executed system.cpu0.kern.syscall::98 2 1.00% 98.01% # number of syscalls executed system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed system.cpu0.memDep0.conflictingLoads 2323915 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 1919788 # Number of conflicting stores. system.cpu0.memDep0.insertedLoads 9134985 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 5843371 # Number of stores inserted to the mem dependence unit. system.cpu0.misc_regfile_reads 1626355 # number of misc regfile reads system.cpu0.misc_regfile_writes 787160 # number of misc regfile writes system.cpu0.numCycles 112761178 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.rename.RENAME:BlockCycles 12784143 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 33979065 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 1006573 # Number of times rename has blocked due to IQ full system.cpu0.rename.RENAME:IdleCycles 33581705 # Number of cycles rename is idle system.cpu0.rename.RENAME:LSQFullEvents 1371242 # Number of times rename has blocked due to LSQ full system.cpu0.rename.RENAME:ROBFullEvents 43321 # Number of times rename has blocked due to ROB full system.cpu0.rename.RENAME:RenameLookups 72539076 # Number of register rename lookups that rename has made system.cpu0.rename.RENAME:RenamedInsts 59327188 # Number of instructions processed by rename system.cpu0.rename.RENAME:RenamedOperands 39979686 # Number of destination operands rename has renamed system.cpu0.rename.RENAME:RunCycles 11035795 # Number of cycles rename is running system.cpu0.rename.RENAME:SquashCycles 1271210 # Number of cycles rename is squashing system.cpu0.rename.RENAME:UnblockCycles 3987790 # Number of cycles rename is unblocking system.cpu0.rename.RENAME:UndoneMaps 6000619 # Number of HB maps that are undone due to squashing system.cpu0.rename.RENAME:fp_rename_lookups 358919 # Number of floating rename lookups system.cpu0.rename.RENAME:int_rename_lookups 72180157 # Number of integer rename lookups system.cpu0.rename.RENAME:serializeStallCycles 16862195 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializingInsts 1393628 # count of serializing insts renamed system.cpu0.rename.RENAME:skidInsts 10087517 # count of insts added to the skid buffer system.cpu0.rename.RENAME:tempSerializingInsts 207585 # count of temporary serializing insts renamed system.cpu0.rob.rob_reads 134196797 # The number of ROB reads system.cpu0.rob.rob_writes 115377386 # The number of ROB writes system.cpu0.timesIdled 1187168 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.BTBHits 1161804 # Number of BTB hits system.cpu1.BPredUnit.BTBLookups 2701483 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 8265 # Number of incorrect RAS predictions. system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect system.cpu1.BPredUnit.condPredicted 2484023 # Number of conditional branches predicted system.cpu1.BPredUnit.lookups 2997822 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 209923 # Number of times the RAS was used to get a target. system.cpu1.commit.COM:branches 1520807 # Number of branches committed system.cpu1.commit.COM:bw_lim_events 198341 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.COM:committed_per_cycle::samples 17840200 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::mean 0.594448 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::stdev 1.407345 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::0 13454331 75.42% 75.42% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::1 2070557 11.61% 87.02% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::2 797281 4.47% 91.49% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::3 568657 3.19% 94.68% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::4 399402 2.24% 96.92% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::5 150078 0.84% 97.76% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::6 111624 0.63% 98.38% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::7 89929 0.50% 98.89% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::8 198341 1.11% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::total 17840200 # Number of insts commited each cycle system.cpu1.commit.COM:count 10605063 # Number of instructions committed system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions. system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed. system.cpu1.commit.COM:int_insts 9814594 # Number of committed integer instructions. system.cpu1.commit.COM:loads 1991971 # Number of loads committed system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed system.cpu1.commit.COM:refs 3376356 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.branchMispredicts 164474 # The number of times a branch was mispredicted system.cpu1.commit.commitCommittedInsts 10605063 # The number of committed instructions system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.commitSquashedInsts 1721637 # The number of squashed insts skipped by commit system.cpu1.committedInsts 10077591 # Number of Instructions Simulated system.cpu1.committedInsts_total 10077591 # Number of Instructions Simulated system.cpu1.cpi 1.948947 # CPI: Cycles Per Instruction system.cpu1.cpi_total 1.948947 # CPI: Total CPI of All Threads system.cpu1.dcache.LoadLockedReq_accesses::0 46373 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 46373 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11076.917360 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7999.664711 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_hits::0 39645 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 39645 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_latency 74525500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145084 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_misses::0 6728 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 6728 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_mshr_hits 763 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47718000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128631 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 5965 # number of LoadLockedReq MSHR misses system.cpu1.dcache.ReadReq_accesses::0 2063020 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 2063020 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_avg_miss_latency::0 15006.932779 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11671.409798 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_hits::0 1868365 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1868365 # number of ReadReq hits system.cpu1.dcache.ReadReq_miss_latency 2921174500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_rate::0 0.094354 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses::0 194655 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 194655 # number of ReadReq misses system.cpu1.dcache.ReadReq_mshr_hits 99535 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_miss_latency 1110184500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046107 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 95120 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13132.452048 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10137.707469 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_hits::0 39338 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 39338 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_miss_latency 50665000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089314 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_misses::0 3858 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 3858 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39091000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089268 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_avg_miss_latency::0 21239.554449 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18778.969096 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_hits::0 1085291 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 1085291 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_latency 5299459991 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_rate::0 0.186926 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses::0 249509 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 249509 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 201036 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_miss_latency 910272969 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036315 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 48473 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377656000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9801.734092 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 22.873773 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 5359 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 52527493 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses::0 3397820 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 3397820 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency::0 18508.106220 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency system.cpu1.dcache.demand_hits::0 2953656 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 2953656 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 8220634491 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate::0 0.130720 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu1.dcache.demand_misses::0 444164 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 444164 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 300571 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 2020457469 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate::0 0.042260 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 143593 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.occ_%::0 0.933239 # Average percentage of cache occupancy system.cpu1.dcache.occ_blocks::0 477.818308 # Average occupied blocks per context system.cpu1.dcache.overall_accesses::0 3397820 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 3397820 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency::0 18508.106220 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits::0 2953656 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits system.cpu1.dcache.overall_hits::total 2953656 # number of overall hits system.cpu1.dcache.overall_miss_latency 8220634491 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate::0 0.130720 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu1.dcache.overall_misses::0 444164 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses system.cpu1.dcache.overall_misses::total 444164 # number of overall misses system.cpu1.dcache.overall_mshr_hits 300571 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 2020457469 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate::0 0.042260 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 143593 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 395333500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 132541 # number of replacements system.cpu1.dcache.sampled_refs 132935 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.tagsinuse 477.818308 # Cycle average of tags in use system.cpu1.dcache.total_refs 3040725 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 88729 # number of writebacks system.cpu1.decode.DECODE:BlockedCycles 6964749 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 7942 # Number of times decode detected a branch misprediction system.cpu1.decode.DECODE:BranchResolved 127908 # Number of times decode resolved a branch system.cpu1.decode.DECODE:DecodedInsts 13950494 # Number of instructions handled by decode system.cpu1.decode.DECODE:IdleCycles 8268833 # Number of cycles decode is idle system.cpu1.decode.DECODE:RunCycles 2507185 # Number of cycles decode is running system.cpu1.decode.DECODE:SquashCycles 305915 # Number of cycles decode is squashing system.cpu1.decode.DECODE:SquashedInsts 23718 # Number of squashed instructions handled by decode system.cpu1.decode.DECODE:UnblockCycles 99432 # Number of cycles decode is unblocking system.cpu1.dtb.data_accesses 453938 # DTB accesses system.cpu1.dtb.data_acv 180 # DTB access violations system.cpu1.dtb.data_hits 3612649 # DTB hits system.cpu1.dtb.data_misses 12920 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 321913 # DTB read accesses system.cpu1.dtb.read_acv 80 # DTB read access violations system.cpu1.dtb.read_hits 2185375 # DTB read hits system.cpu1.dtb.read_misses 10510 # DTB read misses system.cpu1.dtb.write_accesses 132025 # DTB write accesses system.cpu1.dtb.write_acv 100 # DTB write access violations system.cpu1.dtb.write_hits 1427274 # DTB write hits system.cpu1.dtb.write_misses 2410 # DTB write misses system.cpu1.fetch.Branches 2997822 # Number of branches that fetch encountered system.cpu1.fetch.CacheLines 1676432 # Number of cache lines fetched system.cpu1.fetch.Cycles 2639364 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.IcacheSquashes 103824 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.Insts 14202816 # Number of instructions fetch has processed system.cpu1.fetch.MiscStallCycles 9160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.SquashCycles 191448 # Number of cycles fetch has spent squashing system.cpu1.fetch.branchRate 0.152633 # Number of branch fetches per cycle system.cpu1.fetch.icacheStallCycles 1676430 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.predictedBranches 1371727 # Number of branches that fetch has predicted taken system.cpu1.fetch.rate 0.723132 # Number of inst fetches per cycle system.cpu1.fetch.rateDist::samples 18146115 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 0.782692 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 2.130549 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 15506751 85.45% 85.45% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 211557 1.17% 86.62% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 323359 1.78% 88.40% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 200500 1.10% 89.51% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::4 379117 2.09% 91.60% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::5 126850 0.70% 92.30% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 170740 0.94% 93.24% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 250045 1.38% 94.61% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 977196 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 18146115 # Number of instructions fetched each cycle (Total) system.cpu1.fp_regfile_reads 63126 # number of floating regfile reads system.cpu1.fp_regfile_writes 63154 # number of floating regfile writes system.cpu1.icache.ReadReq_accesses::0 1676432 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 1676432 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.725411 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.810943 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_hits::0 1412386 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 1412386 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_latency 3874538500 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_rate::0 0.157505 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses::0 264046 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 264046 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_hits 8197 # number of ReadReq MSHR hits system.cpu1.icache.ReadReq_mshr_miss_latency 2975475500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152615 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 255849 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs 5555.555556 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 5.521576 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 50000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses::0 1676432 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 1676432 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency::0 14673.725411 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency system.cpu1.icache.demand_hits::0 1412386 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 1412386 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 3874538500 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate::0 0.157505 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu1.icache.demand_misses::0 264046 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 264046 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 8197 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 2975475500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate::0 0.152615 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 255849 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy system.cpu1.icache.occ_blocks::0 461.022397 # Average occupied blocks per context system.cpu1.icache.overall_accesses::0 1676432 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 1676432 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency::0 14673.725411 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits::0 1412386 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits system.cpu1.icache.overall_hits::total 1412386 # number of overall hits system.cpu1.icache.overall_miss_latency 3874538500 # number of overall miss cycles system.cpu1.icache.overall_miss_rate::0 0.157505 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu1.icache.overall_misses::0 264046 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses system.cpu1.icache.overall_misses::total 264046 # number of overall misses system.cpu1.icache.overall_mshr_hits 8197 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 2975475500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate::0 0.152615 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 255849 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.replacements 255282 # number of replacements system.cpu1.icache.sampled_refs 255794 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.tagsinuse 461.022397 # Cycle average of tags in use system.cpu1.icache.total_refs 1412386 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 1897915594000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 23 # number of writebacks system.cpu1.idleCycles 1494579 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.iew.EXEC:branches 1630757 # Number of branches executed system.cpu1.iew.EXEC:nop 601681 # number of nop insts executed system.cpu1.iew.EXEC:rate 0.552014 # Inst execution rate system.cpu1.iew.EXEC:refs 3642117 # number of memory reference insts executed system.cpu1.iew.EXEC:stores 1436733 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed system.cpu1.iew.WB:consumers 6271876 # num instructions consuming a value system.cpu1.iew.WB:count 10737023 # cumulative count of insts written-back system.cpu1.iew.WB:fanout 0.735626 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.iew.WB:producers 4613753 # num instructions producing a value system.cpu1.iew.WB:rate 0.546672 # insts written-back per cycle system.cpu1.iew.WB:sent 10760010 # cumulative count of insts sent to commit system.cpu1.iew.branchMispredicts 178779 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 257448 # Number of cycles IEW is blocking system.cpu1.iew.iewDispLoadInsts 2307630 # Number of dispatched load instructions system.cpu1.iew.iewDispNonSpecInsts 500245 # Number of dispatched non-speculative instructions system.cpu1.iew.iewDispSquashedInsts 209270 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispStoreInsts 1513195 # Number of dispatched store instructions system.cpu1.iew.iewDispatchedInsts 12409620 # Number of instructions dispatched to IQ system.cpu1.iew.iewExecLoadInsts 2205384 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 107607 # Number of squashed instructions skipped in execute system.cpu1.iew.iewExecutedInsts 10841947 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 2515 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 4902 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.iewSquashCycles 305915 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 10123 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 20397 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.lsq.thread.0.forwLoads 68108 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 2244 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread.0.memOrderViolation 10644 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 381 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread.0.squashedLoads 315659 # Number of loads squashed system.cpu1.iew.lsq.thread.0.squashedStores 128810 # Number of stores squashed system.cpu1.iew.memOrderViolationEvents 10644 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 104770 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 74009 # Number of branches that were predicted taken incorrectly system.cpu1.int_regfile_reads 13934200 # number of integer regfile reads system.cpu1.int_regfile_writes 7613029 # number of integer regfile writes system.cpu1.ipc 0.513098 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.513098 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6872542 62.77% 62.80% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IntMult 18152 0.17% 62.96% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.96% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.07% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::MemRead 2280411 20.83% 83.91% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453875 13.28% 97.19% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::total 10949554 # Type of FU issued system.cpu1.iq.ISSUE:fu_busy_cnt 155065 # FU busy when requested system.cpu1.iq.ISSUE:fu_busy_rate 0.014162 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IntAlu 4030 2.60% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::MemRead 91114 58.76% 61.36% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::MemWrite 59921 38.64% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:issued_per_cycle::samples 18146115 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603410 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.208341 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::0 12918859 71.19% 71.19% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::1 2566374 14.14% 85.34% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::2 1069941 5.90% 91.23% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::3 687798 3.79% 95.02% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::4 527186 2.91% 97.93% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::5 238422 1.31% 99.24% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::6 93189 0.51% 99.76% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::7 34852 0.19% 99.95% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::8 9494 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::total 18146115 # Number of insts issued each cycle system.cpu1.iq.ISSUE:rate 0.557493 # Inst issue rate system.cpu1.iq.fp_alu_accesses 125187 # Number of floating point alu accesses system.cpu1.iq.fp_inst_queue_reads 243060 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_wakeup_accesses 117556 # Number of floating instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_writes 119680 # Number of floating instruction queue writes system.cpu1.iq.int_alu_accesses 10975908 # Number of integer alu accesses system.cpu1.iq.int_inst_queue_reads 39967405 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_wakeup_accesses 10619467 # Number of integer instruction queue wakeup accesses system.cpu1.iq.int_inst_queue_writes 13352100 # Number of integer instruction queue writes system.cpu1.iq.iqInstsAdded 11252265 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 10949554 # Number of instructions issued system.cpu1.iq.iqNonSpecInstsAdded 555674 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqSquashedInstsExamined 1655179 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedInstsIssued 10177 # Number of squashed instructions issued system.cpu1.iq.iqSquashedNonSpecRemoved 392670 # Number of squashed non-spec instructions that were removed system.cpu1.iq.iqSquashedOperandsExamined 852165 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.fetch_accesses 448608 # ITB accesses system.cpu1.itb.fetch_acv 274 # ITB acv system.cpu1.itb.fetch_hits 439933 # ITB hits system.cpu1.itb.fetch_misses 8675 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 254 0.45% 0.45% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed system.cpu1.kern.callpal::swpipl 49364 86.50% 89.53% # number of callpals executed system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed system.cpu1.kern.callpal::rdusp 2 0.00% 93.72% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.72% # number of callpals executed system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # number of callpals executed system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.callpal::total 57066 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 64904 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed system.cpu1.kern.ipl_count::0 20664 37.58% 37.58% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1922 3.50% 41.07% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl system.cpu1.kern.ipl_count::31 32053 58.29% 100.00% # number of times we switched to this ipl system.cpu1.kern.ipl_count::total 54990 # number of times we switched to this ipl system.cpu1.kern.ipl_good::0 20157 47.72% 47.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_ticks::0 1870770905000 98.44% 98.44% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 347965500 0.02% 98.46% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 137591500 0.01% 98.46% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 29223562000 1.54% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::total 1900480024000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.617914 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good::kernel 849 system.cpu1.kern.mode_good::user 573 system.cpu1.kern.mode_good::idle 276 system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches system.cpu1.kern.mode_switch::user 573 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2541 # number of protection mode switches system.cpu1.kern.mode_switch_good::kernel 0.480747 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 6317215000 0.33% 0.33% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 1021115000 0.05% 0.39% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1893129227000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.80% 12.80% # number of syscalls executed system.cpu1.kern.syscall::6 15 12.00% 24.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.80% 25.60% # number of syscalls executed system.cpu1.kern.syscall::17 6 4.80% 30.40% # number of syscalls executed system.cpu1.kern.syscall::19 4 3.20% 33.60% # number of syscalls executed system.cpu1.kern.syscall::20 2 1.60% 35.20% # number of syscalls executed system.cpu1.kern.syscall::23 3 2.40% 37.60% # number of syscalls executed system.cpu1.kern.syscall::24 3 2.40% 40.00% # number of syscalls executed system.cpu1.kern.syscall::33 4 3.20% 43.20% # number of syscalls executed system.cpu1.kern.syscall::45 18 14.40% 57.60% # number of syscalls executed system.cpu1.kern.syscall::47 3 2.40% 60.00% # number of syscalls executed system.cpu1.kern.syscall::48 3 2.40% 62.40% # number of syscalls executed system.cpu1.kern.syscall::54 1 0.80% 63.20% # number of syscalls executed system.cpu1.kern.syscall::59 2 1.60% 64.80% # number of syscalls executed system.cpu1.kern.syscall::71 27 21.60% 86.40% # number of syscalls executed system.cpu1.kern.syscall::74 9 7.20% 93.60% # number of syscalls executed system.cpu1.kern.syscall::90 2 1.60% 95.20% # number of syscalls executed system.cpu1.kern.syscall::92 2 1.60% 96.80% # number of syscalls executed system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed system.cpu1.memDep0.conflictingLoads 495102 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 416651 # Number of conflicting stores. system.cpu1.memDep0.insertedLoads 2307630 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 1513195 # Number of stores inserted to the mem dependence unit. system.cpu1.misc_regfile_reads 594453 # number of misc regfile reads system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes system.cpu1.numCycles 19640694 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.rename.RENAME:BlockCycles 523712 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 7159591 # Number of HB maps that are committed system.cpu1.rename.RENAME:IQFullEvents 32710 # Number of times rename has blocked due to IQ full system.cpu1.rename.RENAME:IdleCycles 8501498 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 256763 # Number of times rename has blocked due to LSQ full system.cpu1.rename.RENAME:ROBFullEvents 15504 # Number of times rename has blocked due to ROB full system.cpu1.rename.RENAME:RenameLookups 15470992 # Number of register rename lookups that rename has made system.cpu1.rename.RENAME:RenamedInsts 12928500 # Number of instructions processed by rename system.cpu1.rename.RENAME:RenamedOperands 8487290 # Number of destination operands rename has renamed system.cpu1.rename.RENAME:RunCycles 2361527 # Number of cycles rename is running system.cpu1.rename.RENAME:SquashCycles 305915 # Number of cycles rename is squashing system.cpu1.rename.RENAME:UnblockCycles 801170 # Number of cycles rename is unblocking system.cpu1.rename.RENAME:UndoneMaps 1327699 # Number of HB maps that are undone due to squashing system.cpu1.rename.RENAME:fp_rename_lookups 171482 # Number of floating rename lookups system.cpu1.rename.RENAME:int_rename_lookups 15299510 # Number of integer rename lookups system.cpu1.rename.RENAME:serializeStallCycles 5652291 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializingInsts 515456 # count of serializing insts renamed system.cpu1.rename.RENAME:skidInsts 2302074 # count of insts added to the skid buffer system.cpu1.rename.RENAME:tempSerializingInsts 52719 # count of temporary serializing insts renamed system.cpu1.rob.rob_reads 29864417 # The number of ROB reads system.cpu1.rob.rob_writes 24957573 # The number of ROB writes system.cpu1.timesIdled 194633 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 172 # number of ReadReq misses system.iocache.ReadReq_misses::total 172 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::1 137701.983202 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85698.425972 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5721792806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3560940996 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6175.644708 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_mshrs 64591068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency system.iocache.demand_avg_miss_latency::1 137609.500623 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5741618804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3571822994 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41724 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.occ_%::1 0.029206 # Average percentage of cache occupancy system.iocache.occ_blocks::1 0.467303 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency system.iocache.overall_avg_miss_latency::1 137609.500623 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5741618804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3571822994 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41724 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.tagsinuse 0.467303 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks system.l2c.ReadExReq_accesses::0 257283 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 42295 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 299578 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 55985.536569 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 837818.012343 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40324.759412 # average ReadExReq mshr miss latency system.l2c.ReadExReq_hits::0 140886 # number of ReadExReq hits system.l2c.ReadExReq_hits::1 34517 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 175403 # number of ReadExReq hits system.l2c.ReadExReq_miss_latency 6516548500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 0.452408 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 0.183899 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 116397 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5007327000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 0.482640 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 2.935926 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses system.l2c.ReadReq_accesses::0 1807428 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::1 343680 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2151108 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_avg_miss_latency::0 52801.503186 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 3683358.780376 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40018.194749 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_hits::0 1503141 # number of ReadReq hits system.l2c.ReadReq_hits::1 339318 # number of ReadReq hits system.l2c.ReadReq_hits::total 1842459 # number of ReadReq hits system.l2c.ReadReq_miss_latency 16066811000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.168354 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::1 0.012692 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 304287 # number of ReadReq misses system.l2c.ReadReq_misses::1 4362 # number of ReadReq misses system.l2c.ReadReq_misses::total 308649 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 12350935500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::0 0.170758 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 0.898024 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 308633 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 840464000 # number of ReadReq MSHR uncacheable cycles system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_avg_miss_latency::0 4879.928315 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 4727.430556 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40008.377425 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_hits::0 51 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::1 25 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_miss_latency 2723000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 0.916256 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::1 0.958403 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_misses::0 558 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::1 576 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1134 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_mshr_miss_latency 45369500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.862069 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses system.l2c.UpgradeReq_accesses::0 2883 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 12567.610063 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.991504 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::1 350 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 503 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 0.946930 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 0.784217 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 1272 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 4002 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 160148000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1.388137 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 2.467324 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 4002 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1532817998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 810507 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 810507 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 810507 # number of Writeback hits system.l2c.Writeback_hits::total 810507 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 5.658014 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses::0 2064711 # number of demand (read+write) accesses system.l2c.demand_accesses::1 385975 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2450686 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 53682.477822 # average overall miss latency system.l2c.demand_avg_miss_latency::1 1860243.780890 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency system.l2c.demand_hits::0 1644027 # number of demand (read+write) hits system.l2c.demand_hits::1 373835 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits system.l2c.demand_hits::total 2017862 # number of demand (read+write) hits system.l2c.demand_miss_latency 22583359500 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.203750 # miss rate for demand accesses system.l2c.demand_miss_rate::1 0.031453 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses system.l2c.demand_misses::0 420684 # number of demand (read+write) misses system.l2c.demand_misses::1 12140 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses system.l2c.demand_misses::total 432824 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 17358262500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0.209622 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 1.121337 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 432808 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.occ_%::0 0.187716 # Average percentage of cache occupancy system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy system.l2c.occ_blocks::0 12302.143800 # Average occupied blocks per context system.l2c.occ_blocks::1 376.171509 # Average occupied blocks per context system.l2c.occ_blocks::2 23058.900248 # Average occupied blocks per context system.l2c.overall_accesses::0 2064711 # number of overall (read+write) accesses system.l2c.overall_accesses::1 385975 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2450686 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 53682.477822 # average overall miss latency system.l2c.overall_avg_miss_latency::1 1860243.780890 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.overall_hits::0 1644027 # number of overall hits system.l2c.overall_hits::1 373835 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits system.l2c.overall_hits::total 2017862 # number of overall hits system.l2c.overall_miss_latency 22583359500 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.203750 # miss rate for overall accesses system.l2c.overall_miss_rate::1 0.031453 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses system.l2c.overall_misses::0 420684 # number of overall misses system.l2c.overall_misses::1 12140 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses system.l2c.overall_misses::total 432824 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 17358262500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0.209622 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 1.121337 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 432808 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2373281998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 395559 # number of replacements system.l2c.sampled_refs 431638 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.tagsinuse 35737.215556 # Cycle average of tags in use system.l2c.total_refs 2442214 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 121360 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR ---------- End Simulation Statistics ----------