---------- Begin Simulation Statistics ---------- host_inst_rate 1404297 # Simulator instruction rate (inst/s) host_mem_usage 200728 # Number of bytes of host memory used host_seconds 398.40 # Real time elapsed on the host host_tick_rate 1806912378 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 559470527 # Number of instructions simulated sim_seconds 0.719872 # Number of seconds simulated sim_ticks 719872424000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 15508654000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 13159666000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 55371547 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 10029586000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006394 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 356300 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 8960686000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006394 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 356300 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 22415.807657 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency system.cpu.dcache.demand_hits 181914877 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 25538240000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006224 # miss rate for demand accesses system.cpu.dcache.demand_misses 1139296 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 22120352000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006224 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1139296 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.992721 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4066.183353 # Average occupied blocks per context system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22415.807657 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 181914877 # number of overall hits system.cpu.dcache.overall_miss_latency 25538240000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006224 # miss rate for overall accesses system.cpu.dcache.overall_misses 1139296 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 22120352000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006224 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1139296 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1135200 # number of replacements system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4066.183353 # Cycle average of tags in use system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1025629 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 44452.238521 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.482234 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 987.615046 # Average occupied blocks per context system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 512134240 # number of overall hits system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses system.cpu.icache.overall_misses 11521 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 9788 # number of replacements system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 987.615046 # Cycle average of tags in use system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 236267 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_miss_latency 6241716000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.336887 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 120033 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336887 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 120033 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 683315 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 5782504000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.139962 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 111202 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 4448080000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139962 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 111202 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 1025629 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 1025629 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 6.147006 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 919582 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 12024220000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.200931 # miss rate for demand accesses system.cpu.l2cache.demand_misses 231235 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 9249400000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.200931 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 231235 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.178887 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.445562 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 5861.784368 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 14600.161549 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 919582 # number of overall hits system.cpu.l2cache.overall_miss_latency 12024220000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.200931 # miss rate for overall accesses system.cpu.l2cache.overall_misses 231235 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 9249400000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.200931 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 231235 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 212119 # number of replacements system.cpu.l2cache.sampled_refs 232160 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 20461.945917 # Cycle average of tags in use system.cpu.l2cache.total_refs 1427089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 510281834000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 172310 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1439744848 # number of cpu cycles simulated system.cpu.num_insts 559470527 # Number of instructions executed system.cpu.num_refs 184987503 # Number of memory references system.cpu.workload.PROG:num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ----------