---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 8028209 # Number of BTB hits global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted global.BPredUnit.lookups 16239906 # Number of BP lookups global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target. host_inst_rate 108698 # Simulator instruction rate (inst/s) host_mem_usage 171788 # Number of bytes of host memory used host_seconds 732.23 # Real time elapsed on the host host_tick_rate 34286652 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads. memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores. memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.025106 # Number of seconds simulated sim_ticks 25105678500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 48941983 system.cpu.commit.COM:committed_per_cycle.min_value 0 0 20096984 4106.29% 1 10996856 2246.92% 2 5104227 1042.91% 3 3459002 706.76% 4 2556441 522.34% 5 1507300 307.98% 6 975853 199.39% 7 821586 167.87% 8 3423734 699.55% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 20452895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 8143.771495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.007108 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 145380 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003008 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 7484.182742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.069117 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1010036 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 165.460856 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 35066272 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 7567.175372 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.032949 # miss rate for demand accesses system.cpu.dcache.demand_misses 1155416 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 35066272 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 7567.175372 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 33910856 # number of overall hits system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.032949 # miss rate for overall accesses system.cpu.dcache.overall_misses 1155416 # number of overall misses system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 200914 # number of replacements system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use system.cpu.dcache.total_refs 33921130 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147756 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking system.cpu.dtb.accesses 36627367 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations system.cpu.dtb.hits 36456086 # DTB hits system.cpu.dtb.misses 171281 # DTB misses system.cpu.dtb.read_accesses 21562223 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations system.cpu.dtb.read_hits 21405571 # DTB read hits system.cpu.dtb.read_misses 156652 # DTB read misses system.cpu.dtb.write_accesses 15065144 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations system.cpu.dtb.write_hits 15050515 # DTB write hits system.cpu.dtb.write_misses 14629 # DTB write misses system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 50204254 system.cpu.fetch.rateDist.min_value 0 0 30393344 6053.94% 1 1855009 369.49% 2 1535971 305.94% 3 1792342 357.01% 4 4000264 796.80% 5 1878750 374.22% 6 697475 138.93% 7 1087494 216.61% 8 6963605 1387.05% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 13373612 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 5755.491777 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.006474 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 86584 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.006388 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 13373612 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 5755.491777 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.006474 # miss rate for demand accesses system.cpu.icache.demand_misses 86584 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.006388 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 13373612 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 5755.491777 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 13287028 # number of overall hits system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.006474 # miss rate for overall accesses system.cpu.icache.overall_misses 86584 # number of overall misses system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.006388 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 83382 # number of replacements system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 14739955 # Number of branches executed system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed system.cpu.iew.EXEC:stores 15298022 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 32426009 # num instructions producing a value system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued IntAlu 47875288 56.09% # Type of FU issued IntMult 42930 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 121387 0.14% # Type of FU issued FloatCmp 87 0.00% # Type of FU issued FloatCvt 121941 0.14% # Type of FU issued FloatMult 50 0.00% # Type of FU issued FloatDiv 38534 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 21778158 25.51% # Type of FU issued MemWrite 15380330 18.02% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 96046 9.70% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 442273 44.69% # attempts to use FU when none available MemWrite 451365 45.61% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 15297066 3046.97% 1 13336776 2656.50% 2 8168141 1626.98% 3 4718425 939.85% 4 4728752 941.90% 5 2063960 411.11% 6 1191217 237.27% 7 451074 89.85% 8 248843 49.57% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 13398974 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 13373612 # ITB hits system.cpu.itb.misses 25362 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 102374 # number of overall hits system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses system.cpu.l2cache.overall_misses 188067 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 148782 # number of replacements system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120646 # number of writebacks system.cpu.numCycles 50211358 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ----------