---------- Begin Simulation Statistics ---------- sim_seconds 1.841723 # Number of seconds simulated sim_ticks 1841722715000 # Number of ticks simulated final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 105391 # Simulator instruction rate (inst/s) host_op_rate 105391 # Simulator op (including micro ops) rate (op/s) host_tick_rate 2775370642 # Simulator tick rate (ticks/s) host_mem_usage 350548 # Number of bytes of host memory used host_seconds 663.60 # Real time elapsed on the host sim_insts 69936964 # Number of instructions simulated sim_ops 69936964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 109804 # Total number of read requests seen system.physmem.writeReqs 45341 # Total number of write requests seen system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 7027456 # Total number of bytes read from memory system.physmem.bytesWritten 2901824 # Total number of bytes written to memory system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 2753 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3191 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 2906 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry system.physmem.totGap 1840710411000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 109804 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 45341 # Categorize write packet sizes system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1970 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1187 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1085 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1083 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1070 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1047 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 612 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 589 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 568 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 553 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 554 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 577 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 669 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 359 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 305 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1251 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1428 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1611 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1823 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1970 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1968 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1964 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1971 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1969 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1963 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1958 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 1958 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 1955 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 1949 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 775 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 572 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 377 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 162 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see system.physmem.totQLat 2345988500 # Total cycles spent in queuing delays system.physmem.totMemAccLat 4348949750 # Sum of mem lat for all requests system.physmem.totBusLat 548995000 # Total cycles spent in databus access system.physmem.totBankLat 1453966250 # Total cycles spent in bank access system.physmem.avgQLat 21366.21 # Average queueing delay per request system.physmem.avgBankLat 13242.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 39608.28 # Average memory access latency system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time system.physmem.readRowHits 99788 # Number of row buffer hits during reads system.physmem.writeRowHits 34189 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes system.physmem.avgGap 11864452.04 # Average gap between requests system.l2c.replacements 337462 # number of replacements system.l2c.tagsinuse 65423.385083 # Cycle average of tags in use system.l2c.total_refs 2475374 # Total number of references to valid blocks. system.l2c.sampled_refs 402624 # Sample count of references to valid blocks. system.l2c.avg_refs 6.148103 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 54864.603018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 2279.979000 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 2628.690447 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 619.088006 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 659.286821 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.inst 2246.098023 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.data 2125.639768 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.837167 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.034790 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.040111 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.010060 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.inst 0.034273 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.032435 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.998282 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 516841 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 491603 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 126887 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 83607 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 295482 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 241937 # number of ReadReq hits system.l2c.ReadReq_hits::total 1756357 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 836151 # number of Writeback hits system.l2c.Writeback_hits::total 836151 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 92117 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 27417 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2.data 67376 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 186910 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 516841 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 583720 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 126887 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 111024 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 295482 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 309313 # number of demand (read+write) hits system.l2c.demand_hits::total 1943267 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 516841 # number of overall hits system.l2c.overall_hits::cpu0.data 583720 # number of overall hits system.l2c.overall_hits::cpu1.inst 126887 # number of overall hits system.l2c.overall_hits::cpu1.data 111024 # number of overall hits system.l2c.overall_hits::cpu2.inst 295482 # number of overall hits system.l2c.overall_hits::cpu2.data 309313 # number of overall hits system.l2c.overall_hits::total 1943267 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 7386 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 225256 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 2379 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 23009 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 4597 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 24998 # number of ReadReq misses system.l2c.ReadReq_misses::total 287625 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 77538 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 20985 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 17224 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 115747 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 7386 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 302794 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2379 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 43994 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 4597 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 42222 # number of demand (read+write) misses system.l2c.demand_misses::total 403372 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 7386 # number of overall misses system.l2c.overall_misses::cpu0.data 302794 # number of overall misses system.l2c.overall_misses::cpu1.inst 2379 # number of overall misses system.l2c.overall_misses::cpu1.data 43994 # number of overall misses system.l2c.overall_misses::cpu2.inst 4597 # number of overall misses system.l2c.overall_misses::cpu2.data 42222 # number of overall misses system.l2c.overall_misses::total 403372 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.inst 156027500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 1047000000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 315202000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 1118067500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 2636297000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 291000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 973607000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1279851000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 2253458000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.inst 156027500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 2020607000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 315202000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 2397918500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 4889755000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.inst 156027500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 2020607000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 315202000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 2397918500 # number of overall miss cycles system.l2c.overall_miss_latency::total 4889755000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 524227 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 716859 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 129266 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 106616 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 300079 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 266935 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2043982 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 836151 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 836151 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 169655 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 48402 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 84600 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 302657 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 524227 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 886514 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 129266 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 155018 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 300079 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 351535 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2346639 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 524227 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 886514 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 129266 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 155018 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 300079 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 351535 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2346639 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.014089 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.314226 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.018404 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.215812 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.015319 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.093648 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.140718 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.457033 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.433556 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 0.203593 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.382436 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.014089 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.341556 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.018404 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.283799 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.015319 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.120108 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.171894 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.014089 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.341556 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.018404 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.283799 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.015319 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.120108 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.171894 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65585.329971 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 45503.933244 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 68566.891451 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 44726.278102 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 9165.743590 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24250 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 14550 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46395.377651 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74306.258709 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 19468.824246 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 65585.329971 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 45929.149429 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 68566.891451 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 56793.105490 # average overall miss latency system.l2c.demand_avg_miss_latency::total 12122.197376 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 65585.329971 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 45929.149429 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 68566.891451 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 56793.105490 # average overall miss latency system.l2c.overall_avg_miss_latency::total 12122.197376 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 75151 # number of writebacks system.l2c.writebacks::total 75151 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu1.inst 2379 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 23009 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.inst 4597 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 24998 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 54983 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 20985 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 17224 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 38209 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2379 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 43994 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 4597 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 42222 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 93192 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2379 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 43994 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 4597 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 42222 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 93192 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 126107876 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 763949732 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 257885507 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 814738055 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 1962681170 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 276009 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 276009 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 714531723 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1069638349 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 1784170072 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 126107876 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 1478481455 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 257885507 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 1884376404 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 3746851242 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 126107876 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1478481455 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 257885507 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 1884376404 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 3746851242 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269571500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 330624500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 600196000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 336395500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 405229500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 741625000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605967000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2.data 735854000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 1341821000 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018404 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.215812 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015319 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093648 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.026900 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.433556 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.203593 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.126245 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018404 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.283799 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015319 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.120108 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.039713 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018404 # 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average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34049.641315 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62101.622678 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 46695.021382 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33606.433946 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33606.433946 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.255752 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1693877946000 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::tsunami.ide 1.255752 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::tsunami.ide 4282592586 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 4282592586 # number of WriteReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 4291770584 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 4291770584 # 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miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103065.859309 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 103065.859309 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency system.iocache.demand_avg_miss_latency::total 102858.492127 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency system.iocache.overall_avg_miss_latency::total 102858.492127 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 114365 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 10.414807 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3410139151 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 3410139151 # number of WriteReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 3415728400 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 3415728400 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 3415728400 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3415728400 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203371.848223 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 203371.848223 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.read_hits 4882466 # DTB read hits system.cpu0.dtb.read_misses 6004 # DTB read misses system.cpu0.dtb.read_acv 119 # DTB read access violations system.cpu0.dtb.read_accesses 427336 # DTB read accesses system.cpu0.dtb.write_hits 3509197 # DTB write hits system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations system.cpu0.dtb.write_accesses 162892 # DTB write accesses system.cpu0.dtb.data_hits 8391663 # DTB hits system.cpu0.dtb.data_misses 6665 # DTB misses system.cpu0.dtb.data_acv 201 # DTB access violations system.cpu0.dtb.data_accesses 590228 # DTB accesses system.cpu0.itb.fetch_hits 2746663 # ITB hits system.cpu0.itb.fetch_misses 2999 # ITB misses system.cpu0.itb.fetch_acv 99 # ITB acv system.cpu0.itb.fetch_accesses 2749662 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.numCycles 928532780 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 33005928 # Number of instructions committed system.cpu0.committedOps 33005928 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 30880412 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 168592 # Number of float alu accesses system.cpu0.num_func_calls 809679 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 4456286 # number of instructions that are conditional controls system.cpu0.num_int_insts 30880412 # number of integer instructions system.cpu0.num_fp_insts 168592 # number of float instructions system.cpu0.num_int_register_reads 43182890 # number of times the integer registers were read system.cpu0.num_int_register_writes 22546428 # number of times the integer registers were written system.cpu0.num_fp_register_reads 87049 # number of times the floating registers were read system.cpu0.num_fp_register_writes 88627 # number of times the floating registers were written system.cpu0.num_mem_refs 8421419 # number of memory refs system.cpu0.num_load_insts 4903545 # Number of load instructions system.cpu0.num_store_insts 3517874 # Number of store instructions system.cpu0.num_idle_cycles 214028071508.499786 # Number of idle cycles system.cpu0.num_busy_cycles -213099538728.499786 # Number of busy cycles system.cpu0.not_idle_fraction -229.501363 # Percentage of non-idle cycles system.cpu0.idle_fraction 230.501363 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks::0 1818570193000 98.74% 98.74% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 39079500 0.00% 98.75% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 22747610500 1.24% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1841721945500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 326 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 192207 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 29799200000 1.62% 1.62% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 2569954000 0.14% 1.76% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 1809352787000 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.icache.replacements 952928 # number of replacements system.cpu0.icache.tagsinuse 511.202677 # Cycle average of tags in use system.cpu0.icache.total_refs 42504111 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 953439 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 44.579791 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 252.529954 # Average occupied blocks per requestor system.cpu0.icache.occ_blocks::cpu1.inst 82.679092 # Average occupied blocks per requestor system.cpu0.icache.occ_blocks::cpu2.inst 175.993631 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.493223 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::cpu1.inst 0.161483 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::cpu2.inst 0.343738 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32488547 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 7734067 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2281497 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 42504111 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 32488547 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 7734067 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 2281497 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 42504111 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 32488547 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 7734067 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 2281497 # number of overall hits system.cpu0.icache.overall_hits::total 42504111 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 524247 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 129266 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 316688 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 970201 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 524247 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 129266 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu2.inst 316688 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 970201 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 524247 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 129266 # number of overall misses system.cpu0.icache.overall_misses::cpu2.inst 316688 # number of overall misses system.cpu0.icache.overall_misses::total 970201 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820027500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4433734984 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 6253762484 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 1820027500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu2.inst 4433734984 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 6253762484 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 1820027500 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 4433734984 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 6253762484 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 33012794 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863333 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 2598185 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 43474312 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 33012794 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 7863333 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 2598185 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 43474312 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 33012794 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 7863333 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 2598185 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 43474312 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015880 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016439 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121888 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015880 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016439 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121888 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015880 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016439 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121888 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14079.707734 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14000.325191 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 6445.842134 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 6445.842134 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 6445.842134 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 6047 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 177 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.163842 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16592 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 16592 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu2.inst 16592 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 16592 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu2.inst 16592 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 16592 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129266 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 300096 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 429362 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 129266 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::cpu2.inst 300096 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 429362 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 129266 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu2.inst 300096 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 429362 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1561495500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3655561484 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 5217056984 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1561495500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3655561484 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 5217056984 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1561495500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3655561484 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 5217056984 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.009876 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.009876 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.718936 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1392518 # number of replacements system.cpu0.dcache.tagsinuse 511.997811 # Cycle average of tags in use system.cpu0.dcache.total_refs 13324693 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 1393030 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 9.565259 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::cpu0.data 242.082942 # Average occupied blocks per requestor system.cpu0.dcache.occ_blocks::cpu1.data 91.912647 # Average occupied blocks per requestor system.cpu0.dcache.occ_blocks::cpu2.data 178.002223 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.472818 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu1.data 0.179517 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu2.data 0.347661 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 4059783 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1097740 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 2407711 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7565234 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3212644 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 860147 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 1303129 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5375920 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116773 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19259 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48170 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 184202 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125878 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21341 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52053 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199272 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 7272427 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 1957887 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 3710840 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12941154 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 7272427 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 1957887 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 3710840 # number of overall hits system.cpu0.dcache.overall_hits::total 12941154 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 707193 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 104402 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 546003 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1357598 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 169666 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 48403 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu2.data 557126 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 775195 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9666 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2214 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6955 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 18835 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 876859 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 152805 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu2.data 1103129 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2132793 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 876859 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 152805 # number of overall misses system.cpu0.dcache.overall_misses::cpu2.data 1103129 # number of overall misses system.cpu0.dcache.overall_misses::total 2132793 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2177012500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9421187500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 11598200000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393651000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14650982812 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 16044633812 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29146500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103568500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 132715000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 3570663500 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu2.data 24072170312 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 27642833812 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 3570663500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 24072170312 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 27642833812 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 4766976 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202142 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 2953714 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8922832 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3382310 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 908550 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 1860255 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6151115 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126439 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21473 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55125 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 203037 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125878 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21341 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52054 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199273 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 8149286 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 2110692 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 4813969 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 15073947 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 8149286 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 2110692 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 4813969 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 15073947 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148353 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086847 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184853 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.152149 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050163 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053275 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.299489 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.126025 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103106 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.126168 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092766 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107599 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072396 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229152 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.141489 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107599 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072396 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229152 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.141489 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20852.210686 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17254.827354 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 8543.176993 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28792.657480 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26297.431482 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 20697.545536 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13164.634146 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14891.229331 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7046.190603 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 12960.861092 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 12960.861092 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 423654 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 2998 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 16794 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.226509 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 428.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 836151 # number of writebacks system.cpu0.dcache.writebacks::total 836151 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 284315 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 284315 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 472764 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 472764 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1457 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu2.data 757079 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 757079 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu2.data 757079 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 757079 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104402 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261688 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 366090 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48403 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84362 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 132765 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2214 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5498 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7712 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 152805 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu2.data 346050 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 498855 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 152805 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 346050 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 498855 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1968208500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4300121500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6268330000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1296845000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131428631 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3428273631 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24718500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69834500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94553000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3265053500 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6431550131 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 9696603631 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3265053500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6431550131 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9696603631 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287785000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353197500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 640982500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356424500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.read_hits 1221293 # DTB read hits system.cpu1.dtb.read_misses 1489 # DTB read misses system.cpu1.dtb.read_acv 40 # DTB read access violations system.cpu1.dtb.read_accesses 143781 # DTB read accesses system.cpu1.dtb.write_hits 930282 # DTB write hits system.cpu1.dtb.write_misses 202 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 59266 # DTB write accesses system.cpu1.dtb.data_hits 2151575 # DTB hits system.cpu1.dtb.data_misses 1691 # DTB misses system.cpu1.dtb.data_acv 64 # DTB access violations system.cpu1.dtb.data_accesses 203047 # DTB accesses system.cpu1.itb.fetch_hits 872259 # ITB hits system.cpu1.itb.fetch_misses 756 # ITB misses system.cpu1.itb.fetch_acv 43 # ITB acv system.cpu1.itb.fetch_accesses 873015 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numCycles 953618286 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 7861577 # Number of instructions committed system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses system.cpu1.num_func_calls 212083 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls system.cpu1.num_int_insts 7312995 # number of integer instructions system.cpu1.num_fp_insts 45507 # number of float instructions system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written system.cpu1.num_mem_refs 2159267 # number of memory refs system.cpu1.num_load_insts 1226545 # Number of load instructions system.cpu1.num_store_insts 932722 # Number of store instructions system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu1.kern.mode_switch::user 0 # number of protection mode switches system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches system.cpu1.kern.mode_good::kernel 0 system.cpu1.kern.mode_good::user 0 system.cpu1.kern.mode_good::idle 0 system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed system.cpu2.branchPred.lookups 8378030 # Number of BP lookups system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses system.cpu2.dtb.read_hits 3213070 # DTB read hits system.cpu2.dtb.read_misses 11858 # DTB read misses system.cpu2.dtb.read_acv 125 # DTB read access violations system.cpu2.dtb.read_accesses 216838 # DTB read accesses system.cpu2.dtb.write_hits 1985729 # DTB write hits system.cpu2.dtb.write_misses 2626 # DTB write misses system.cpu2.dtb.write_acv 132 # DTB write access violations system.cpu2.dtb.write_accesses 82100 # DTB write accesses system.cpu2.dtb.data_hits 5198799 # DTB hits system.cpu2.dtb.data_misses 14484 # DTB misses system.cpu2.dtb.data_acv 257 # DTB access violations system.cpu2.dtb.data_accesses 298938 # DTB accesses system.cpu2.itb.fetch_hits 371799 # ITB hits system.cpu2.itb.fetch_misses 5527 # ITB misses system.cpu2.itb.fetch_acv 268 # ITB acv system.cpu2.itb.fetch_accesses 377326 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.write_acv 0 # DTB write access violations system.cpu2.itb.write_accesses 0 # DTB write accesses system.cpu2.itb.data_hits 0 # DTB hits system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.numCycles 30456501 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit. system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit. system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads. system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores. system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued system.cpu2.iq.rate 0.994264 # Inst issue rate system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst) system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 1279986 # number of nop insts executed system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed system.cpu2.iew.exec_branches 6791959 # Number of branches executed system.cpu2.iew.exec_stores 1992832 # Number of stores executed system.cpu2.iew.exec_rate 0.989003 # Inst execution rate system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back system.cpu2.iew.wb_producers 17325737 # num instructions producing a value system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle system.cpu2.commit.committedInsts 30241196 # Number of instructions committed system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.refs 4874767 # Number of memory references committed system.cpu2.commit.loads 2959021 # Number of loads committed system.cpu2.commit.membars 64729 # Number of memory barriers committed system.cpu2.commit.branches 6642526 # Number of branches committed system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions. system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions. system.cpu2.commit.function_calls 230913 # Number of function calls committed. system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu2.rob.rob_reads 58235962 # The number of ROB reads system.cpu2.rob.rob_writes 65598028 # The number of ROB writes system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 29069459 # Number of Instructions Simulated system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu2.kern.mode_switch::user 0 # number of protection mode switches system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches system.cpu2.kern.mode_good::kernel 0 system.cpu2.kern.mode_good::user 0 system.cpu2.kern.mode_good::idle 0 system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu2.kern.swap_context 0 # number of times the context was actually changed ---------- End Simulation Statistics ----------