---------- Begin Simulation Statistics ---------- sim_seconds 1.842592 # Number of seconds simulated sim_ticks 1842591955000 # Number of ticks simulated final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 212167 # Simulator instruction rate (inst/s) host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) host_tick_rate 5858461865 # Simulator tick rate (ticks/s) host_mem_usage 373744 # Number of bytes of host memory used host_seconds 314.52 # Real time elapsed on the host sim_insts 66730424 # Number of instructions simulated sim_ops 66730424 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 81945 # Number of read requests accepted system.physmem.writeReqs 62218 # Number of write requests accepted system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 5216 # Per bank write bursts system.physmem.perBankRdBursts::1 4952 # Per bank write bursts system.physmem.perBankRdBursts::2 4966 # Per bank write bursts system.physmem.perBankRdBursts::3 5032 # Per bank write bursts system.physmem.perBankRdBursts::4 5011 # Per bank write bursts system.physmem.perBankRdBursts::5 5077 # Per bank write bursts system.physmem.perBankRdBursts::6 5139 # Per bank write bursts system.physmem.perBankRdBursts::7 5153 # Per bank write bursts system.physmem.perBankRdBursts::8 5336 # Per bank write bursts system.physmem.perBankRdBursts::9 5012 # Per bank write bursts system.physmem.perBankRdBursts::10 5284 # Per bank write bursts system.physmem.perBankRdBursts::11 5137 # Per bank write bursts system.physmem.perBankRdBursts::12 4814 # Per bank write bursts system.physmem.perBankRdBursts::13 5083 # Per bank write bursts system.physmem.perBankRdBursts::14 5582 # Per bank write bursts system.physmem.perBankRdBursts::15 5130 # Per bank write bursts system.physmem.perBankWrBursts::0 3820 # Per bank write bursts system.physmem.perBankWrBursts::1 3672 # Per bank write bursts system.physmem.perBankWrBursts::2 3762 # Per bank write bursts system.physmem.perBankWrBursts::3 4075 # Per bank write bursts system.physmem.perBankWrBursts::4 3759 # Per bank write bursts system.physmem.perBankWrBursts::5 3520 # Per bank write bursts system.physmem.perBankWrBursts::6 4123 # Per bank write bursts system.physmem.perBankWrBursts::7 3706 # Per bank write bursts system.physmem.perBankWrBursts::8 4379 # Per bank write bursts system.physmem.perBankWrBursts::9 3471 # Per bank write bursts system.physmem.perBankWrBursts::10 3889 # Per bank write bursts system.physmem.perBankWrBursts::11 3981 # Per bank write bursts system.physmem.perBankWrBursts::12 3541 # Per bank write bursts system.physmem.perBankWrBursts::13 3879 # Per bank write bursts system.physmem.perBankWrBursts::14 4169 # Per bank write bursts system.physmem.perBankWrBursts::15 3676 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 1841579678500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 81945 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 62218 # Write request sizes (log2) system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4691 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 3896 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3337 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 3243 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 2582 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2407 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 2265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads system.physmem.totQLat 814366500 # Total ticks spent queuing system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing system.physmem.readRowHits 70260 # Number of row buffer hits during reads system.physmem.writeRowHits 50807 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes system.physmem.avgGap 12774287.98 # Average gap between requests system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) system.physmem_0.averagePower 667.726630 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) system.physmem_1.averagePower 667.972279 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.read_hits 4841130 # DTB read hits system.cpu0.dtb.read_misses 6162 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429577 # DTB read accesses system.cpu0.dtb.write_hits 3448228 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 85 # DTB write access violations system.cpu0.dtb.write_accesses 165228 # DTB write accesses system.cpu0.dtb.data_hits 8289358 # DTB hits system.cpu0.dtb.data_misses 6850 # DTB misses system.cpu0.dtb.data_acv 211 # DTB access violations system.cpu0.dtb.data_accesses 594805 # DTB accesses system.cpu0.itb.fetch_hits 2744473 # ITB hits system.cpu0.itb.fetch_misses 3071 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv system.cpu0.itb.fetch_accesses 2747544 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.numCycles 929111283 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 30392058 # Number of instructions committed system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses system.cpu0.num_func_calls 800920 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls system.cpu0.num_int_insts 28296981 # number of integer instructions system.cpu0.num_fp_insts 165313 # number of float instructions system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written system.cpu0.num_mem_refs 8319320 # number of memory refs system.cpu0.num_load_insts 4862427 # Number of load instructions system.cpu0.num_store_insts 3456893 # Number of store instructions system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles system.cpu0.Branches 4712544 # Number of branches fetched system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 30399119 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 326 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 192228 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1910 system.cpu0.kern.mode_good::user 1740 system.cpu0.kern.mode_good::idle 170 system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.cpu0.dcache.tags.replacements 1393017 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 184484 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123743 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20765 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54820 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 7171355 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 1861632 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 3864582 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12897569 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 7171355 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 1861632 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 3864582 # number of overall hits system.cpu0.dcache.overall_hits::total 12897569 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 713110 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 94552 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 558128 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1365790 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 166356 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 43595 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu2.data 617033 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 826984 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9412 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2104 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7556 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 19072 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 879466 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 138147 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu2.data 1175161 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2192774 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 879466 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 138147 # number of overall misses system.cpu0.dcache.overall_misses::cpu2.data 1175161 # number of overall misses system.cpu0.dcache.overall_misses::total 2192774 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193347250 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9664547340 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 11857894590 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1652894510 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19391335975 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 21044230485 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27729500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125483249 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 153212749 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 91000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 3846241760 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu2.data 29055883315 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 32902125075 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 3846241760 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 29055883315 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 32902125075 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727619 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147984 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 3064749 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8940352 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3323202 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 851795 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974994 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6149991 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124292 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20895 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58369 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 203556 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123745 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20765 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54827 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199337 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks system.cpu0.dcache.writebacks::total 835667 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292188 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 292188 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524505 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 524505 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1570 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1570 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu2.data 816693 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 816693 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu2.data 816693 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 816693 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94552 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 265940 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 360492 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43595 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92528 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 136123 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2104 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5986 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8090 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 138147 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu2.data 358468 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 496615 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 138147 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 358468 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 496615 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1996702750 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4449426882 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6446129632 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1557368490 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2781486410 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4338854900 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23520500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72740751 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96261251 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 77000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554071240 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7230913292 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 10784984532 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554071240 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7230913292 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1331768500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082364 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086774 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040322 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051180 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046850 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022134 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100694 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102554 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039743 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000128 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.032909 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 964323 # number of replacements system.cpu0.icache.tags.tagsinuse 511.193139 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 39678129 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 964834 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 41.124306 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10191163250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.937948 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.959779 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu2.inst 181.295411 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.515504 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128828 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.354093 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998424 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 41624427 # Number of tag accesses system.cpu0.icache.tags.data_accesses 41624427 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 29884884 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 7331949 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2461296 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 39678129 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29884884 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 7331949 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 2461296 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 39678129 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 29884884 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 7331949 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 2461296 # number of overall hits system.cpu0.icache.overall_hits::total 39678129 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 514235 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 124188 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 342842 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 981265 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 514235 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 124188 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu2.inst 342842 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 981265 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 514235 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 124188 # number of overall misses system.cpu0.icache.overall_misses::cpu2.inst 342842 # number of overall misses system.cpu0.icache.overall_misses::total 981265 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1771676000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4819389197 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 6591065197 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 1771676000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu2.inst 4819389197 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 6591065197 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 1771676000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 4819389197 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 6591065197 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 30399119 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 7456137 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 2804138 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 40659394 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 30399119 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 7456137 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 2804138 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 40659394 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 30399119 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 7456137 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 2804138 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 40659394 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016916 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016656 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122263 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.024134 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016916 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016656 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122263 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.024134 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016916 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016656 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122263 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.024134 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.080459 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14057.172683 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 6716.906439 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 6716.906439 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 6716.906439 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 2709 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.read_hits 1166781 # DTB read hits system.cpu1.dtb.read_misses 1314 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 141633 # DTB read accesses system.cpu1.dtb.write_hits 872888 # DTB write hits system.cpu1.dtb.write_misses 168 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 57088 # DTB write accesses system.cpu1.dtb.data_hits 2039669 # DTB hits system.cpu1.dtb.data_misses 1482 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations system.cpu1.dtb.data_accesses 198721 # DTB accesses system.cpu1.itb.fetch_hits 848090 # ITB hits system.cpu1.itb.fetch_misses 662 # ITB misses system.cpu1.itb.fetch_acv 32 # ITB acv system.cpu1.itb.fetch_accesses 848752 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numCycles 953408444 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 7454598 # Number of instructions committed system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses system.cpu1.num_func_calls 203515 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls system.cpu1.num_int_insts 6929268 # number of integer instructions system.cpu1.num_fp_insts 43953 # number of float instructions system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written system.cpu1.num_mem_refs 2046592 # number of memory refs system.cpu1.num_load_insts 1171450 # Number of load instructions system.cpu1.num_store_insts 875142 # Number of store instructions system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles system.cpu1.Branches 1171881 # Number of branches fetched system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 7456136 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu1.kern.mode_switch::user 0 # number of protection mode switches system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches system.cpu1.kern.mode_good::kernel 0 system.cpu1.kern.mode_good::user 0 system.cpu1.kern.mode_good::idle 0 system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed system.cpu2.branchPred.lookups 9673449 # Number of BP lookups system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses system.cpu2.dtb.read_hits 3461968 # DTB read hits system.cpu2.dtb.read_misses 12174 # DTB read misses system.cpu2.dtb.read_acv 114 # DTB read access violations system.cpu2.dtb.read_accesses 224881 # DTB read accesses system.cpu2.dtb.write_hits 2122047 # DTB write hits system.cpu2.dtb.write_misses 2563 # DTB write misses system.cpu2.dtb.write_acv 106 # DTB write access violations system.cpu2.dtb.write_accesses 83942 # DTB write accesses system.cpu2.dtb.data_hits 5584015 # DTB hits system.cpu2.dtb.data_misses 14737 # DTB misses system.cpu2.dtb.data_acv 220 # DTB access violations system.cpu2.dtb.data_accesses 308823 # DTB accesses system.cpu2.itb.fetch_hits 534012 # ITB hits system.cpu2.itb.fetch_misses 5788 # ITB misses system.cpu2.itb.fetch_acv 158 # ITB acv system.cpu2.itb.fetch_accesses 539800 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.write_acv 0 # DTB write access violations system.cpu2.itb.write_accesses 0 # DTB write accesses system.cpu2.itb.data_hits 0 # DTB hits system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.numCycles 30013580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued system.cpu2.iq.rate 1.012645 # Inst issue rate system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 1379854 # number of nop insts executed system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed system.cpu2.iew.exec_branches 6643679 # Number of branches executed system.cpu2.iew.exec_stores 2129239 # Number of stores executed system.cpu2.iew.exec_rate 1.006060 # Inst execution rate system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back system.cpu2.iew.wb_producers 17254819 # num instructions producing a value system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle system.cpu2.commit.committedInsts 30096794 # Number of instructions committed system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.refs 5086249 # Number of memory references committed system.cpu2.commit.loads 3053005 # Number of loads committed system.cpu2.commit.membars 67981 # Number of memory barriers committed system.cpu2.commit.branches 6474041 # Number of branches committed system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. system.cpu2.commit.function_calls 239427 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu2.rob.rob_reads 59838509 # The number of ROB reads system.cpu2.rob.rob_writes 65974697 # The number of ROB writes system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 28883768 # Number of Instructions Simulated system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution system.iobus.trans_dist::WriteReq 51363 # Transaction distribution system.iobus.trans_dist::WriteResp 9811 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 337565 # number of replacements system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.033507 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.998245 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 5954 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 2697 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 55331 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 26259538 # Number of tag accesses system.l2c.tags.data_accesses 26259538 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 506712 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 484023 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 121893 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 79858 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 321963 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 253653 # number of ReadReq hits system.l2c.ReadReq_hits::total 1768102 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 835667 # number of Writeback hits system.l2c.Writeback_hits::total 835667 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 7 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 90939 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 25234 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2.data 70756 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 186929 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 506712 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 574962 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 121893 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 105092 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 321963 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 324409 # number of demand (read+write) hits system.l2c.demand_hits::total 1955031 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 506712 # number of overall hits system.l2c.overall_hits::cpu0.data 574962 # number of overall hits system.l2c.overall_hits::cpu1.inst 121893 # number of overall hits system.l2c.overall_hits::cpu1.data 105092 # number of overall hits system.l2c.overall_hits::cpu2.inst 321963 # number of overall hits system.l2c.overall_hits::cpu2.data 324409 # number of overall hits system.l2c.overall_hits::total 1955031 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 7503 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 238499 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 2295 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 16798 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 4594 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 17926 # number of ReadReq misses system.l2c.ReadReq_misses::total 287615 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 29 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 37 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 75406 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 18360 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 22084 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 115850 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 7503 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 313905 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2295 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 35158 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 4594 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 40010 # number of demand (read+write) misses system.l2c.demand_misses::total 403465 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 7503 # number of overall misses system.l2c.overall_misses::cpu0.data 313905 # number of overall misses system.l2c.overall_misses::cpu1.inst 2295 # number of overall misses system.l2c.overall_misses::cpu1.data 35158 # number of overall misses system.l2c.overall_misses::cpu2.inst 4594 # number of overall misses system.l2c.overall_misses::cpu2.data 40010 # number of overall misses system.l2c.overall_misses::total 403465 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.inst 172333500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 1121869750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 347709750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 1196370250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 2838283250 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 294497 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 294497 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1260800990 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1814777221 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 3075578211 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.inst 172333500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 2382670740 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 347709750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 3011147471 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 5913861461 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.inst 172333500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 2382670740 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 347709750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 3011147471 # number of overall miss cycles system.l2c.overall_miss_latency::total 5913861461 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 514215 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 722522 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 124188 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 96656 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 326557 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 271579 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2055717 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 835667 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 835667 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 36 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 166345 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 43594 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 92840 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 302779 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 514215 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 888867 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 124188 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 140250 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 326557 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 364419 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2358496 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 514215 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 888867 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 124188 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 140250 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 326557 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 364419 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2358496 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.014591 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.330092 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.018480 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.173792 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.014068 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.066007 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.139910 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 0.805556 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.770833 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.222222 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.453311 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.421159 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 0.237872 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.382622 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.014591 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.353152 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.018480 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.250681 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.014068 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.109791 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.171069 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.014591 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.353152 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.018480 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.250681 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.014068 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.109791 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.171069 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75090.849673 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 66785.912013 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75687.799303 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 66739.386924 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 9868.342228 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10155.068966 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 7959.378378 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68671.077887 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82176.110351 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 26547.934493 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency system.l2c.demand_avg_miss_latency::total 14657.681487 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency system.l2c.overall_avg_miss_latency::total 14657.681487 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 75393 # number of writebacks system.l2c.writebacks::total 75393 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu1.inst 2295 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 16798 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.inst 4594 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 17926 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 41613 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 29 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 18360 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 22084 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 40444 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2295 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 35158 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 4594 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 40010 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 82057 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2295 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 35158 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 4594 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 40010 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 82057 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143128000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 911545250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 289854250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 972645250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 2317172750 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 449026 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 449026 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1030142510 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1544955279 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 2575097789 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 143128000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 1941687760 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 289854250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 2517600529 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 4892270539 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 143128000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1941687760 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 289854250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 2517600529 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 4892270539 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 233455500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320261000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 553716500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302243500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395601500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 697845000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535699000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2.data 715862500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 1251561500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173792 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066007 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.020243 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.805556 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.604167 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421159 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237872 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.133576 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.034792 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.034792 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54265.105965 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54258.911637 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 55683.866820 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 15483.655172 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 15483.655172 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56107.979847 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69958.127106 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 63670.699955 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 294932 # Transaction distribution system.membus.trans_dist::ReadResp 294926 # Transaction distribution system.membus.trans_dist::WriteReq 9811 # Transaction distribution system.membus.trans_dist::WriteResp 9811 # Transaction distribution system.membus.trans_dist::Writeback 116905 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 163 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 165 # Transaction distribution system.membus.trans_dist::ReadExReq 115724 # Transaction distribution system.membus.trans_dist::ReadExResp 115724 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 140 # Total snoops (count) system.membus.snoop_fanout::samples 562134 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 562134 # Request fanout histogram system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu2.kern.mode_switch::user 0 # number of protection mode switches system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches system.cpu2.kern.mode_good::kernel 0 system.cpu2.kern.mode_good::user 0 system.cpu2.kern.mode_good::idle 0 system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu2.kern.swap_context 0 # number of times the context was actually changed ---------- End Simulation Statistics ----------