---------- Begin Simulation Statistics ---------- sim_seconds 2.844427 # Number of seconds simulated sim_ticks 2844427140500 # Number of ticks simulated final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 150296 # Simulator instruction rate (inst/s) host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) host_tick_rate 3416553864 # Simulator tick rate (ticks/s) host_mem_usage 612172 # Number of bytes of host memory used host_seconds 832.54 # Real time elapsed on the host sim_insts 125127935 # Number of instructions simulated sim_ops 151499394 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 216517 # Number of read requests accepted system.physmem.writeReqs 187602 # Number of write requests accepted system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 13513 # Per bank write bursts system.physmem.perBankRdBursts::1 13311 # Per bank write bursts system.physmem.perBankRdBursts::2 14548 # Per bank write bursts system.physmem.perBankRdBursts::3 14027 # Per bank write bursts system.physmem.perBankRdBursts::4 15548 # Per bank write bursts system.physmem.perBankRdBursts::5 13123 # Per bank write bursts system.physmem.perBankRdBursts::6 13508 # Per bank write bursts system.physmem.perBankRdBursts::7 14039 # Per bank write bursts system.physmem.perBankRdBursts::8 13183 # Per bank write bursts system.physmem.perBankRdBursts::9 13181 # Per bank write bursts system.physmem.perBankRdBursts::10 13142 # Per bank write bursts system.physmem.perBankRdBursts::11 11743 # Per bank write bursts system.physmem.perBankRdBursts::12 13238 # Per bank write bursts system.physmem.perBankRdBursts::13 14181 # Per bank write bursts system.physmem.perBankRdBursts::14 13272 # Per bank write bursts system.physmem.perBankRdBursts::15 12799 # Per bank write bursts system.physmem.perBankWrBursts::0 11429 # Per bank write bursts system.physmem.perBankWrBursts::1 11725 # Per bank write bursts system.physmem.perBankWrBursts::2 12190 # Per bank write bursts system.physmem.perBankWrBursts::3 11854 # Per bank write bursts system.physmem.perBankWrBursts::4 10909 # Per bank write bursts system.physmem.perBankWrBursts::5 11199 # Per bank write bursts system.physmem.perBankWrBursts::6 11528 # Per bank write bursts system.physmem.perBankWrBursts::7 11643 # Per bank write bursts system.physmem.perBankWrBursts::8 11026 # Per bank write bursts system.physmem.perBankWrBursts::9 11436 # Per bank write bursts system.physmem.perBankWrBursts::10 11468 # Per bank write bursts system.physmem.perBankWrBursts::11 11022 # Per bank write bursts system.physmem.perBankWrBursts::12 11525 # Per bank write bursts system.physmem.perBankWrBursts::13 11398 # Per bank write bursts system.physmem.perBankWrBursts::14 10974 # Per bank write bursts system.physmem.perBankWrBursts::15 10595 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 2844424796500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 215930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 183166 # Write request sizes (log2) system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads system.physmem.totQLat 7644398000 # Total ticks spent queuing system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing system.physmem.readRowHits 183280 # Number of row buffer hits during reads system.physmem.writeRowHits 121675 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes system.physmem.avgGap 7038582.19 # Average gap between requests system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states system.physmem.memoryStateTime::REF 94981640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) system.physmem.averagePower::0 669.577359 # Core power per rank (mW) system.physmem.averagePower::1 669.493163 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu0.branchPred.lookups 35736686 # Number of BP lookups system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 24607000 # DTB read hits system.cpu0.dtb.read_misses 66402 # DTB read misses system.cpu0.dtb.write_hits 18455953 # DTB write hits system.cpu0.dtb.write_misses 6655 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 24673402 # DTB read accesses system.cpu0.dtb.write_accesses 18462608 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 43062953 # DTB hits system.cpu0.dtb.misses 73057 # DTB misses system.cpu0.dtb.accesses 43136010 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.inst_hits 71661808 # ITB inst hits system.cpu0.itb.inst_misses 4142 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses system.cpu0.itb.hits 71661808 # DTB hits system.cpu0.itb.misses 4142 # DTB misses system.cpu0.itb.accesses 71665950 # DTB accesses system.cpu0.numCycles 235973632 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 111703770 # Number of instructions committed system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.cpi 2.112495 # CPI: cycles per instruction system.cpu0.ipc 0.473374 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped system.cpu0.dcache.tags.replacements 751860 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 41859398 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023568 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.023568 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030988 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.030988 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016733 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016733 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051900 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051900 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026740 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026740 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026740 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026740 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks system.cpu0.dcache.writebacks::total 541643 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # number of WriteReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.inst 285916 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 285916 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.inst 285916 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 285916 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 519803 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 519803 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 313587 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 313587 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6644 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6644 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20340 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 20340 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.inst 833390 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 833390 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.inst 833390 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 833390 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5323715430 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5323715430 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4366940170 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4366940170 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94806000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94806000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 398879017 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 2070442 # number of replacements system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 145377375 # Number of tag accesses system.cpu0.icache.tags.data_accesses 145377375 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 69582233 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 69582233 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 69582233 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 69582233 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 69582233 # number of overall hits system.cpu0.icache.overall_hits::total 69582233 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 2070970 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 2070970 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 2070970 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 2070970 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 2070970 # number of overall misses system.cpu0.icache.overall_misses::total 2070970 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17258012980 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 17258012980 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 17258012980 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 17258012980 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 17258012980 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 17258012980 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 71653203 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276493750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276493750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276493750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 276493750 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028903 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.028903 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.028903 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l2cache.tags.replacements 428439 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.133518 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594950 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.989518 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8981 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7254 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 111 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2870 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5529 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3049 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3651 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 230 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.548157 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.442749 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 57799798 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 57799798 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 84149 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4243 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2500411 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 2588803 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 541643 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 541643 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4674 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 4674 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2411 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 2411 # number of SCUpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 234433 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 234433 # number of ReadExReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 84149 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4243 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 2734844 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 2823236 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 84149 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4243 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 2734844 # number of overall hits system.cpu0.l2cache.overall_hits::total 2823236 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 906 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.inst 97001 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 98045 # number of ReadReq misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27960 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 27960 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17929 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 17929 # number of SCUpgradeReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46525 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 46525 # number of ReadExReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 906 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.inst 143526 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 144570 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 906 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.inst 143526 # number of overall misses system.cpu0.l2cache.overall_misses::total 144570 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31530500 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3231999 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2954004148 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 2988766647 # number of ReadReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497244183 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 497244183 # number of UpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 356127296 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356127296 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 112000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 112000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1936152477 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 1936152477 # number of ReadExReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31530500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3231999 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4890156625 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 4924919124 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31530500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3231999 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4890156625 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 4924919124 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 85055 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4381 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2597412 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 2686848 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 541643 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 541643 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32634 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 32634 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20340 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 20340 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 280958 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 280958 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 85055 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4381 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 2878370 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 2967806 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 85055 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4381 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 2878370 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 2967806 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031500 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037345 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.036491 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856775 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856775 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.881465 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.881465 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.165594 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.165594 # miss rate for ReadExReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031500 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.049864 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.048713 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031500 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.049864 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.048713 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266 # average ReadReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717 # average UpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853 # average ReadExReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 25119 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 346 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 72.598266 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 220063 # number of writebacks system.cpu0.l2cache.writebacks::total 220063 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8315 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 8315 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3034 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 3034 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11349 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 11349 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11349 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 11349 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 906 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 88686 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 89730 # number of ReadReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 534906 # number of HardPFReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27960 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27960 # number of UpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17929 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17929 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43491 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 43491 # number of ReadExReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 906 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 132177 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 133221 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 906 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 132177 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 668127 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2265999 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2160848492 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2188282991 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21648732719 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 481473058 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481473058 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 238593946 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 238593946 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 91000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 91000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1198815233 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1198815233 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2265999 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3359663725 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 3387098224 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2265999 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3359663725 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 25035830943 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6180670251 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6180670251 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4594924508 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4594924508 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10775594759 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10775594759 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034144 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.033396 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 3448752 # Number of BP lookups system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 3432223 # DTB read hits system.cpu1.dtb.read_misses 19764 # DTB read misses system.cpu1.dtb.write_hits 2826731 # DTB write hits system.cpu1.dtb.write_misses 1392 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 3451987 # DTB read accesses system.cpu1.dtb.write_accesses 2828123 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 6258954 # DTB hits system.cpu1.dtb.misses 21156 # DTB misses system.cpu1.dtb.accesses 6280110 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.inst_hits 6653879 # ITB inst hits system.cpu1.itb.inst_misses 1856 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses system.cpu1.itb.hits 6653879 # DTB hits system.cpu1.itb.misses 1856 # DTB misses system.cpu1.itb.accesses 6655735 # DTB accesses system.cpu1.numCycles 36145472 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 13424165 # Number of instructions committed system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 2.692568 # CPI: cycles per instruction system.cpu1.ipc 0.371393 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped system.cpu1.dcache.tags.replacements 149765 # number of replacements system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses system.cpu1.dcache.overall_misses::total 268114 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 5422961673 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.inst 5422961673 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 5422961673 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3318543 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3318543 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.inst 2704080 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2704080 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 84949 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 84949 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 83328 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 83328 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks system.cpu1.dcache.writebacks::total 93707 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 39187 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 39187 # number of WriteReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.inst 50780 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 50780 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.inst 50780 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 50780 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 139568 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 139568 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 77766 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 77766 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5079 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 22818 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 22818 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.inst 217334 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 217334 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.inst 217334 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 217334 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 1914681986 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914681986 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1867013423 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1867013423 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83091000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83091000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 487833202 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 487833202 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 100500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 100500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 3781695409 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 3781695409 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 3781695409 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 3781695409 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 327471996 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 327471996 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 198424999 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 198424999 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 525896995 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 525896995 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042057 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042057 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028759 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028759 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.059789 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059789 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.273834 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273834 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.036086 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.036086 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 827152 # number of replacements system.cpu1.icache.tags.tagsinuse 499.447245 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 5824947 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 827664 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 7.037816 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 71343314500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.447245 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975483 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975483 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 469 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 14132886 # Number of tag accesses system.cpu1.icache.tags.data_accesses 14132886 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 5824947 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 5824947 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 5824947 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 5824947 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 5824947 # number of overall hits system.cpu1.icache.overall_hits::total 5824947 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 827664 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 827664 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 827664 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 827664 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 827664 # number of overall misses system.cpu1.icache.overall_misses::total 827664 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6712177482 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 6712177482 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 6712177482 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 6712177482 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 6712177482 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 6712177482 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 6652611 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 6652611 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 6652611 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 6652611 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 6652611 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 6652611 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124412 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.124412 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l2cache.tags.replacements 52740 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.393188 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 19285639 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 19285639 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22569 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2289 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.inst 905837 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 930695 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 93707 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 93707 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1549 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 1549 # number of UpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 533 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 533 # number of SCUpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 18299 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 18299 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22569 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2289 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 924136 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 948994 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22569 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2289 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 924136 # number of overall hits system.cpu1.l2cache.overall_hits::total 948994 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 245 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.inst 66474 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 67423 # number of ReadReq misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 27781 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 27781 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22285 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22285 # number of SCUpgradeReq misses system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 30137 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 30137 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 245 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.inst 96611 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 97560 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 245 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.inst 96611 # number of overall misses system.cpu1.l2cache.overall_misses::total 97560 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14471499 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4810998 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1464118881 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 1483401378 # number of ReadReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 523592810 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 523592810 # number of UpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 437167020 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 437167020 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 97500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 97500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1078871611 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 1078871611 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14471499 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4810998 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2542990492 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 2562272989 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14471499 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4810998 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2542990492 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 2562272989 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23273 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2534 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 972311 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 998118 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 93707 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 93707 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29330 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 29330 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 22818 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 22818 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 48436 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 48436 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23273 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2534 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 1020747 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 1046554 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23273 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2534 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 1020747 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 1046554 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.096685 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.068367 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.067550 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.947187 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947187 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.976641 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.976641 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.622202 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.622202 # miss rate for ReadExReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.096685 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094647 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.093220 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.096685 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094647 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.093220 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621 # average ReadReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365 # average ReadExReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 2801 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 79 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.455696 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 30368 # number of writebacks system.cpu1.l2cache.writebacks::total 30368 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 950 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 950 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 295 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1245 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1245 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 1245 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 704 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 245 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 65524 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 66473 # number of ReadReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 80004 # number of HardPFReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 27781 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27781 # number of UpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22285 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22285 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 29842 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 29842 # number of ReadExReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 704 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 245 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 95366 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 96315 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 704 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 245 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 95366 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 176319 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3095998 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 981688737 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 994327236 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2522312930 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 396174942 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 396174942 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306073762 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306073762 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 76500 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 76500 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 831450098 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 831450098 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3095998 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1813138835 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 1825777334 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3095998 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1813138835 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 4348090264 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 313994504 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 313994504 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 182561501 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 182561501 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 496556005 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 496556005 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.067390 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.066598 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31020 # Transaction distribution system.iobus.trans_dist::ReadResp 31020 # Transaction distribution system.iobus.trans_dist::WriteReq 59447 # Transaction distribution system.iobus.trans_dist::WriteResp 23223 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36433 # number of replacements system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328203 # Number of tag accesses system.iocache.tags.data_accesses 328203 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 150396 # number of replacements system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 6561930 # Number of tag accesses system.l2c.tags.data_accesses 6561930 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits system.l2c.Writeback_hits::total 250431 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 12263 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.inst 184 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.inst 192 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.inst 3646 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.inst 908 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 4554 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 576 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 131 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 43165 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 221242 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 94 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 7808 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 25945 # number of demand (read+write) hits system.l2c.demand_hits::total 298980 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 576 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 131 # number of overall hits system.l2c.overall_hits::cpu0.inst 43165 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 221242 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 94 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits system.l2c.overall_hits::cpu1.inst 7808 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 25945 # number of overall hits system.l2c.overall_hits::total 298980 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 161 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 11256 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 169617 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1341 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq misses system.l2c.ReadReq_misses::total 199885 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.inst 9580 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.inst 2241 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 11821 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.inst 527 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.inst 1214 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1741 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.inst 6969 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.inst 6429 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 13398 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 161 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 18225 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 169617 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7770 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) misses system.l2c.demand_misses::total 213283 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 161 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.inst 18225 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 169617 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu1.inst 7770 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 17501 # number of overall misses system.l2c.overall_misses::total 213283 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12824000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 957656246 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 597000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 113197750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 21264707667 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.inst 10249624 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.inst 2389898 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 12639522 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1315451 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1074955 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 2390406 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.inst 593841904 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.inst 477642745 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 1071484649 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 12824000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 1551498150 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 597000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 590840495 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 22336192316 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 12824000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 1551498150 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 597000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 590840495 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of overall miss cycles system.l2c.overall_miss_latency::total 22336192316 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 737 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 132 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 50775 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 390859 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 102 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 19 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 8241 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 43446 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 494311 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 250431 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 250431 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.inst 21362 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.inst 2722 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 24084 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.inst 711 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.inst 1406 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2117 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.inst 10615 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.inst 7337 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 17952 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 737 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 132 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 61390 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 390859 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 102 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 15578 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 43446 # number of demand (read+write) accesses system.l2c.demand_accesses::total 512263 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 737 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 132 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 61390 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 390859 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 102 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 15578 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 43446 # number of overall (read+write) accesses system.l2c.overall_accesses::total 512263 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007576 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.221684 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.162723 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.404371 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.448460 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.823292 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.490824 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.741210 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.863442 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.822390 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.inst 0.656524 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.inst 0.876244 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.746324 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.007576 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.296872 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.498780 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.416354 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.007576 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.296872 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.498780 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.416354 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74625 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 106384.709543 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1069.898121 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1066.442660 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 1069.243042 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2496.111954 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 885.465404 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 1373.007467 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 79973.477310 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency system.l2c.demand_avg_miss_latency::total 104725.610180 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency system.l2c.overall_avg_miss_latency::total 104725.610180 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 110752 # number of writebacks system.l2c.writebacks::total 110752 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 161 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 11256 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 1341 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 199884 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9580 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2241 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 11821 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 527 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1214 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1741 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.inst 6969 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.inst 6429 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 13398 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 161 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 18225 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 7770 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 213282 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 161 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 18225 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 7770 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 213282 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 817788246 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 500000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 96492250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 18800812917 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 97817994 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 22626723 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 120444717 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 5423023 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12163710 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 17586733 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 506879094 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396754755 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 903633849 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 1324667340 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 500000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 493247005 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 19704446766 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 1324667340 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 500000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 493247005 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 19704446766 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5522428749 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 260648000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 5783076749 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4102579499 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 146450000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4249029499 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9625008248 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 407098000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 10032106248 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.221684 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.162723 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.404369 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.416353 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.416353 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 238185 # Transaction distribution system.membus.trans_dist::ReadResp 238185 # Transaction distribution system.membus.trans_dist::WriteReq 30953 # Transaction distribution system.membus.trans_dist::WriteResp 30953 # Transaction distribution system.membus.trans_dist::Writeback 146942 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution system.membus.trans_dist::ReadExReq 30241 # Transaction distribution system.membus.trans_dist::ReadExResp 13298 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 122070 # Total snoops (count) system.membus.snoop_fanout::samples 531658 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 531658 # Request fanout histogram system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 287552 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ----------