---------- Begin Simulation Statistics ---------- sim_seconds 2.627261 # Number of seconds simulated sim_ticks 2627260787000 # Number of ticks simulated final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 73269 # Simulator instruction rate (inst/s) host_op_rate 88893 # Simulator op (including micro ops) rate (op/s) host_tick_rate 1598642516 # Simulator tick rate (ticks/s) host_mem_usage 609448 # Number of bytes of host memory used host_seconds 1643.43 # Real time elapsed on the host sim_insts 120413300 # Number of instructions simulated sim_ops 146090184 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1139008 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 1190376 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 8167488 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 326368 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 665684 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 594880 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 12087580 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 1139008 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 326368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1465376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8694784 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory system.physmem.bytes_written::total 8712348 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 20044 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 19120 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 127617 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 10422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 9295 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 191724 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 135856 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 140247 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 585 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 433534 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 453086 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 3108747 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 341 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 124224 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 253376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 226426 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 365 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4600830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 433534 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 124224 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 557758 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3309448 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6670 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3316134 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3309448 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 433534 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 459756 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 3108747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 341 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 124224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 253391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 226426 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7916964 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 191724 # Number of read requests accepted system.physmem.writeReqs 140247 # Number of write requests accepted system.physmem.readBursts 191724 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 140247 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 12260288 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue system.physmem.bytesWritten 8725248 # Total number of bytes written to DRAM system.physmem.bytesReadSys 12087580 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 8712348 # Total written bytes from the system interface side system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 50731 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11367 # Per bank write bursts system.physmem.perBankRdBursts::1 11306 # Per bank write bursts system.physmem.perBankRdBursts::2 12534 # Per bank write bursts system.physmem.perBankRdBursts::3 11925 # Per bank write bursts system.physmem.perBankRdBursts::4 14392 # Per bank write bursts system.physmem.perBankRdBursts::5 11995 # Per bank write bursts system.physmem.perBankRdBursts::6 12528 # Per bank write bursts system.physmem.perBankRdBursts::7 12413 # Per bank write bursts system.physmem.perBankRdBursts::8 12465 # Per bank write bursts system.physmem.perBankRdBursts::9 12343 # Per bank write bursts system.physmem.perBankRdBursts::10 12048 # Per bank write bursts system.physmem.perBankRdBursts::11 11291 # Per bank write bursts system.physmem.perBankRdBursts::12 11598 # Per bank write bursts system.physmem.perBankRdBursts::13 11714 # Per bank write bursts system.physmem.perBankRdBursts::14 10851 # Per bank write bursts system.physmem.perBankRdBursts::15 10797 # Per bank write bursts system.physmem.perBankWrBursts::0 8020 # Per bank write bursts system.physmem.perBankWrBursts::1 8176 # Per bank write bursts system.physmem.perBankWrBursts::2 9316 # Per bank write bursts system.physmem.perBankWrBursts::3 8567 # Per bank write bursts system.physmem.perBankWrBursts::4 8317 # Per bank write bursts system.physmem.perBankWrBursts::5 8617 # Per bank write bursts system.physmem.perBankWrBursts::6 9080 # Per bank write bursts system.physmem.perBankWrBursts::7 8981 # Per bank write bursts system.physmem.perBankWrBursts::8 9059 # Per bank write bursts system.physmem.perBankWrBursts::9 8883 # Per bank write bursts system.physmem.perBankWrBursts::10 8732 # Per bank write bursts system.physmem.perBankWrBursts::11 8494 # Per bank write bursts system.physmem.perBankWrBursts::12 8573 # Per bank write bursts system.physmem.perBankWrBursts::13 8275 # Per bank write bursts system.physmem.perBankWrBursts::14 7766 # Per bank write bursts system.physmem.perBankWrBursts::15 7476 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 6 # Number of times write queue was full causing retry system.physmem.totGap 2627260507500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 188059 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 135856 # Write request sizes (log2) system.physmem.rdQLenPdf::0 61031 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 73227 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12933 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10004 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8250 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7158 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 6223 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 5068 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 4443 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1296 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 829 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 578 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3122 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4091 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5940 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 7239 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 7402 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 8568 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 9044 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9358 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 10932 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 9335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 9345 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 10651 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 8993 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 8113 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 7579 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 660 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 427 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 86649 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 242.189431 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 136.582911 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 303.571271 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 46399 53.55% 53.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 16583 19.14% 72.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5986 6.91% 79.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3348 3.86% 83.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2763 3.19% 86.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1550 1.79% 88.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1005 1.16% 89.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 914 1.05% 90.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8101 9.35% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 86649 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6686 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.651211 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 549.102387 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 6684 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6686 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6686 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 20.390667 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 18.828394 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 12.276627 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 5432 81.24% 81.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 492 7.36% 88.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 97 1.45% 90.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 153 2.29% 92.34% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 34 0.51% 92.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 125 1.87% 94.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 42 0.63% 95.35% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 20 0.30% 95.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 24 0.36% 96.01% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 25 0.37% 96.38% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 6 0.09% 96.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 6 0.09% 96.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 159 2.38% 98.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 6 0.09% 99.03% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 6 0.09% 99.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 24 0.36% 99.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 8 0.12% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.04% 99.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 2 0.03% 99.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 8 0.12% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6686 # Writes before turning the bus around for reads system.physmem.totQLat 6416960776 # Total ticks spent queuing system.physmem.totMemAccLat 10008842026 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 957835000 # Total ticks spent in databus transfers system.physmem.avgQLat 33497.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 52247.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.67 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.32 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.60 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing system.physmem.readRowHits 159898 # Number of row buffer hits during reads system.physmem.writeRowHits 81351 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate 59.66 # Row buffer hit rate for writes system.physmem.avgGap 7914126.56 # Average gap between requests system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 337168440 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 183970875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 767988000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 447599520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 75926466675 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1509753884250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 1759016918640 # Total energy per rank (pJ) system.physmem_0.averagePower 669.525234 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2511501025755 # Time in different power states system.physmem_0.memoryStateTime::REF 87729980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 28029087995 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 317898000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 173456250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 726226800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 435831840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 75533290650 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 1510098775500 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 1758885319920 # Total energy per rank (pJ) system.physmem_1.averagePower 669.475144 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 2512077352355 # Time in different power states system.physmem_1.memoryStateTime::REF 87729980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 27453418145 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu0.branchPred.lookups 22632354 # Number of BP lookups system.cpu0.branchPred.condPredicted 14659623 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 908184 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 13749139 # Number of BTB lookups system.cpu0.branchPred.BTBHits 10145845 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 73.792584 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 3729563 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 29268 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.walks 62082 # Table walker walks requested system.cpu0.dtb.walker.walksShort 62082 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23874 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18654 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 19554 # Table walks squashed before starting system.cpu0.dtb.walker.walkWaitTime::samples 42528 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::mean 489.830229 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::stdev 2960.338749 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0-8191 41379 97.30% 97.30% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::8192-16383 822 1.93% 99.23% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.35% 99.58% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-32767 139 0.33% 99.91% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 42528 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 15147 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 9846.471248 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 8208.075631 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 8231.250252 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-32767 15054 99.39% 99.39% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::32768-65535 70 0.46% 99.85% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.14% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 15147 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 97524095656 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::mean 0.460762 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.504971 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0-1 97474132156 99.95% 99.95% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::2-3 37222000 0.04% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::4-5 6333500 0.01% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::6-7 3452500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::8-9 1280500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::10-11 673000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::12-13 722500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::14-15 263000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::16-17 16500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 97524095656 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 5018 79.05% 79.05% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::1M 1330 20.95% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 6348 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62082 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62082 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6348 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6348 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 68430 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 16776749 # DTB read hits system.cpu0.dtb.read_misses 53234 # DTB read misses system.cpu0.dtb.write_hits 13912942 # DTB write hits system.cpu0.dtb.write_misses 8848 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 2058 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 829 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 16829983 # DTB read accesses system.cpu0.dtb.write_accesses 13921790 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 30689691 # DTB hits system.cpu0.dtb.misses 62082 # DTB misses system.cpu0.dtb.accesses 30751773 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.walks 10470 # Table walker walks requested system.cpu0.itb.walker.walksShort 10470 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4275 # Level at which table walker walks with short descriptors terminate system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6082 # Level at which table walker walks with short descriptors terminate system.cpu0.itb.walker.walksSquashedBefore 113 # Table walks squashed before starting system.cpu0.itb.walker.walkWaitTime::samples 10357 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::mean 430.336970 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::stdev 2100.288015 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0-4095 9961 96.18% 96.18% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::4096-8191 126 1.22% 97.39% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::8192-12287 203 1.96% 99.35% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.37% 99.72% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.85% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::20480-24575 10 0.10% 99.94% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 10357 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 6522.127356 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-16383 2498 92.79% 92.79% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::16384-32767 161 5.98% 98.77% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-49151 32 1.19% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 20202424328 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::mean 0.966577 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::stdev 0.179934 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 675884500 3.35% 3.35% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::1 19525926328 96.65% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::2 564000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::3 49500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 20202424328 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2260 87.63% 87.63% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 319 12.37% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10470 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10470 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 13049 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 35710587 # ITB inst hits system.cpu0.itb.inst_misses 10470 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2356 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 1940 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 35721057 # ITB inst accesses system.cpu0.itb.hits 35710587 # DTB hits system.cpu0.itb.misses 10470 # DTB misses system.cpu0.itb.accesses 35721057 # DTB accesses system.cpu0.numCycles 126659372 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.fetch.icacheStallCycles 17871987 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 106431260 # Number of instructions fetch has processed system.cpu0.fetch.Branches 22632354 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 13875408 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 101673133 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2651880 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 146874 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 68068 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 354842 # Number of stall cycles due to pending traps system.cpu0.fetch.PendingQuiesceStallCycles 428688 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 93530 # Number of stall cycles due to full MSHR system.cpu0.fetch.CacheLines 35711195 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 256145 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 4738 # Number of outstanding ITLB misses that were squashed system.cpu0.fetch.rateDist::samples 121963062 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 1.052824 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 1.258485 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::0 62962688 51.62% 51.62% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 20162814 16.53% 68.16% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 8269817 6.78% 74.94% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 30567743 25.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 121963062 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.178687 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.840295 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 18684987 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 58693341 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 38833256 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 4747637 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1003841 # Number of cycles decode is squashing system.cpu0.decode.BranchResolved 2912386 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 326313 # Number of times decode detected a branch misprediction system.cpu0.decode.DecodedInsts 104496141 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 3704345 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 1003841 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 24126481 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 12572099 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 34554184 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 38013567 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 11692890 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 99684423 # Number of instructions processed by rename system.cpu0.rename.SquashedInsts 977099 # Number of squashed instructions processed by rename system.cpu0.rename.ROBFullEvents 1404281 # Number of times rename has blocked due to ROB full system.cpu0.rename.IQFullEvents 150386 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 54053 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 7679999 # Number of times rename has blocked due to SQ full system.cpu0.rename.RenamedOperands 103244507 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 455598825 # Number of register rename lookups that rename has made system.cpu0.rename.int_rename_lookups 114217475 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 92488092 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 10756412 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 1189033 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 1051673 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 11830745 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 17693579 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 15395073 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 1633265 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 2155883 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 96874005 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 1635627 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqInstsIssued 95096979 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 454397 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 8909178 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 20852751 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 116081 # Number of squashed non-spec instructions that were removed system.cpu0.iq.issued_per_cycle::samples 121963062 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.779720 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 1.027198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::0 68765776 56.38% 56.38% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 22213388 18.21% 74.60% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 21122370 17.32% 91.91% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 8807290 7.22% 99.14% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::4 1054209 0.86% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::total 121963062 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 8813581 40.35% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 132 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.35% # attempts to use FU when none available system.cpu0.iq.fu_full::MemRead 5351630 24.50% 64.85% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 7678552 35.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued system.cpu0.iq.FU_type_0::IntAlu 62602265 65.83% 65.83% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 87841 0.09% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 7143 0.01% 65.93% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.93% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.93% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.93% # Type of FU issued system.cpu0.iq.FU_type_0::MemRead 17444547 18.34% 84.28% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 14952910 15.72% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 95096979 # Type of FU issued system.cpu0.iq.rate 0.750809 # Inst issue rate system.cpu0.iq.fu_busy_cnt 21843895 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.229701 # FU busy rate (busy events/executed inst) system.cpu0.iq.int_inst_queue_reads 334422549 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 107425966 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 93117016 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 32763 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 11378 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9790 # Number of floating instruction queue wakeup accesses system.cpu0.iq.int_alu_accesses 116917216 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 21386 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 346137 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 1858057 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 2517 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 18608 # Number of memory ordering violations system.cpu0.iew.lsq.thread0.squashedStores 952368 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 100941 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 343903 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1003841 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 1765434 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 210085 # Number of cycles IEW is unblocking system.cpu0.iew.iewDispatchedInsts 98680740 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 17693579 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 15395073 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 848677 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 265563 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 639510 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 171108 # number of nop insts executed system.cpu0.iew.exec_refs 31795600 # number of memory reference insts executed system.cpu0.iew.exec_branches 15818182 # Number of branches executed system.cpu0.iew.exec_stores 14774938 # Number of stores executed system.cpu0.iew.exec_rate 0.742778 # Inst execution rate system.cpu0.iew.wb_sent 93557624 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 93126806 # cumulative count of insts written-back system.cpu0.iew.wb_producers 48392376 # num instructions producing a value system.cpu0.iew.wb_consumers 80015738 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.wb_rate 0.735254 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.604786 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 7942186 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 1519546 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 586085 # The number of times a branch was mispredicted system.cpu0.commit.committed_per_cycle::samples 120319586 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::mean 0.745699 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::stdev 1.465434 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::0 78400270 65.16% 65.16% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 23370127 19.42% 84.58% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 7855137 6.53% 91.11% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 3041175 2.53% 93.64% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 3186617 2.65% 96.29% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::5 1413825 1.18% 97.46% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 1097896 0.91% 98.38% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 521063 0.43% 98.81% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 1433476 1.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 120319586 # Number of insts commited each cycle system.cpu0.commit.committedInsts 74552173 # Number of instructions committed system.cpu0.commit.committedOps 89722144 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 30278227 # Number of memory references committed system.cpu0.commit.loads 15835522 # Number of loads committed system.cpu0.commit.membars 627502 # Number of memory barriers committed system.cpu0.commit.branches 15222627 # Number of branches committed system.cpu0.commit.fp_insts 9772 # Number of committed floating point instructions. system.cpu0.commit.int_insts 77510355 # Number of committed integer instructions. system.cpu0.commit.function_calls 1849810 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu0.commit.op_class_0::IntAlu 59351234 66.15% 66.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 85540 0.10% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMisc 7143 0.01% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction system.cpu0.commit.op_class_0::MemRead 15835522 17.65% 83.90% # Class of committed instruction system.cpu0.commit.op_class_0::MemWrite 14442705 16.10% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 89722144 # Class of committed instruction system.cpu0.commit.bw_lim_events 1433476 # number cycles where commit BW limit reached system.cpu0.rob.rob_reads 212523033 # The number of ROB reads system.cpu0.rob.rob_writes 196970686 # The number of ROB writes system.cpu0.timesIdled 126988 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 4696310 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 5127862528 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 74430479 # Number of Instructions Simulated system.cpu0.committedOps 89600450 # Number of Ops (including micro ops) Simulated system.cpu0.cpi 1.701714 # CPI: Cycles Per Instruction system.cpu0.cpi_total 1.701714 # CPI: Total CPI of All Threads system.cpu0.ipc 0.587643 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.587643 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 104622739 # number of integer regfile reads system.cpu0.int_regfile_writes 56501496 # number of integer regfile writes system.cpu0.fp_regfile_reads 8247 # number of floating regfile reads system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes system.cpu0.cc_regfile_reads 331476991 # number of cc regfile reads system.cpu0.cc_regfile_writes 38443016 # number of cc regfile writes system.cpu0.misc_regfile_reads 169856708 # number of misc regfile reads system.cpu0.misc_regfile_writes 1190913 # number of misc regfile writes system.cpu0.dcache.tags.replacements 672498 # number of replacements system.cpu0.dcache.tags.tagsinuse 485.161129 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 27296512 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 673010 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 40.558851 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.161129 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947580 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.947580 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 60152551 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 60152551 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 14711290 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 14711290 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 11396766 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 11396766 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295733 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 295733 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354236 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 354236 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350938 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 350938 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 26108056 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 26108056 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 26403789 # number of overall hits system.cpu0.dcache.overall_hits::total 26403789 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 611234 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 611234 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 1805910 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1805910 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141308 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 141308 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24174 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 24174 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21176 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 21176 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 2417144 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2417144 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 2558452 # number of overall misses system.cpu0.dcache.overall_misses::total 2558452 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9073163500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 9073163500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32396978375 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 32396978375 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 391326000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 391326000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534289500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 534289500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 728500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 728500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 41470141875 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 41470141875 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 41470141875 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 41470141875 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 15322524 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 15322524 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 13202676 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 13202676 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437041 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 437041 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378410 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 378410 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372114 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 372114 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 28525200 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 28525200 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 28962241 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 28962241 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039891 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.039891 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136784 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.136784 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323329 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323329 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063883 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063883 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056907 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056907 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084737 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.084737 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088338 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.088338 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17156.669969 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 17156.669969 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16209.075595 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 16209.075595 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 1312 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 5225040 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 49 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 192315 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.775510 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 27.169176 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 490431 # number of writebacks system.cpu0.dcache.writebacks::total 490431 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 244715 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 244715 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493725 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1493725 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18048 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18048 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 1738440 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1738440 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 1738440 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1738440 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366519 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 366519 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312185 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 312185 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97992 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 97992 # number of SoftPFReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6126 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6126 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21176 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 21176 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 678704 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 678704 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 776696 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 776696 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17958 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34667 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4650113000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4650113000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6789940400 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6789940400 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1696741500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1696741500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97425500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97425500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513125500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513125500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 716500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 716500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11440053400 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 11440053400 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13136794900 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 13136794900 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3760775500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3760775500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2938081500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2938081500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6698857000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6698857000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023920 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023920 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023646 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023646 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224217 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224217 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016189 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016189 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056907 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056907 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023793 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.023793 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026818 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026818 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253 # average SoftPFReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16855.732985 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16855.732985 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16913.689397 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16913.689397 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209420.620336 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209420.620336 # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175838.260818 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175838.260818 # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193234.401592 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1200820 # number of replacements system.cpu0.icache.tags.tagsinuse 511.709969 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 34456109 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1201332 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 28.681588 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 8093069500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.709969 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 72616555 # Number of tag accesses system.cpu0.icache.tags.data_accesses 72616555 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 34456109 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 34456109 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 34456109 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 34456109 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 34456109 # number of overall hits system.cpu0.icache.overall_hits::total 34456109 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 1251492 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 1251492 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 1251492 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 1251492 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 1251492 # number of overall misses system.cpu0.icache.overall_misses::total 1251492 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13477536890 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 13477536890 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 13477536890 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 13477536890 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 13477536890 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 13477536890 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 35707601 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 35707601 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 35707601 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 35707601 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 35707601 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 35707601 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035048 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.035048 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035048 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.035048 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035048 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.035048 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10769.175424 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 10769.175424 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 10769.175424 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 10769.175424 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1798735 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 112593 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.975549 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50137 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 50137 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu0.inst 50137 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 50137 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 50137 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 50137 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201355 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 1201355 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201355 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 1201355 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201355 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 1201355 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12113813705 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 12113813705 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12113813705 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 12113813705 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12113813705 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 12113813705 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420637998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420637998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420637998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 420637998 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033644 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.033644 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.033644 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10083.458849 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140025.964714 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767941 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1770755 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 2568 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 220461 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 267926 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16038.044511 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 3405557 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 284162 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 11.984562 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 9237.046322 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.824240 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.088026 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3962.897629 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1653.213235 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.975059 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.563785 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.241876 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100904 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071532 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.978885 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1081 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15141 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 306 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4597 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7301 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2771 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065979 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924133 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 63212919 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 63212919 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49275 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12221 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 61496 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 490428 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 490428 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28559 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 28559 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1634 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 1634 # number of SCUpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 183915 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 183915 # number of ReadExReq hits system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1150269 # number of ReadCleanReq hits system.cpu0.l2cache.ReadCleanReq_hits::total 1150269 # number of ReadCleanReq hits system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 371621 # number of ReadSharedReq hits system.cpu0.l2cache.ReadSharedReq_hits::total 371621 # number of ReadSharedReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49275 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12221 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 1150269 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 555536 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 1767301 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49275 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12221 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 1150269 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 555536 # number of overall hits system.cpu0.l2cache.overall_hits::total 1767301 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 406 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 160 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 566 # number of ReadReq misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27413 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 27413 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19541 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 19541 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 72546 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 72546 # number of ReadExReq misses system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 51075 # number of ReadCleanReq misses system.cpu0.l2cache.ReadCleanReq_misses::total 51075 # number of ReadCleanReq misses system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98927 # number of ReadSharedReq misses system.cpu0.l2cache.ReadSharedReq_misses::total 98927 # number of ReadSharedReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 406 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 160 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.inst 51075 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.data 171473 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 223114 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 406 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 160 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.inst 51075 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.data 171473 # number of overall misses system.cpu0.l2cache.overall_misses::total 223114 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12326500 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4195000 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 16521500 # number of ReadReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 607087500 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 607087500 # number of UpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 414982000 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 414982000 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 697999 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 697999 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3859915499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 3859915499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3399489999 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3399489999 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3280988498 # number of ReadSharedReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3280988498 # number of ReadSharedReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12326500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4195000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3399489999 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.data 7140903997 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 10556915496 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12326500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4195000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3399489999 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.data 7140903997 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 10556915496 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 49681 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12381 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 62062 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 490428 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 490428 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55972 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 55972 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21175 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 21175 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256461 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 256461 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1201344 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1201344 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 470548 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 470548 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 49681 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12381 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1201344 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 727009 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 1990415 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 49681 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12381 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1201344 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 727009 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 1990415 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012923 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.009120 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489763 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489763 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.922834 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.922834 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.282873 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.282873 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042515 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042515 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.210238 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.210238 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012923 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042515 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235861 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.112094 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012923 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042515 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235861 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.112094 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26218.750000 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29189.929329 # average ReadReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22145.970890 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22145.970890 # average UpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21236.477151 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21236.477151 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 697999 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 697999 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53206.455201 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53206.455201 # average ReadExReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 66558.786079 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 66558.786079 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33165.753515 # average ReadSharedReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33165.753515 # average ReadSharedReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26218.750000 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 66558.786079 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41644.480455 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 47316.239662 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26218.750000 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 66558.786079 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41644.480455 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 47316.239662 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 193883 # number of writebacks system.cpu0.l2cache.writebacks::total 193883 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 31886 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 31886 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 21 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 720 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 720 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 21 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.data 32606 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 32628 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 21 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.data 32606 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 32628 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 406 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 565 # number of ReadReq MSHR misses system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8411 # number of CleanEvict MSHR misses system.cpu0.l2cache.CleanEvict_mshr_misses::total 8411 # number of CleanEvict MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 234452 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 234452 # number of HardPFReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27413 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27413 # number of UpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19541 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19541 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40660 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 40660 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 51054 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 51054 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 98207 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 98207 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 406 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 51054 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138867 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 190486 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 406 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 51054 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138867 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 234452 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 424938 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20962 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37671 # number of overall MSHR uncacheable misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3228500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 13119000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20996976517 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20996976517 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 895938500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 895938500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 352988996 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 352988996 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 625999 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 625999 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2326484000 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2326484000 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3092587999 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3092587999 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2638772998 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2638772998 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3228500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3092587999 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4965256998 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 8070963997 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3228500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3092587999 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4965256998 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20996976517 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 29067940514 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398106500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3617019000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4015125500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2810012462 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2810012462 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398106500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6427031462 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6825137962 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009104 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489763 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489763 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.922834 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.922834 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158543 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158543 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042497 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208708 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.208708 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.095702 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.213492 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23219.469027 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 89557.677124 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 625999 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 625999 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.snoop_filter.tot_requests 3900428 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1972103 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 30395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.snoop_filter.tot_snoops 166078 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 150 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 98608 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1819240 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 16709 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 16709 # Transaction distribution system.cpu0.toL2Bus.trans_dist::Writeback 685334 # Transaction distribution system.cpu0.toL2Bus.trans_dist::CleanEvict 1450937 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 287419 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 90627 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43495 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 114961 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 273601 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 270191 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1201355 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 557036 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 3216 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3585963 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2443651 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28820 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 110863 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 6169297 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76933952 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82016191 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49524 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 198724 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 159198391 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 860528 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 4738789 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 0.052471 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.223116 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 4490292 94.76% 94.76% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 248347 5.24% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 150 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 4738789 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 2495889948 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 112738429 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 1805438687 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 1156413493 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 16448481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 61214934 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 35362528 # Number of BP lookups system.cpu1.branchPred.condPredicted 12650645 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 376011 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 19640345 # Number of BTB lookups system.cpu1.branchPred.BTBHits 15643376 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 79.649191 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 12652559 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 10779 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.walks 24283 # Table walker walks requested system.cpu1.dtb.walker.walksShort 24283 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11247 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5966 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 7070 # Table walks squashed before starting system.cpu1.dtb.walker.walkWaitTime::samples 17213 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::mean 473.798873 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::stdev 2831.806000 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0-4095 16574 96.29% 96.29% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::4096-8191 219 1.27% 97.56% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::8192-12287 229 1.33% 98.89% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::12288-16383 75 0.44% 99.33% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.44% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.14% 99.58% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.04% 99.62% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.25% 99.87% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::32768-36863 17 0.10% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 17213 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 5394 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 9365.976538 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 8403.035892 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-16383 4813 89.23% 89.23% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::16384-32767 520 9.64% 98.87% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::32768-49151 49 0.91% 99.78% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::49152-65535 4 0.07% 99.85% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.06% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::147456-163839 4 0.07% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 5394 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 75766592176 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::mean 0.320474 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::stdev 0.469554 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 51526613188 68.01% 68.01% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::1 24219637488 31.97% 99.97% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::2 12480500 0.02% 99.99% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::3 3766000 0.00% 99.99% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::4 1197500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::5 815500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::6 985500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::7 293500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::8 146000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::9 224500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::10 83500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::11 76500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::12 137000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::13 18000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::14 22000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::15 95500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 75766592176 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 1932 75.85% 75.85% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 615 24.15% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 2547 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2547 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2547 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 26830 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 11209013 # DTB read hits system.cpu1.dtb.read_misses 21079 # DTB read misses system.cpu1.dtb.write_hits 7325054 # DTB write hits system.cpu1.dtb.write_misses 3204 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2001 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 612 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 367 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 11230092 # DTB read accesses system.cpu1.dtb.write_accesses 7328258 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 18534067 # DTB hits system.cpu1.dtb.misses 24283 # DTB misses system.cpu1.dtb.accesses 18558350 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.walks 6861 # Table walker walks requested system.cpu1.itb.walker.walksShort 6861 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4105 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2676 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksSquashedBefore 80 # Table walks squashed before starting system.cpu1.itb.walker.walkWaitTime::samples 6781 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::mean 216.855921 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::stdev 1684.274104 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0-4095 6669 98.35% 98.35% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::4096-8191 39 0.58% 98.92% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::8192-12287 44 0.65% 99.57% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::12288-16383 12 0.18% 99.75% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 6781 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1249 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 6381.189280 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-8191 353 28.26% 28.26% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 65.17% 93.43% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::16384-24575 24 1.92% 95.36% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::24576-32767 32 2.56% 97.92% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::32768-40959 17 1.36% 99.28% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.56% 99.84% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.92% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.08% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1249 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 15604919032 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::mean 0.958751 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::stdev 0.198933 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 643875264 4.13% 4.13% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::1 14960875268 95.87% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::2 148500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::3 20000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 15604919032 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 997 85.29% 85.29% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 172 14.71% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1169 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6861 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6861 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1169 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1169 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 8030 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 45813094 # ITB inst hits system.cpu1.itb.inst_misses 6861 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 526 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 45819955 # ITB inst accesses system.cpu1.itb.hits 45813094 # DTB hits system.cpu1.itb.misses 6861 # DTB misses system.cpu1.itb.accesses 45819955 # DTB accesses system.cpu1.numCycles 115872528 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.fetch.icacheStallCycles 11244647 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 115696053 # Number of instructions fetch has processed system.cpu1.fetch.Branches 35362528 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 28295935 # Number of branches that fetch has predicted taken system.cpu1.fetch.Cycles 100513645 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3955668 # Number of cycles fetch has spent squashing system.cpu1.fetch.TlbCycles 92958 # Number of cycles fetch has spent waiting for tlb system.cpu1.fetch.MiscStallCycles 43827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.PendingTrapStallCycles 218813 # Number of stall cycles due to pending traps system.cpu1.fetch.PendingQuiesceStallCycles 324785 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 35760 # Number of stall cycles due to full MSHR system.cpu1.fetch.CacheLines 45812479 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 133633 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.ItlbSquashes 2410 # Number of outstanding ITLB misses that were squashed system.cpu1.fetch.rateDist::samples 114452269 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 1.250587 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 1.333322 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 53787165 47.00% 47.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 15397458 13.45% 60.45% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 8067873 7.05% 67.50% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 37199773 32.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 114452269 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.branchRate 0.305185 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.998477 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 14331089 # Number of cycles decode is idle system.cpu1.decode.BlockedCycles 67536075 # Number of cycles decode is blocked system.cpu1.decode.RunCycles 29425449 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 1338809 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 1820847 # Number of cycles decode is squashing system.cpu1.decode.BranchResolved 912295 # Number of times decode resolved a branch system.cpu1.decode.BranchMispred 160061 # Number of times decode detected a branch misprediction system.cpu1.decode.DecodedInsts 74627346 # Number of instructions handled by decode system.cpu1.decode.SquashedInsts 1451044 # Number of squashed instructions handled by decode system.cpu1.rename.SquashCycles 1820847 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 19084331 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 2925531 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 61205079 # count of cycles rename stalled for serializing inst system.cpu1.rename.RunCycles 25977648 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 3438833 # Number of cycles rename is unblocking system.cpu1.rename.RenamedInsts 61437487 # Number of instructions processed by rename system.cpu1.rename.SquashedInsts 313811 # Number of squashed instructions processed by rename system.cpu1.rename.ROBFullEvents 329328 # Number of times rename has blocked due to ROB full system.cpu1.rename.IQFullEvents 50880 # Number of times rename has blocked due to IQ full system.cpu1.rename.LQFullEvents 21104 # Number of times rename has blocked due to LQ full system.cpu1.rename.SQFullEvents 2227690 # Number of times rename has blocked due to SQ full system.cpu1.rename.RenamedOperands 61781071 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 288761968 # Number of register rename lookups that rename has made system.cpu1.rename.int_rename_lookups 65715217 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 58198437 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 3582634 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1923301 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1845273 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 13635165 # count of insts added to the skid buffer system.cpu1.memDep0.insertedLoads 11552975 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 7780383 # Number of stores inserted to the mem dependence unit. system.cpu1.memDep0.conflictingLoads 701343 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 925146 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 60392573 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 653667 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqInstsIssued 59853310 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 146761 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 4556505 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 7374621 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 54925 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 114452269 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::mean 0.522954 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 0.862457 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 77949624 68.11% 68.11% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 17744881 15.50% 83.61% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 14511556 12.68% 96.29% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::3 3899540 3.41% 99.70% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 346643 0.30% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 25 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::total 114452269 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 3494882 44.84% 44.84% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 604 0.01% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.85% # attempts to use FU when none available system.cpu1.iq.fu_full::MemRead 1953801 25.07% 69.91% # attempts to use FU when none available system.cpu1.iq.fu_full::MemWrite 2345303 30.09% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued system.cpu1.iq.FU_type_0::IntAlu 40748712 68.08% 68.08% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 52853 0.09% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.17% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 4129 0.01% 68.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.18% # Type of FU issued system.cpu1.iq.FU_type_0::MemRead 11462159 19.15% 87.33% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 7585390 12.67% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 59853310 # Type of FU issued system.cpu1.iq.rate 0.516544 # Inst issue rate system.cpu1.iq.fu_busy_cnt 7794590 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.130228 # FU busy rate (busy events/executed inst) system.cpu1.iq.int_inst_queue_reads 242094525 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 65611557 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 57714006 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 5715 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses system.cpu1.iq.int_alu_accesses 67644200 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 3633 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 110002 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 628284 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 842 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 10885 # Number of memory ordering violations system.cpu1.iew.lsq.thread0.squashedStores 426405 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 57089 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 100676 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 1820847 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 727831 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 179449 # Number of cycles IEW is unblocking system.cpu1.iew.iewDispatchedInsts 61101449 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispLoadInsts 11552975 # Number of dispatched load instructions system.cpu1.iew.iewDispStoreInsts 7780383 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 331927 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 11154 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 159363 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 10885 # Number of memory order violations system.cpu1.iew.predictedTakenIncorrect 82141 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 153260 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 235401 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 59500982 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 11329735 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 328066 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 55209 # number of nop insts executed system.cpu1.iew.exec_refs 18836194 # number of memory reference insts executed system.cpu1.iew.exec_branches 12894851 # Number of branches executed system.cpu1.iew.exec_stores 7506459 # Number of stores executed system.cpu1.iew.exec_rate 0.513504 # Inst execution rate system.cpu1.iew.wb_sent 59314333 # cumulative count of insts sent to commit system.cpu1.iew.wb_count 57715790 # cumulative count of insts written-back system.cpu1.iew.wb_producers 28288530 # num instructions producing a value system.cpu1.iew.wb_consumers 43462608 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.wb_rate 0.498097 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.650871 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 4228906 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 598742 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 219024 # The number of times a branch was mispredicted system.cpu1.commit.committed_per_cycle::samples 112407306 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::mean 0.502841 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::stdev 1.169324 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::0 84196637 74.90% 74.90% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::1 15782926 14.04% 88.94% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 6506905 5.79% 94.73% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 899885 0.80% 95.53% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 2238894 1.99% 97.53% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::5 1696394 1.51% 99.03% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 469505 0.42% 99.45% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 157300 0.14% 99.59% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 458860 0.41% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 112407306 # Number of insts commited each cycle system.cpu1.commit.committedInsts 46016034 # Number of instructions committed system.cpu1.commit.committedOps 56522947 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 18278669 # Number of memory references committed system.cpu1.commit.loads 10924691 # Number of loads committed system.cpu1.commit.membars 232005 # Number of memory barriers committed system.cpu1.commit.branches 12685356 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. system.cpu1.commit.int_insts 50487985 # Number of committed integer instructions. system.cpu1.commit.function_calls 3456157 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu1.commit.op_class_0::IntAlu 38188356 67.56% 67.56% # Class of committed instruction system.cpu1.commit.op_class_0::IntMult 51793 0.09% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.65% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMisc 4129 0.01% 67.66% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.66% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.66% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.66% # Class of committed instruction system.cpu1.commit.op_class_0::MemRead 10924691 19.33% 86.99% # Class of committed instruction system.cpu1.commit.op_class_0::MemWrite 7353978 13.01% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 56522947 # Class of committed instruction system.cpu1.commit.bw_lim_events 458860 # number cycles where commit BW limit reached system.cpu1.rob.rob_reads 152481338 # The number of ROB reads system.cpu1.rob.rob_writes 123545319 # The number of ROB writes system.cpu1.timesIdled 68699 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 1420259 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 5138082707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 45982821 # Number of Instructions Simulated system.cpu1.committedOps 56489734 # Number of Ops (including micro ops) Simulated system.cpu1.cpi 2.519909 # CPI: Cycles Per Instruction system.cpu1.cpi_total 2.519909 # CPI: Total CPI of All Threads system.cpu1.ipc 0.396840 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.396840 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 62666330 # number of integer regfile reads system.cpu1.int_regfile_writes 39173045 # number of integer regfile writes system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes system.cpu1.cc_regfile_reads 211754483 # number of cc regfile reads system.cpu1.cc_regfile_writes 18307351 # number of cc regfile writes system.cpu1.misc_regfile_reads 158297998 # number of misc regfile reads system.cpu1.misc_regfile_writes 426234 # number of misc regfile writes system.cpu1.dcache.tags.replacements 227119 # number of replacements system.cpu1.dcache.tags.tagsinuse 480.780000 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 17377933 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 227440 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 76.406670 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 89481619000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 480.780000 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.939023 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.939023 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 24 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 36531516 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 36531516 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 10502192 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 10502192 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 6578620 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 6578620 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65191 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 65191 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88541 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 88541 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80577 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 80577 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 17080812 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 17080812 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 17146003 # number of overall hits system.cpu1.dcache.overall_hits::total 17146003 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 257246 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 257246 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 477990 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 477990 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35676 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 35676 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19120 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 19120 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23513 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 23513 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 735236 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 735236 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 770912 # number of overall misses system.cpu1.dcache.overall_misses::total 770912 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4397234500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 4397234500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13204055417 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 13204055417 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 384125500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 384125500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615714500 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 615714500 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2019500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2019500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 17601289917 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 17601289917 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 17601289917 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 17601289917 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 10759438 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 10759438 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7056610 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 7056610 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100867 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 100867 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107661 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 107661 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104090 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 104090 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 17816048 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 17816048 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 17916915 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 17916915 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023909 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.023909 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067736 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.067736 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353693 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353693 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177594 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177594 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225891 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225891 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041268 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.041268 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043027 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.043027 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 1982545 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 49131 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.243243 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets 40.352222 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 137800 # number of writebacks system.cpu1.dcache.writebacks::total 137800 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 93990 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 93990 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 374320 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 374320 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13607 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13607 # number of LoadLockedReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 468310 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 468310 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 468310 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 468310 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163256 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 163256 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103670 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 103670 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32269 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 32269 # number of SoftPFReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5513 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5513 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23513 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 23513 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 266926 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 266926 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 299195 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 299195 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17062 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31403 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2326061500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2326061500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3203086933 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3203086933 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 553503000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 553503000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 109001000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 109001000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592222500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592222500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1998500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5529148433 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 5529148433 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6082651433 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 6082651433 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2940631000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2940631000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2452626000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2452626000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5393257000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5393257000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015173 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015173 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014691 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014691 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319916 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319916 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051207 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051207 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225891 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225891 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014982 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.014982 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016699 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.016699 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208 # average SoftPFReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20714.162101 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20714.162101 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20330.057097 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534 # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995 # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995 # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 672301 # number of replacements system.cpu1.icache.tags.tagsinuse 498.450521 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 45113050 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 672813 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 67.051395 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 79271830500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.450521 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973536 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.973536 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 92297132 # Number of tag accesses system.cpu1.icache.tags.data_accesses 92297132 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 45113050 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 45113050 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 45113050 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 45113050 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 45113050 # number of overall hits system.cpu1.icache.overall_hits::total 45113050 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 699105 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 699105 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 699105 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 699105 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 699105 # number of overall misses system.cpu1.icache.overall_misses::total 699105 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6808598319 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 6808598319 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 6808598319 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 6808598319 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 6808598319 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 6808598319 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 45812155 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 45812155 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 45812155 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 45812155 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 45812155 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 45812155 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.015260 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.015260 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.015260 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9739.021061 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 9739.021061 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 9739.021061 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 9739.021061 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 778427 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 223 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 55737 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.966073 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets 111.500000 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 26283 # number of ReadReq MSHR hits system.cpu1.icache.ReadReq_mshr_hits::total 26283 # number of ReadReq MSHR hits system.cpu1.icache.demand_mshr_hits::cpu1.inst 26283 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_hits::total 26283 # number of demand (read+write) MSHR hits system.cpu1.icache.overall_mshr_hits::cpu1.inst 26283 # number of overall MSHR hits system.cpu1.icache.overall_mshr_hits::total 26283 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672822 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 672822 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 672822 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 672822 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 672822 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 672822 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6167077156 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 6167077156 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6167077156 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 6167077156 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6167077156 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6167077156 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13506000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13506000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13506000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13506000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014687 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.014687 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.014687 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9165.986184 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 262736 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 263407 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 604 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 68017 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 62303 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15536.648070 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 1677232 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 76854 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 21.823614 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 6569.267487 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.374590 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.390464 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4943.655897 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2538.739672 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1470.219959 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.400956 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000877 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000024 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301737 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.154952 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.089735 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.948282 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1250 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 33 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13268 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 890 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8543 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4263 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076294 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002014 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.809814 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 30842090 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 30842090 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19102 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7340 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 26442 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 137798 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 137798 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1915 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 1915 # number of UpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1089 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 1089 # number of SCUpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37080 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 37080 # number of ReadExReq hits system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 650319 # number of ReadCleanReq hits system.cpu1.l2cache.ReadCleanReq_hits::total 650319 # number of ReadCleanReq hits system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 128580 # number of ReadSharedReq hits system.cpu1.l2cache.ReadSharedReq_hits::total 128580 # number of ReadSharedReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19102 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7340 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 650319 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 165660 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 842421 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19102 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7340 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 650319 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 165660 # number of overall hits system.cpu1.l2cache.overall_hits::total 842421 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 434 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 283 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29244 # 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number of ReadSharedReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10853500 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5913500 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1248275500 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.data 3745713491 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 5010755991 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10853500 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5913500 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1248275500 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.data 3745713491 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 5010755991 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19536 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7623 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 27159 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 137799 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 137799 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31159 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 31159 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23513 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 23513 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73151 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 73151 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 672811 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 672811 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 201010 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 201010 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19536 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7623 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 672811 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 274161 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 974131 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19536 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7623 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 672811 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 274161 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 974131 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022215 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037124 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.026400 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938541 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938541 # 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average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20311.294590 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21059.489832 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21059.489832 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52945.080508 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52945.080508 # average ReadExReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55498.643962 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55498.643962 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25347.666602 # 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average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 38043.853853 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 22.500000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 35002 # number of writebacks system.cpu1.l2cache.writebacks::total 35002 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # 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number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1591439000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1591439000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1112203000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1112203000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1393604492 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1393604492 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8235500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4129500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1112203000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2985043492 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 4109611492 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8235500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4129500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1112203000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2985043492 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1812441817 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 5922053309 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12741000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2803854000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2816595000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2344848498 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2344848498 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12741000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5148702498 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5161443498 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025885 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938541 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938541 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.953685 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.953685 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.471080 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.471080 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359509 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359509 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133351 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170100 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.snoop_filter.tot_requests 1911239 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 964293 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 15206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.snoop_filter.tot_snoops 115900 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 115705 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 49800 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 965132 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 14341 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution system.cpu1.toL2Bus.trans_dist::Writeback 177279 # Transaction distribution system.cpu1.toL2Bus.trans_dist::CleanEvict 810351 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 43777 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 73201 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 89676 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 81502 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 78977 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 672822 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 286780 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 213 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2005740 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1027154 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17080 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42715 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 3092689 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43061536 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29508655 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30492 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78144 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 72678827 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 390895 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 2268265 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 0.069071 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.253913 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 2111789 93.10% 93.10% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 156281 6.89% 99.99% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 195 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 2268265 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 1127589981 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 88549490 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 1009459749 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 464204253 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 9470972 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 23200956 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31010 # Transaction distribution system.iobus.trans_dist::ReadResp 31010 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer27.occupancy 186507978 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements system.iocache.tags.tagsinuse 14.440882 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 256003407000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ide 14.440882 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.902555 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.902555 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 32773877 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 32773877 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4715888101 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4715888101 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 32773877 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 32773877 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 32773877 # number of overall miss cycles system.iocache.overall_miss_latency::total 32773877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 130055.067460 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency system.iocache.demand_avg_miss_latency::total 130055.067460 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency system.iocache.overall_avg_miss_latency::total 130055.067460 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 4.200000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 20173877 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 20173877 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904688101 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2904688101 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 20173877 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 20173877 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 20173877 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 20173877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 129384 # number of replacements system.l2c.tags.tagsinuse 63948.068698 # Cycle average of tags in use system.l2c.tags.total_refs 411864 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 193785 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.125366 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 12531.983329 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.494639 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048364 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 6442.782513 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 2029.980541 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.674973 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.902888 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 3492.124605 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 1459.870620 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3683.572737 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.191223 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.098309 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.030975 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.523066 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.053286 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.022276 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.056207 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.975770 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 30986 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 33385 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 6088 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 24764 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.472809 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.509415 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 5503227 # Number of tag accesses system.l2c.tags.data_accesses 5503227 # Number of data accesses system.l2c.Writeback_hits::writebacks 228886 # number of Writeback hits system.l2c.Writeback_hits::total 228886 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2462 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 805 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3267 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 259 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 3934 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 2169 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 6103 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 77 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.inst 33993 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.data 45721 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45094 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 77 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 41 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.inst 17373 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 11135 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7486 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 161181 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 77 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 33993 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 49655 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 45094 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 17373 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 13304 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 7486 # number of demand (read+write) hits system.l2c.demand_hits::total 167284 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 77 # number of overall hits system.l2c.overall_hits::cpu0.inst 33993 # number of overall hits system.l2c.overall_hits::cpu0.data 49655 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 45094 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 77 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits system.l2c.overall_hits::cpu1.inst 17373 # number of overall hits system.l2c.overall_hits::cpu1.data 13304 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 7486 # number of overall hits system.l2c.overall_hits::total 167284 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 8340 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 3970 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12310 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 899 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1200 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2099 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 10813 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 8272 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 19085 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 24 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 5 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.inst 17052 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.data 7978 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 127774 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 14 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.inst 5084 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 2174 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9295 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 169401 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 17052 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 18791 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 127774 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 5084 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 10446 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 9295 # number of demand (read+write) misses system.l2c.demand_misses::total 188486 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 24 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.inst 17052 # number of overall misses system.l2c.overall_misses::cpu0.data 18791 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 127774 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 5084 # number of overall misses system.l2c.overall_misses::cpu1.data 10446 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 9295 # number of overall misses system.l2c.overall_misses::total 188486 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0.data 18505000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 12201500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 30706500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2576000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3491000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 6067000 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 1643662000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1106109000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 2749771000 # number of ReadExReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3382000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 654000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2259320501 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 1108395000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20200841109 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1916500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 687304500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 302855500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1643216668 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 26208018278 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 3382000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 654000 # 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miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.776339 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918836 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.851867 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.733234 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.792261 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.757702 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.060976 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.334058 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.148569 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739142 # 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miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.023810 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.226388 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.439832 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.553900 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.529797 # miss rate for overall accesses system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2218.824940 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3073.425693 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 2494.435418 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2865.406007 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2909.166667 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 2890.424011 # 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number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 928342001 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 69607504 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 92088000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 161695504 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1535532000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1023389000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 2558921000 # number of ReadExReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 604000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2088682501 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1028615000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 635761500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 281115500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::total 24513187278 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 604000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 2088682501 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 2564147000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 635761500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 1304504500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 27072108278 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 604000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 2088682501 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 2564147000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 635761500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1304504500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 27072108278 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344034000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3293772500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10902500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2496744500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 6145453500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2525916538 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2101048002 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4626964540 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344034000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5819689038 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10902500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4597792502 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 10772418040 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772079 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.831414 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.790268 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.776339 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.918836 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.851867 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733234 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792261 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.757702 # mshr miss rate for ReadExReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.148569 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.163348 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.512405 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.529772 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.529772 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75444.184652 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75349.496474 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75413.647522 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77427.701891 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76740 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77034.542163 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 142007.953389 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123717.238878 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 134080.220068 # average ReadExReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128931.436450 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380 # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 38123 # Transaction distribution system.membus.trans_dist::ReadResp 207766 # Transaction distribution system.membus.trans_dist::WriteReq 31050 # Transaction distribution system.membus.trans_dist::WriteResp 31050 # Transaction distribution system.membus.trans_dist::Writeback 135856 # Transaction distribution system.membus.trans_dist::CleanEvict 15674 # Transaction distribution system.membus.trans_dist::UpgradeReq 78082 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 41568 # Transaction distribution system.membus.trans_dist::UpgradeResp 14509 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution system.membus.trans_dist::ReadExReq 38794 # Transaction distribution system.membus.trans_dist::ReadExResp 18985 # Transaction distribution system.membus.trans_dist::ReadSharedReq 169644 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14282 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661810 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 784044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 892978 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28564 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18481720 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 18673398 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 20991542 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 125523 # Total snoops (count) system.membus.snoop_fanout::samples 585264 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 585264 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 585264 # Request fanout histogram system.membus.reqLayer0.occupancy 81621000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 11798981 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 986725496 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 1119474906 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 64610767 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.toL2Bus.snoop_filter.tot_requests 957960 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 483276 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 165836 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 22284 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 21444 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 38126 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 494242 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 31050 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 31050 # Transaction distribution system.toL2Bus.trans_dist::Writeback 364748 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 86802 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 81249 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 41933 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 123182 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 50538 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 50538 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 456132 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1043214 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 384499 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 1427713 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31299443 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6394691 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 37694134 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 458404 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 1229453 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.314167 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.465653 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 844039 68.65% 68.65% # Request fanout histogram system.toL2Bus.snoop_fanout::1 384574 31.28% 99.93% # Request fanout histogram system.toL2Bus.snoop_fanout::2 840 0.07% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 1229453 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 827244513 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 603608816 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 273833055 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 2086 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed ---------- End Simulation Statistics ----------