---------- Begin Simulation Statistics ---------- sim_seconds 2.631271 # Number of seconds simulated sim_ticks 2631271319500 # Number of ticks simulated final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 354699 # Simulator instruction rate (inst/s) host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) host_tick_rate 15499898557 # Simulator tick rate (ticks/s) host_mem_usage 465856 # Number of bytes of host memory used host_seconds 169.76 # Real time elapsed on the host sim_insts 60213853 # Number of instructions simulated sim_ops 76620850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15690868 # Number of read requests accepted system.physmem.writeReqs 811684 # Number of write requests accepted system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts system.physmem.perBankRdBursts::3 980428 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts system.physmem.perBankRdBursts::6 980611 # Per bank write bursts system.physmem.perBankRdBursts::7 980420 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979544 # Per bank write bursts system.physmem.perBankRdBursts::12 980153 # Per bank write bursts system.physmem.perBankRdBursts::13 980076 # Per bank write bursts system.physmem.perBankRdBursts::14 980177 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts system.physmem.perBankWrBursts::0 6626 # Per bank write bursts system.physmem.perBankWrBursts::1 6496 # Per bank write bursts system.physmem.perBankWrBursts::2 6497 # Per bank write bursts system.physmem.perBankWrBursts::3 6558 # Per bank write bursts system.physmem.perBankWrBursts::4 6634 # Per bank write bursts system.physmem.perBankWrBursts::5 6937 # Per bank write bursts system.physmem.perBankWrBursts::6 6920 # Per bank write bursts system.physmem.perBankWrBursts::7 6772 # Per bank write bursts system.physmem.perBankWrBursts::8 6893 # Per bank write bursts system.physmem.perBankWrBursts::9 6718 # Per bank write bursts system.physmem.perBankWrBursts::10 6212 # Per bank write bursts system.physmem.perBankWrBursts::11 6014 # Per bank write bursts system.physmem.perBankWrBursts::12 6499 # Per bank write bursts system.physmem.perBankWrBursts::13 6274 # Per bank write bursts system.physmem.perBankWrBursts::14 6516 # Per bank write bursts system.physmem.perBankWrBursts::15 6506 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 2631266900000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 152172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57666 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads system.physmem.totQLat 402822623250 # Total ticks spent queuing system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing system.physmem.readRowHits 14667283 # Number of row buffer hits during reads system.physmem.writeRowHits 88101 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes system.physmem.avgGap 159446.06 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states system.physmem.memoryStateTime::REF 87863880000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 54394584 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16743630 # Transaction distribution system.membus.trans_dist::ReadResp 16743630 # Transaction distribution system.membus.trans_dist::WriteReq 763389 # Transaction distribution system.membus.trans_dist::WriteResp 763389 # Transaction distribution system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution system.membus.trans_dist::ReadExReq 131349 # Transaction distribution system.membus.trans_dist::ReadExResp 131349 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 143126910 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62060 # number of replacements system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 17278044 # Number of tag accesses system.l2c.tags.data_accesses 17278044 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits system.l2c.Writeback_hits::total 596476 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56762 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 114533 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 10108 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3664 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 418356 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 245103 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 9807 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 426125 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 239886 # number of demand (read+write) hits system.l2c.demand_hits::total 1356617 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 10108 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3664 # number of overall hits system.l2c.overall_hits::cpu0.inst 418356 # number of overall hits system.l2c.overall_hits::cpu0.data 245103 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 9807 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits system.l2c.overall_hits::cpu1.inst 426125 # number of overall hits system.l2c.overall_hits::cpu1.data 239886 # number of overall hits system.l2c.overall_hits::total 1356617 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 4266 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 5262 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 4967 # number of ReadReq misses system.l2c.ReadReq_misses::total 20823 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1468 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1421 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2889 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 66168 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 66809 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 132977 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 4266 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 71430 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 71776 # number of demand (read+write) misses system.l2c.demand_misses::total 153800 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 4266 # number of overall misses system.l2c.overall_misses::cpu0.data 71430 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses system.l2c.overall_misses::cpu1.data 71776 # number of overall misses system.l2c.overall_misses::total 153800 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 299478000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 388418000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 441554500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 374768000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1504457250 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 209991 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 255989 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 4604837922 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 4645007200 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 9249845122 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 299478000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 4993255922 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 441554500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 5019775200 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 10754302372 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 299478000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 4993255922 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 441554500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 5019775200 # number of overall miss cycles system.l2c.overall_miss_latency::total 10754302372 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 10108 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3666 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 422622 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 192594 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9808 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 3568 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 432450 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 188091 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1262907 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 596476 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 596476 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1483 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1432 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2915 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 123939 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 123571 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247510 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 10108 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3666 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 422622 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 316533 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9808 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 3568 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 432450 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 311662 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1510417 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 10108 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3666 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 422622 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 316533 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 9808 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 3568 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 432450 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 311662 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1510417 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000546 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.010094 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.027322 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014626 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.026407 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016488 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989885 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992318 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991081 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.533876 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.540653 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.537259 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000546 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.010094 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.225664 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014626 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.230301 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.101826 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000546 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.010094 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.225664 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014626 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.230301 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.101826 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70201.125176 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 73815.659445 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69810.988142 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 75451.580431 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 72249.783893 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 143.045640 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 180.147080 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 161.294566 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69593.125408 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69526.668563 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 69559.736812 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 70201.125176 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 69904.184824 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 69810.988142 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 69936.680785 # average overall miss latency system.l2c.demand_avg_miss_latency::total 69923.942601 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 70201.125176 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 69904.184824 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 69810.988142 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 69936.680785 # average overall miss latency system.l2c.overall_avg_miss_latency::total 69923.942601 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 57666 # number of writebacks system.l2c.writebacks::total 57666 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 4266 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 5262 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 6325 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 4967 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 20823 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 1468 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 1421 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2889 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 66168 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 66809 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 132977 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 4266 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 71430 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 6325 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 71776 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 153800 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 4266 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 71430 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 6325 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 71776 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 153800 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 245455500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 322888500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 361377500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312814000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 1242736750 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14681468 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14215421 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 28896889 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3759009578 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3789807300 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 7548816878 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 245455500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 4081898078 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 361377500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 4102621300 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 8791553628 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 245455500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 4081898078 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 361377500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 4102621300 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 8791553628 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349718500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83155205750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83528725500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 167033649750 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8440426101 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8262522003 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 16702948104 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349718500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91595631851 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91791247503 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 183736597854 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027322 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026407 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.016488 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989885 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992318 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991081 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.533876 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.540653 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.537259 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.225664 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.230301 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.101826 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.225664 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.230301 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.101826 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61362.314709 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62978.457822 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 59680.965759 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.814919 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.384562 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56810.083092 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56725.999491 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 56767.838634 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57145.430183 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57145.430183 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.toL2Bus.throughput 52759012 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2471877 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2471877 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution system.toL2Bus.trans_dist::Writeback 596476 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2915 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725028 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753762 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20291 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50582 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7549663 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54751132 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83793442 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28936 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79664 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size::total 138653174 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 138653174 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.throughput 48131413 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 126646806 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7447963 # DTB read hits system.cpu0.dtb.read_misses 7119 # DTB read misses system.cpu0.dtb.write_hits 5549645 # DTB write hits system.cpu0.dtb.write_misses 1815 # DTB write misses system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 7455082 # DTB read accesses system.cpu0.dtb.write_accesses 5551460 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 12997608 # DTB hits system.cpu0.dtb.misses 8934 # DTB misses system.cpu0.dtb.accesses 13006542 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.inst_hits 30500446 # ITB inst hits system.cpu0.itb.inst_misses 3756 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses system.cpu0.itb.hits 30500446 # DTB hits system.cpu0.itb.misses 3756 # DTB misses system.cpu0.itb.accesses 30504202 # DTB accesses system.cpu0.numCycles 2629256644 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 29876886 # Number of instructions committed system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses system.cpu0.num_func_calls 1058651 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls system.cpu0.num_int_insts 34283991 # number of integer instructions system.cpu0.num_fp_insts 4842 # number of float instructions system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written system.cpu0.num_mem_refs 13572889 # number of memory refs system.cpu0.num_load_insts 7771976 # Number of load instructions system.cpu0.num_store_insts 5800913 # Number of store instructions system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles system.cpu0.Branches 5129174 # Number of branches fetched system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 38615997 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 856182 # number of replacements system.cpu0.icache.tags.tagsinuse 510.863139 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 60651276 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 856694 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 70.796896 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 20196898250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.776297 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.086842 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.304251 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.693529 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997780 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 62364664 # Number of tag accesses system.cpu0.icache.tags.data_accesses 62364664 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 30077042 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 30574234 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60651276 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 30077042 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 30574234 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60651276 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 30077042 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 30574234 # number of overall hits system.cpu0.icache.overall_hits::total 60651276 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 423404 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 433290 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856694 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 423404 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 433290 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856694 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 423404 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 433290 # number of overall misses system.cpu0.icache.overall_misses::total 856694 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5772656000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6023287000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 11795943000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 5772656000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 6023287000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 11795943000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 5772656000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 6023287000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 11795943000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 30500446 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 31007524 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61507970 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 30500446 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 31007524 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61507970 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 30500446 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 31007524 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61507970 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013974 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013974 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013974 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13633.919377 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13901.283205 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 13769.143942 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13633.919377 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13901.283205 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 13769.143942 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13633.919377 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13901.283205 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 13769.143942 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 423404 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 433290 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856694 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 423404 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 433290 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856694 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 423404 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 433290 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856694 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4924249000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5154307000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 10078556000 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4924249000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5154307000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 10078556000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4924249000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5154307000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 10078556000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 441046000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 441046000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 441046000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.475997 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.475997 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.475997 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 627683 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.876343 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 23661001 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 628195 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 37.665058 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 147.481748 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 364.394596 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.288050 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.711708 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 97784979 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 97784979 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6545596 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6653610 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13199206 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4917377 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 5057557 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 9974934 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119123 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117066 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236189 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125242 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 122515 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247757 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 11462973 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 11711167 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 23174140 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 11462973 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 11711167 # number of overall hits system.cpu0.dcache.overall_hits::total 23174140 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 186473 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 182643 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 369116 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 125422 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 125003 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250425 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6121 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5448 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11569 # number of LoadLockedReq misses system.cpu0.dcache.demand_misses::cpu0.data 311895 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 307646 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 619541 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 311895 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 307646 # number of overall misses system.cpu0.dcache.overall_misses::total 619541 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2771059250 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705059750 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 5476119000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5617953546 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5645844221 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 11263797767 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82277250 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78257750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 160535000 # number of LoadLockedReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 8389012796 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 8350903971 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 16739916767 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 8389012796 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 8350903971 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 16739916767 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 6732069 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 6836253 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13568322 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5042799 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 5182560 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10225359 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125244 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 122514 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247758 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125242 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 122515 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247757 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 11774868 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 12018813 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 23793681 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 11774868 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 12018813 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 23793681 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027699 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026717 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024872 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024120 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048873 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044468 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046695 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026488 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025597 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026488 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025597 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14860.377910 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14810.640156 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14835.767076 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44792.409195 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373 # average LoadLockedReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 596476 # number of writebacks system.cpu0.dcache.writebacks::total 596476 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186473 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182643 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 369116 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125422 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125003 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 250425 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6121 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5448 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11569 # number of LoadLockedReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 311895 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 307646 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 619541 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 311895 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 307646 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 619541 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2396807750 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2338699250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735507000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5342161454 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5370757779 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10712919233 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70030750 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67311250 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137342000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7738969204 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7709457029 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 15448426233 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7738969204 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7709457029 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 15448426233 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90834275250 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91243928750 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13255943399 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12983118997 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239062396 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027699 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026717 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024872 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024120 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048873 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044468 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046695 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289 # average LoadLockedReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 7552227 # DTB read hits system.cpu1.dtb.read_misses 6971 # DTB read misses system.cpu1.dtb.write_hits 5683121 # DTB write hits system.cpu1.dtb.write_misses 1859 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 7559198 # DTB read accesses system.cpu1.dtb.write_accesses 5684980 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 13235348 # DTB hits system.cpu1.dtb.misses 8830 # DTB misses system.cpu1.dtb.accesses 13244178 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.inst_hits 31007524 # ITB inst hits system.cpu1.itb.inst_misses 3606 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses system.cpu1.itb.hits 31007524 # DTB hits system.cpu1.itb.misses 3606 # DTB misses system.cpu1.itb.accesses 31011130 # DTB accesses system.cpu1.numCycles 2633285995 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 30336967 # Number of instructions committed system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses system.cpu1.num_func_calls 1081754 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls system.cpu1.num_int_insts 34937438 # number of integer instructions system.cpu1.num_fp_insts 5427 # number of float instructions system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written system.cpu1.num_mem_refs 13827657 # number of memory refs system.cpu1.num_load_insts 7892397 # Number of load instructions system.cpu1.num_store_insts 5935260 # Number of store instructions system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles system.cpu1.Branches 5180924 # Number of branches fetched system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 39299664 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------